1 /* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keith (at) tungstengraphics.com> 30 */ 31 32 33 34 #include "brw_context.h" 35 #include "brw_state.h" 36 #include "intel_batchbuffer.h" 37 #include "intel_buffers.h" 38 39 /* This is used to initialize brw->state.atoms[]. We could use this 40 * list directly except for a single atom, brw_constant_buffer, which 41 * has a .dirty value which changes according to the parameters of the 42 * current fragment and vertex programs, and so cannot be a static 43 * value. 44 */ 45 static const struct brw_tracked_state *gen4_atoms[] = 46 { 47 &brw_wm_input_sizes, 48 &brw_vs_prog, /* must do before GS prog, state base address. */ 49 &brw_gs_prog, /* must do before state base address */ 50 &brw_clip_prog, /* must do before state base address */ 51 &brw_sf_prog, /* must do before state base address */ 52 &brw_wm_prog, /* must do before state base address */ 53 54 /* Once all the programs are done, we know how large urb entry 55 * sizes need to be and can decide if we need to change the urb 56 * layout. 57 */ 58 &brw_curbe_offsets, 59 &brw_recalculate_urb_fence, 60 61 &brw_cc_vp, 62 &brw_cc_unit, 63 64 /* Surface state setup. Must come before the VS/WM unit. The binding 65 * table upload must be last. 66 */ 67 &brw_vs_pull_constants, 68 &brw_wm_pull_constants, 69 &brw_renderbuffer_surfaces, 70 &brw_texture_surfaces, 71 &brw_vs_binding_table, 72 &brw_wm_binding_table, 73 74 &brw_samplers, 75 76 /* These set up state for brw_psp_urb_cbs */ 77 &brw_wm_unit, 78 &brw_sf_vp, 79 &brw_sf_unit, 80 &brw_vs_unit, /* always required, enabled or not */ 81 &brw_clip_unit, 82 &brw_gs_unit, 83 84 /* Command packets: 85 */ 86 &brw_invariant_state, 87 &brw_state_base_address, 88 89 &brw_binding_table_pointers, 90 &brw_blend_constant_color, 91 92 &brw_depthbuffer, 93 94 &brw_polygon_stipple, 95 &brw_polygon_stipple_offset, 96 97 &brw_line_stipple, 98 &brw_aa_line_parameters, 99 100 &brw_psp_urb_cbs, 101 102 &brw_drawing_rect, 103 &brw_indices, 104 &brw_index_buffer, 105 &brw_vertices, 106 107 &brw_constant_buffer 108 }; 109 110 static const struct brw_tracked_state *gen6_atoms[] = 111 { 112 &brw_wm_input_sizes, 113 &brw_vs_prog, /* must do before state base address */ 114 &brw_gs_prog, /* must do before state base address */ 115 &brw_wm_prog, /* must do before state base address */ 116 117 &gen6_clip_vp, 118 &gen6_sf_vp, 119 120 /* Command packets: */ 121 &brw_invariant_state, 122 123 /* must do before binding table pointers, cc state ptrs */ 124 &brw_state_base_address, 125 126 &brw_cc_vp, 127 &gen6_viewport_state, /* must do after *_vp stages */ 128 129 &gen6_urb, 130 &gen6_blend_state, /* must do before cc unit */ 131 &gen6_color_calc_state, /* must do before cc unit */ 132 &gen6_depth_stencil_state, /* must do before cc unit */ 133 &gen6_cc_state_pointers, 134 135 &gen6_vs_push_constants, /* Before vs_state */ 136 &gen6_wm_push_constants, /* Before wm_state */ 137 138 /* Surface state setup. Must come before the VS/WM unit. The binding 139 * table upload must be last. 140 */ 141 &brw_vs_pull_constants, 142 &brw_vs_ubo_surfaces, 143 &brw_wm_pull_constants, 144 &brw_wm_ubo_surfaces, 145 &gen6_renderbuffer_surfaces, 146 &brw_texture_surfaces, 147 &gen6_sol_surface, 148 &brw_vs_binding_table, 149 &gen6_gs_binding_table, 150 &brw_wm_binding_table, 151 152 &brw_samplers, 153 &gen6_sampler_state, 154 &gen6_multisample_state, 155 156 &gen6_vs_state, 157 &gen6_gs_state, 158 &gen6_clip_state, 159 &gen6_sf_state, 160 &gen6_wm_state, 161 162 &gen6_scissor_state, 163 164 &gen6_binding_table_pointers, 165 166 &brw_depthbuffer, 167 168 &brw_polygon_stipple, 169 &brw_polygon_stipple_offset, 170 171 &brw_line_stipple, 172 &brw_aa_line_parameters, 173 174 &brw_drawing_rect, 175 176 &gen6_sol_indices, 177 &brw_indices, 178 &brw_index_buffer, 179 &brw_vertices, 180 }; 181 182 const struct brw_tracked_state *gen7_atoms[] = 183 { 184 &brw_wm_input_sizes, 185 &brw_vs_prog, 186 &brw_wm_prog, 187 188 /* Command packets: */ 189 &brw_invariant_state, 190 &gen7_push_constant_alloc, 191 192 /* must do before binding table pointers, cc state ptrs */ 193 &brw_state_base_address, 194 195 &brw_cc_vp, 196 &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */ 197 &gen7_sf_clip_viewport, 198 199 &gen7_urb, 200 &gen6_blend_state, /* must do before cc unit */ 201 &gen6_color_calc_state, /* must do before cc unit */ 202 &gen6_depth_stencil_state, /* must do before cc unit */ 203 &gen7_blend_state_pointer, 204 &gen7_cc_state_pointer, 205 &gen7_depth_stencil_state_pointer, 206 207 &gen6_vs_push_constants, /* Before vs_state */ 208 &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */ 209 210 /* Surface state setup. Must come before the VS/WM unit. The binding 211 * table upload must be last. 212 */ 213 &brw_vs_pull_constants, 214 &brw_vs_ubo_surfaces, 215 &brw_wm_pull_constants, 216 &brw_wm_ubo_surfaces, 217 &gen6_renderbuffer_surfaces, 218 &brw_texture_surfaces, 219 &brw_vs_binding_table, 220 &brw_wm_binding_table, 221 222 &gen7_samplers, 223 &gen6_multisample_state, 224 225 &gen7_disable_stages, 226 &gen7_vs_state, 227 &gen7_sol_state, 228 &gen7_clip_state, 229 &gen7_sbe_state, 230 &gen7_sf_state, 231 &gen7_wm_state, 232 &gen7_ps_state, 233 234 &gen6_scissor_state, 235 236 &gen7_depthbuffer, 237 238 &brw_polygon_stipple, 239 &brw_polygon_stipple_offset, 240 241 &brw_line_stipple, 242 &brw_aa_line_parameters, 243 244 &brw_drawing_rect, 245 246 &brw_indices, 247 &brw_index_buffer, 248 &brw_vertices, 249 250 &haswell_cut_index, 251 }; 252 253 254 void brw_init_state( struct brw_context *brw ) 255 { 256 const struct brw_tracked_state **atoms; 257 int num_atoms; 258 259 brw_init_caches(brw); 260 261 if (brw->intel.gen >= 7) { 262 atoms = gen7_atoms; 263 num_atoms = ARRAY_SIZE(gen7_atoms); 264 } else if (brw->intel.gen == 6) { 265 atoms = gen6_atoms; 266 num_atoms = ARRAY_SIZE(gen6_atoms); 267 } else { 268 atoms = gen4_atoms; 269 num_atoms = ARRAY_SIZE(gen4_atoms); 270 } 271 272 brw->atoms = atoms; 273 brw->num_atoms = num_atoms; 274 275 while (num_atoms--) { 276 assert((*atoms)->dirty.mesa | 277 (*atoms)->dirty.brw | 278 (*atoms)->dirty.cache); 279 assert((*atoms)->emit); 280 atoms++; 281 } 282 } 283 284 285 void brw_destroy_state( struct brw_context *brw ) 286 { 287 brw_destroy_caches(brw); 288 } 289 290 /*********************************************************************** 291 */ 292 293 static GLuint check_state( const struct brw_state_flags *a, 294 const struct brw_state_flags *b ) 295 { 296 return ((a->mesa & b->mesa) | 297 (a->brw & b->brw) | 298 (a->cache & b->cache)) != 0; 299 } 300 301 static void accumulate_state( struct brw_state_flags *a, 302 const struct brw_state_flags *b ) 303 { 304 a->mesa |= b->mesa; 305 a->brw |= b->brw; 306 a->cache |= b->cache; 307 } 308 309 310 static void xor_states( struct brw_state_flags *result, 311 const struct brw_state_flags *a, 312 const struct brw_state_flags *b ) 313 { 314 result->mesa = a->mesa ^ b->mesa; 315 result->brw = a->brw ^ b->brw; 316 result->cache = a->cache ^ b->cache; 317 } 318 319 struct dirty_bit_map { 320 uint32_t bit; 321 char *name; 322 uint32_t count; 323 }; 324 325 #define DEFINE_BIT(name) {name, #name, 0} 326 327 static struct dirty_bit_map mesa_bits[] = { 328 DEFINE_BIT(_NEW_MODELVIEW), 329 DEFINE_BIT(_NEW_PROJECTION), 330 DEFINE_BIT(_NEW_TEXTURE_MATRIX), 331 DEFINE_BIT(_NEW_COLOR), 332 DEFINE_BIT(_NEW_DEPTH), 333 DEFINE_BIT(_NEW_EVAL), 334 DEFINE_BIT(_NEW_FOG), 335 DEFINE_BIT(_NEW_HINT), 336 DEFINE_BIT(_NEW_LIGHT), 337 DEFINE_BIT(_NEW_LINE), 338 DEFINE_BIT(_NEW_PIXEL), 339 DEFINE_BIT(_NEW_POINT), 340 DEFINE_BIT(_NEW_POLYGON), 341 DEFINE_BIT(_NEW_POLYGONSTIPPLE), 342 DEFINE_BIT(_NEW_SCISSOR), 343 DEFINE_BIT(_NEW_STENCIL), 344 DEFINE_BIT(_NEW_TEXTURE), 345 DEFINE_BIT(_NEW_TRANSFORM), 346 DEFINE_BIT(_NEW_VIEWPORT), 347 DEFINE_BIT(_NEW_PACKUNPACK), 348 DEFINE_BIT(_NEW_ARRAY), 349 DEFINE_BIT(_NEW_RENDERMODE), 350 DEFINE_BIT(_NEW_BUFFERS), 351 DEFINE_BIT(_NEW_MULTISAMPLE), 352 DEFINE_BIT(_NEW_TRACK_MATRIX), 353 DEFINE_BIT(_NEW_PROGRAM), 354 DEFINE_BIT(_NEW_PROGRAM_CONSTANTS), 355 {0, 0, 0} 356 }; 357 358 static struct dirty_bit_map brw_bits[] = { 359 DEFINE_BIT(BRW_NEW_URB_FENCE), 360 DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM), 361 DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM), 362 DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS), 363 DEFINE_BIT(BRW_NEW_CURBE_OFFSETS), 364 DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE), 365 DEFINE_BIT(BRW_NEW_PRIMITIVE), 366 DEFINE_BIT(BRW_NEW_CONTEXT), 367 DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS), 368 DEFINE_BIT(BRW_NEW_PROGRAM_CACHE), 369 DEFINE_BIT(BRW_NEW_PSP), 370 DEFINE_BIT(BRW_NEW_SURFACES), 371 DEFINE_BIT(BRW_NEW_INDICES), 372 DEFINE_BIT(BRW_NEW_INDEX_BUFFER), 373 DEFINE_BIT(BRW_NEW_VERTICES), 374 DEFINE_BIT(BRW_NEW_BATCH), 375 DEFINE_BIT(BRW_NEW_VS_CONSTBUF), 376 DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE), 377 DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE), 378 DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE), 379 DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS), 380 {0, 0, 0} 381 }; 382 383 static struct dirty_bit_map cache_bits[] = { 384 DEFINE_BIT(CACHE_NEW_BLEND_STATE), 385 DEFINE_BIT(CACHE_NEW_CC_VP), 386 DEFINE_BIT(CACHE_NEW_CC_UNIT), 387 DEFINE_BIT(CACHE_NEW_WM_PROG), 388 DEFINE_BIT(CACHE_NEW_SAMPLER), 389 DEFINE_BIT(CACHE_NEW_WM_UNIT), 390 DEFINE_BIT(CACHE_NEW_SF_PROG), 391 DEFINE_BIT(CACHE_NEW_SF_VP), 392 DEFINE_BIT(CACHE_NEW_SF_UNIT), 393 DEFINE_BIT(CACHE_NEW_VS_UNIT), 394 DEFINE_BIT(CACHE_NEW_VS_PROG), 395 DEFINE_BIT(CACHE_NEW_GS_UNIT), 396 DEFINE_BIT(CACHE_NEW_GS_PROG), 397 DEFINE_BIT(CACHE_NEW_CLIP_VP), 398 DEFINE_BIT(CACHE_NEW_CLIP_UNIT), 399 DEFINE_BIT(CACHE_NEW_CLIP_PROG), 400 {0, 0, 0} 401 }; 402 403 404 static void 405 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits) 406 { 407 int i; 408 409 for (i = 0; i < 32; i++) { 410 if (bit_map[i].bit == 0) 411 return; 412 413 if (bit_map[i].bit & bits) 414 bit_map[i].count++; 415 } 416 } 417 418 static void 419 brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits) 420 { 421 int i; 422 423 for (i = 0; i < 32; i++) { 424 if (bit_map[i].bit == 0) 425 return; 426 427 fprintf(stderr, "0x%08x: %12d (%s)\n", 428 bit_map[i].bit, bit_map[i].count, bit_map[i].name); 429 } 430 } 431 432 /*********************************************************************** 433 * Emit all state: 434 */ 435 void brw_upload_state(struct brw_context *brw) 436 { 437 struct gl_context *ctx = &brw->intel.ctx; 438 struct intel_context *intel = &brw->intel; 439 struct brw_state_flags *state = &brw->state.dirty; 440 int i; 441 static int dirty_count = 0; 442 443 state->mesa |= brw->intel.NewGLState; 444 brw->intel.NewGLState = 0; 445 446 if (brw->emit_state_always) { 447 state->mesa |= ~0; 448 state->brw |= ~0; 449 state->cache |= ~0; 450 } 451 452 if (brw->fragment_program != ctx->FragmentProgram._Current) { 453 brw->fragment_program = ctx->FragmentProgram._Current; 454 brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM; 455 } 456 457 if (brw->vertex_program != ctx->VertexProgram._Current) { 458 brw->vertex_program = ctx->VertexProgram._Current; 459 brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM; 460 } 461 462 if ((state->mesa | state->cache | state->brw) == 0) 463 return; 464 465 intel_check_front_buffer_rendering(intel); 466 467 if (unlikely(INTEL_DEBUG)) { 468 /* Debug version which enforces various sanity checks on the 469 * state flags which are generated and checked to help ensure 470 * state atoms are ordered correctly in the list. 471 */ 472 struct brw_state_flags examined, prev; 473 memset(&examined, 0, sizeof(examined)); 474 prev = *state; 475 476 for (i = 0; i < brw->num_atoms; i++) { 477 const struct brw_tracked_state *atom = brw->atoms[i]; 478 struct brw_state_flags generated; 479 480 if (check_state(state, &atom->dirty)) { 481 atom->emit(brw); 482 } 483 484 accumulate_state(&examined, &atom->dirty); 485 486 /* generated = (prev ^ state) 487 * if (examined & generated) 488 * fail; 489 */ 490 xor_states(&generated, &prev, state); 491 assert(!check_state(&examined, &generated)); 492 prev = *state; 493 } 494 } 495 else { 496 for (i = 0; i < brw->num_atoms; i++) { 497 const struct brw_tracked_state *atom = brw->atoms[i]; 498 499 if (check_state(state, &atom->dirty)) { 500 atom->emit(brw); 501 } 502 } 503 } 504 505 if (unlikely(INTEL_DEBUG & DEBUG_STATE)) { 506 brw_update_dirty_count(mesa_bits, state->mesa); 507 brw_update_dirty_count(brw_bits, state->brw); 508 brw_update_dirty_count(cache_bits, state->cache); 509 if (dirty_count++ % 1000 == 0) { 510 brw_print_dirty_count(mesa_bits, state->mesa); 511 brw_print_dirty_count(brw_bits, state->brw); 512 brw_print_dirty_count(cache_bits, state->cache); 513 fprintf(stderr, "\n"); 514 } 515 } 516 517 memset(state, 0, sizeof(*state)); 518 } 519
