1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the MCOperandInfo and MCInstrDesc classes, which 11 // are used to describe target instructions and their operands. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_MC_MCINSTRDESC_H 16 #define LLVM_MC_MCINSTRDESC_H 17 18 #include "llvm/MC/MCRegisterInfo.h" 19 #include "llvm/Support/DataTypes.h" 20 #include <string> 21 22 namespace llvm { 23 class MCInst; 24 class MCSubtargetInfo; 25 class FeatureBitset; 26 27 //===----------------------------------------------------------------------===// 28 // Machine Operand Flags and Description 29 //===----------------------------------------------------------------------===// 30 31 namespace MCOI { 32 // Operand constraints 33 enum OperandConstraint { 34 TIED_TO = 0, // Must be allocated the same register as. 35 EARLY_CLOBBER // Operand is an early clobber register operand 36 }; 37 38 /// \brief These are flags set on operands, but should be considered 39 /// private, all access should go through the MCOperandInfo accessors. 40 /// See the accessors for a description of what these are. 41 enum OperandFlags { LookupPtrRegClass = 0, Predicate, OptionalDef }; 42 43 /// \brief Operands are tagged with one of the values of this enum. 44 enum OperandType { 45 OPERAND_UNKNOWN = 0, 46 OPERAND_IMMEDIATE = 1, 47 OPERAND_REGISTER = 2, 48 OPERAND_MEMORY = 3, 49 OPERAND_PCREL = 4, 50 OPERAND_FIRST_TARGET = 5 51 }; 52 } 53 54 /// \brief This holds information about one operand of a machine instruction, 55 /// indicating the register class for register operands, etc. 56 class MCOperandInfo { 57 public: 58 /// \brief This specifies the register class enumeration of the operand 59 /// if the operand is a register. If isLookupPtrRegClass is set, then this is 60 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to 61 /// get a dynamic register class. 62 int16_t RegClass; 63 64 /// \brief These are flags from the MCOI::OperandFlags enum. 65 uint8_t Flags; 66 67 /// \brief Information about the type of the operand. 68 uint8_t OperandType; 69 /// \brief The lower 16 bits are used to specify which constraints are set. 70 /// The higher 16 bits are used to specify the value of constraints (4 bits 71 /// each). 72 uint32_t Constraints; 73 74 /// \brief Set if this operand is a pointer value and it requires a callback 75 /// to look up its register class. 76 bool isLookupPtrRegClass() const { 77 return Flags & (1 << MCOI::LookupPtrRegClass); 78 } 79 80 /// \brief Set if this is one of the operands that made up of the predicate 81 /// operand that controls an isPredicable() instruction. 82 bool isPredicate() const { return Flags & (1 << MCOI::Predicate); } 83 84 /// \brief Set if this operand is a optional def. 85 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } 86 }; 87 88 //===----------------------------------------------------------------------===// 89 // Machine Instruction Flags and Description 90 //===----------------------------------------------------------------------===// 91 92 namespace MCID { 93 /// \brief These should be considered private to the implementation of the 94 /// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc, 95 /// not use these directly. These all correspond to bitfields in the 96 /// MCInstrDesc::Flags field. 97 enum Flag { 98 Variadic = 0, 99 HasOptionalDef, 100 Pseudo, 101 Return, 102 Call, 103 Barrier, 104 Terminator, 105 Branch, 106 IndirectBranch, 107 Compare, 108 MoveImm, 109 Bitcast, 110 Select, 111 DelaySlot, 112 FoldableAsLoad, 113 MayLoad, 114 MayStore, 115 Predicable, 116 NotDuplicable, 117 UnmodeledSideEffects, 118 Commutable, 119 ConvertibleTo3Addr, 120 UsesCustomInserter, 121 HasPostISelHook, 122 Rematerializable, 123 CheapAsAMove, 124 ExtraSrcRegAllocReq, 125 ExtraDefRegAllocReq, 126 RegSequence, 127 ExtractSubreg, 128 InsertSubreg, 129 Convergent 130 }; 131 } 132 133 /// \brief Describe properties that are true of each instruction in the target 134 /// description file. This captures information about side effects, register 135 /// use and many other things. There is one instance of this struct for each 136 /// target instruction class, and the MachineInstr class points to this struct 137 /// directly to describe itself. 138 class MCInstrDesc { 139 public: 140 unsigned short Opcode; // The opcode number 141 unsigned short NumOperands; // Num of args (may be more if variable_ops) 142 unsigned char NumDefs; // Num of args that are definitions 143 unsigned char Size; // Number of bytes in encoding. 144 unsigned short SchedClass; // enum identifying instr sched class 145 uint64_t Flags; // Flags identifying machine instr class 146 uint64_t TSFlags; // Target Specific Flag values 147 const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr 148 const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr 149 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands 150 // Subtarget feature that this is deprecated on, if any 151 // -1 implies this is not deprecated by any single feature. It may still be 152 // deprecated due to a "complex" reason, below. 153 int64_t DeprecatedFeature; 154 155 // A complex method to determine is a certain is deprecated or not, and return 156 // the reason for deprecation. 157 bool (*ComplexDeprecationInfo)(MCInst &, const MCSubtargetInfo &, 158 std::string &); 159 160 /// \brief Returns the value of the specific constraint if 161 /// it is set. Returns -1 if it is not set. 162 int getOperandConstraint(unsigned OpNum, 163 MCOI::OperandConstraint Constraint) const { 164 if (OpNum < NumOperands && 165 (OpInfo[OpNum].Constraints & (1 << Constraint))) { 166 unsigned Pos = 16 + Constraint * 4; 167 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 168 } 169 return -1; 170 } 171 172 /// \brief Returns true if a certain instruction is deprecated and if so 173 /// returns the reason in \p Info. 174 bool getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI, 175 std::string &Info) const; 176 177 /// \brief Return the opcode number for this descriptor. 178 unsigned getOpcode() const { return Opcode; } 179 180 /// \brief Return the number of declared MachineOperands for this 181 /// MachineInstruction. Note that variadic (isVariadic() returns true) 182 /// instructions may have additional operands at the end of the list, and note 183 /// that the machine instruction may include implicit register def/uses as 184 /// well. 185 unsigned getNumOperands() const { return NumOperands; } 186 187 /// \brief Return the number of MachineOperands that are register 188 /// definitions. Register definitions always occur at the start of the 189 /// machine operand list. This is the number of "outs" in the .td file, 190 /// and does not include implicit defs. 191 unsigned getNumDefs() const { return NumDefs; } 192 193 /// \brief Return flags of this instruction. 194 unsigned getFlags() const { return Flags; } 195 196 /// \brief Return true if this instruction can have a variable number of 197 /// operands. In this case, the variable operands will be after the normal 198 /// operands but before the implicit definitions and uses (if any are 199 /// present). 200 bool isVariadic() const { return Flags & (1 << MCID::Variadic); } 201 202 /// \brief Set if this instruction has an optional definition, e.g. 203 /// ARM instructions which can set condition code if 's' bit is set. 204 bool hasOptionalDef() const { return Flags & (1 << MCID::HasOptionalDef); } 205 206 /// \brief Return true if this is a pseudo instruction that doesn't 207 /// correspond to a real machine instruction. 208 bool isPseudo() const { return Flags & (1 << MCID::Pseudo); } 209 210 /// \brief Return true if the instruction is a return. 211 bool isReturn() const { return Flags & (1 << MCID::Return); } 212 213 /// \brief Return true if the instruction is a call. 214 bool isCall() const { return Flags & (1 << MCID::Call); } 215 216 /// \brief Returns true if the specified instruction stops control flow 217 /// from executing the instruction immediately following it. Examples include 218 /// unconditional branches and return instructions. 219 bool isBarrier() const { return Flags & (1 << MCID::Barrier); } 220 221 /// \brief Returns true if this instruction part of the terminator for 222 /// a basic block. Typically this is things like return and branch 223 /// instructions. 224 /// 225 /// Various passes use this to insert code into the bottom of a basic block, 226 /// but before control flow occurs. 227 bool isTerminator() const { return Flags & (1 << MCID::Terminator); } 228 229 /// \brief Returns true if this is a conditional, unconditional, or 230 /// indirect branch. Predicates below can be used to discriminate between 231 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to 232 /// get more information. 233 bool isBranch() const { return Flags & (1 << MCID::Branch); } 234 235 /// \brief Return true if this is an indirect branch, such as a 236 /// branch through a register. 237 bool isIndirectBranch() const { return Flags & (1 << MCID::IndirectBranch); } 238 239 /// \brief Return true if this is a branch which may fall 240 /// through to the next instruction or may transfer control flow to some other 241 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more 242 /// information about this branch. 243 bool isConditionalBranch() const { 244 return isBranch() & !isBarrier() & !isIndirectBranch(); 245 } 246 247 /// \brief Return true if this is a branch which always 248 /// transfers control flow to some other block. The 249 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information 250 /// about this branch. 251 bool isUnconditionalBranch() const { 252 return isBranch() & isBarrier() & !isIndirectBranch(); 253 } 254 255 /// \brief Return true if this is a branch or an instruction which directly 256 /// writes to the program counter. Considered 'may' affect rather than 257 /// 'does' affect as things like predication are not taken into account. 258 bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const; 259 260 /// \brief Return true if this instruction has a predicate operand 261 /// that controls execution. It may be set to 'always', or may be set to other 262 /// values. There are various methods in TargetInstrInfo that can be used to 263 /// control and modify the predicate in this instruction. 264 bool isPredicable() const { return Flags & (1 << MCID::Predicable); } 265 266 /// \brief Return true if this instruction is a comparison. 267 bool isCompare() const { return Flags & (1 << MCID::Compare); } 268 269 /// \brief Return true if this instruction is a move immediate 270 /// (including conditional moves) instruction. 271 bool isMoveImmediate() const { return Flags & (1 << MCID::MoveImm); } 272 273 /// \brief Return true if this instruction is a bitcast instruction. 274 bool isBitcast() const { return Flags & (1 << MCID::Bitcast); } 275 276 /// \brief Return true if this is a select instruction. 277 bool isSelect() const { return Flags & (1 << MCID::Select); } 278 279 /// \brief Return true if this instruction cannot be safely 280 /// duplicated. For example, if the instruction has a unique labels attached 281 /// to it, duplicating it would cause multiple definition errors. 282 bool isNotDuplicable() const { return Flags & (1 << MCID::NotDuplicable); } 283 284 /// \brief Returns true if the specified instruction has a delay slot which 285 /// must be filled by the code generator. 286 bool hasDelaySlot() const { return Flags & (1 << MCID::DelaySlot); } 287 288 /// \brief Return true for instructions that can be folded as memory operands 289 /// in other instructions. The most common use for this is instructions that 290 /// are simple loads from memory that don't modify the loaded value in any 291 /// way, but it can also be used for instructions that can be expressed as 292 /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be 293 /// folded when it is beneficial. This should only be set on instructions 294 /// that return a value in their only virtual register definition. 295 bool canFoldAsLoad() const { return Flags & (1 << MCID::FoldableAsLoad); } 296 297 /// \brief Return true if this instruction behaves 298 /// the same way as the generic REG_SEQUENCE instructions. 299 /// E.g., on ARM, 300 /// dX VMOVDRR rY, rZ 301 /// is equivalent to 302 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1. 303 /// 304 /// Note that for the optimizers to be able to take advantage of 305 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be 306 /// override accordingly. 307 bool isRegSequenceLike() const { return Flags & (1 << MCID::RegSequence); } 308 309 /// \brief Return true if this instruction behaves 310 /// the same way as the generic EXTRACT_SUBREG instructions. 311 /// E.g., on ARM, 312 /// rX, rY VMOVRRD dZ 313 /// is equivalent to two EXTRACT_SUBREG: 314 /// rX = EXTRACT_SUBREG dZ, ssub_0 315 /// rY = EXTRACT_SUBREG dZ, ssub_1 316 /// 317 /// Note that for the optimizers to be able to take advantage of 318 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be 319 /// override accordingly. 320 bool isExtractSubregLike() const { 321 return Flags & (1 << MCID::ExtractSubreg); 322 } 323 324 /// \brief Return true if this instruction behaves 325 /// the same way as the generic INSERT_SUBREG instructions. 326 /// E.g., on ARM, 327 /// dX = VSETLNi32 dY, rZ, Imm 328 /// is equivalent to a INSERT_SUBREG: 329 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm) 330 /// 331 /// Note that for the optimizers to be able to take advantage of 332 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be 333 /// override accordingly. 334 bool isInsertSubregLike() const { return Flags & (1 << MCID::InsertSubreg); } 335 336 337 /// \brief Return true if this instruction is convergent. 338 /// 339 /// Convergent instructions may not be made control-dependent on any 340 /// additional values. 341 bool isConvergent() const { return Flags & (1 << MCID::Convergent); } 342 343 //===--------------------------------------------------------------------===// 344 // Side Effect Analysis 345 //===--------------------------------------------------------------------===// 346 347 /// \brief Return true if this instruction could possibly read memory. 348 /// Instructions with this flag set are not necessarily simple load 349 /// instructions, they may load a value and modify it, for example. 350 bool mayLoad() const { return Flags & (1 << MCID::MayLoad); } 351 352 /// \brief Return true if this instruction could possibly modify memory. 353 /// Instructions with this flag set are not necessarily simple store 354 /// instructions, they may store a modified value based on their operands, or 355 /// may not actually modify anything, for example. 356 bool mayStore() const { return Flags & (1 << MCID::MayStore); } 357 358 /// \brief Return true if this instruction has side 359 /// effects that are not modeled by other flags. This does not return true 360 /// for instructions whose effects are captured by: 361 /// 362 /// 1. Their operand list and implicit definition/use list. Register use/def 363 /// info is explicit for instructions. 364 /// 2. Memory accesses. Use mayLoad/mayStore. 365 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch. 366 /// 367 /// Examples of side effects would be modifying 'invisible' machine state like 368 /// a control register, flushing a cache, modifying a register invisible to 369 /// LLVM, etc. 370 bool hasUnmodeledSideEffects() const { 371 return Flags & (1 << MCID::UnmodeledSideEffects); 372 } 373 374 //===--------------------------------------------------------------------===// 375 // Flags that indicate whether an instruction can be modified by a method. 376 //===--------------------------------------------------------------------===// 377 378 /// \brief Return true if this may be a 2- or 3-address instruction (of the 379 /// form "X = op Y, Z, ..."), which produces the same result if Y and Z are 380 /// exchanged. If this flag is set, then the 381 /// TargetInstrInfo::commuteInstruction method may be used to hack on the 382 /// instruction. 383 /// 384 /// Note that this flag may be set on instructions that are only commutable 385 /// sometimes. In these cases, the call to commuteInstruction will fail. 386 /// Also note that some instructions require non-trivial modification to 387 /// commute them. 388 bool isCommutable() const { return Flags & (1 << MCID::Commutable); } 389 390 /// \brief Return true if this is a 2-address instruction which can be changed 391 /// into a 3-address instruction if needed. Doing this transformation can be 392 /// profitable in the register allocator, because it means that the 393 /// instruction can use a 2-address form if possible, but degrade into a less 394 /// efficient form if the source and dest register cannot be assigned to the 395 /// same register. For example, this allows the x86 backend to turn a "shl 396 /// reg, 3" instruction into an LEA instruction, which is the same speed as 397 /// the shift but has bigger code size. 398 /// 399 /// If this returns true, then the target must implement the 400 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which 401 /// is allowed to fail if the transformation isn't valid for this specific 402 /// instruction (e.g. shl reg, 4 on x86). 403 /// 404 bool isConvertibleTo3Addr() const { 405 return Flags & (1 << MCID::ConvertibleTo3Addr); 406 } 407 408 /// \brief Return true if this instruction requires custom insertion support 409 /// when the DAG scheduler is inserting it into a machine basic block. If 410 /// this is true for the instruction, it basically means that it is a pseudo 411 /// instruction used at SelectionDAG time that is expanded out into magic code 412 /// by the target when MachineInstrs are formed. 413 /// 414 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method 415 /// is used to insert this into the MachineBasicBlock. 416 bool usesCustomInsertionHook() const { 417 return Flags & (1 << MCID::UsesCustomInserter); 418 } 419 420 /// \brief Return true if this instruction requires *adjustment* after 421 /// instruction selection by calling a target hook. For example, this can be 422 /// used to fill in ARM 's' optional operand depending on whether the 423 /// conditional flag register is used. 424 bool hasPostISelHook() const { return Flags & (1 << MCID::HasPostISelHook); } 425 426 /// \brief Returns true if this instruction is a candidate for remat. This 427 /// flag is only used in TargetInstrInfo method isTriviallyRematerializable. 428 /// 429 /// If this flag is set, the isReallyTriviallyReMaterializable() 430 /// or isReallyTriviallyReMaterializableGeneric methods are called to verify 431 /// the instruction is really rematable. 432 bool isRematerializable() const { 433 return Flags & (1 << MCID::Rematerializable); 434 } 435 436 /// \brief Returns true if this instruction has the same cost (or less) than a 437 /// move instruction. This is useful during certain types of optimizations 438 /// (e.g., remat during two-address conversion or machine licm) where we would 439 /// like to remat or hoist the instruction, but not if it costs more than 440 /// moving the instruction into the appropriate register. Note, we are not 441 /// marking copies from and to the same register class with this flag. 442 /// 443 /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove 444 /// for different subtargets. 445 bool isAsCheapAsAMove() const { return Flags & (1 << MCID::CheapAsAMove); } 446 447 /// \brief Returns true if this instruction source operands have special 448 /// register allocation requirements that are not captured by the operand 449 /// register classes. e.g. ARM::STRD's two source registers must be an even / 450 /// odd pair, ARM::STM registers have to be in ascending order. Post-register 451 /// allocation passes should not attempt to change allocations for sources of 452 /// instructions with this flag. 453 bool hasExtraSrcRegAllocReq() const { 454 return Flags & (1 << MCID::ExtraSrcRegAllocReq); 455 } 456 457 /// \brief Returns true if this instruction def operands have special register 458 /// allocation requirements that are not captured by the operand register 459 /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair, 460 /// ARM::LDM registers have to be in ascending order. Post-register 461 /// allocation passes should not attempt to change allocations for definitions 462 /// of instructions with this flag. 463 bool hasExtraDefRegAllocReq() const { 464 return Flags & (1 << MCID::ExtraDefRegAllocReq); 465 } 466 467 /// \brief Return a list of registers that are potentially read by any 468 /// instance of this machine instruction. For example, on X86, the "adc" 469 /// instruction adds two register operands and adds the carry bit in from the 470 /// flags register. In this case, the instruction is marked as implicitly 471 /// reading the flags. Likewise, the variable shift instruction on X86 is 472 /// marked as implicitly reading the 'CL' register, which it always does. 473 /// 474 /// This method returns null if the instruction has no implicit uses. 475 const MCPhysReg *getImplicitUses() const { return ImplicitUses; } 476 477 /// \brief Return the number of implicit uses this instruction has. 478 unsigned getNumImplicitUses() const { 479 if (!ImplicitUses) 480 return 0; 481 unsigned i = 0; 482 for (; ImplicitUses[i]; ++i) /*empty*/ 483 ; 484 return i; 485 } 486 487 /// \brief Return a list of registers that are potentially written by any 488 /// instance of this machine instruction. For example, on X86, many 489 /// instructions implicitly set the flags register. In this case, they are 490 /// marked as setting the FLAGS. Likewise, many instructions always deposit 491 /// their result in a physical register. For example, the X86 divide 492 /// instruction always deposits the quotient and remainder in the EAX/EDX 493 /// registers. For that instruction, this will return a list containing the 494 /// EAX/EDX/EFLAGS registers. 495 /// 496 /// This method returns null if the instruction has no implicit defs. 497 const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; } 498 499 /// \brief Return the number of implicit defs this instruct has. 500 unsigned getNumImplicitDefs() const { 501 if (!ImplicitDefs) 502 return 0; 503 unsigned i = 0; 504 for (; ImplicitDefs[i]; ++i) /*empty*/ 505 ; 506 return i; 507 } 508 509 /// \brief Return true if this instruction implicitly 510 /// uses the specified physical register. 511 bool hasImplicitUseOfPhysReg(unsigned Reg) const { 512 if (const MCPhysReg *ImpUses = ImplicitUses) 513 for (; *ImpUses; ++ImpUses) 514 if (*ImpUses == Reg) 515 return true; 516 return false; 517 } 518 519 /// \brief Return true if this instruction implicitly 520 /// defines the specified physical register. 521 bool hasImplicitDefOfPhysReg(unsigned Reg, 522 const MCRegisterInfo *MRI = nullptr) const; 523 524 /// \brief Return the scheduling class for this instruction. The 525 /// scheduling class is an index into the InstrItineraryData table. This 526 /// returns zero if there is no known scheduling information for the 527 /// instruction. 528 unsigned getSchedClass() const { return SchedClass; } 529 530 /// \brief Return the number of bytes in the encoding of this instruction, 531 /// or zero if the encoding size cannot be known from the opcode. 532 unsigned getSize() const { return Size; } 533 534 /// \brief Find the index of the first operand in the 535 /// operand list that is used to represent the predicate. It returns -1 if 536 /// none is found. 537 int findFirstPredOperandIdx() const { 538 if (isPredicable()) { 539 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 540 if (OpInfo[i].isPredicate()) 541 return i; 542 } 543 return -1; 544 } 545 546 private: 547 548 /// \brief Return true if this instruction defines the specified physical 549 /// register, either explicitly or implicitly. 550 bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg, 551 const MCRegisterInfo &RI) const; 552 }; 553 554 } // end namespace llvm 555 556 #endif 557
