1 //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// \brief This file is part of the XCore Disassembler. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #include "XCore.h" 16 #include "XCoreRegisterInfo.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/TargetRegistry.h" 23 24 using namespace llvm; 25 26 #define DEBUG_TYPE "xcore-disassembler" 27 28 typedef MCDisassembler::DecodeStatus DecodeStatus; 29 30 namespace { 31 32 /// \brief A disassembler class for XCore. 33 class XCoreDisassembler : public MCDisassembler { 34 public: 35 XCoreDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 36 MCDisassembler(STI, Ctx) {} 37 38 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 39 ArrayRef<uint8_t> Bytes, uint64_t Address, 40 raw_ostream &VStream, 41 raw_ostream &CStream) const override; 42 }; 43 } 44 45 static bool readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 46 uint64_t &Size, uint16_t &Insn) { 47 // We want to read exactly 2 Bytes of data. 48 if (Bytes.size() < 2) { 49 Size = 0; 50 return false; 51 } 52 // Encoded as a little-endian 16-bit word in the stream. 53 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); 54 return true; 55 } 56 57 static bool readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 58 uint64_t &Size, uint32_t &Insn) { 59 // We want to read exactly 4 Bytes of data. 60 if (Bytes.size() < 4) { 61 Size = 0; 62 return false; 63 } 64 // Encoded as a little-endian 32-bit word in the stream. 65 Insn = 66 (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | (Bytes[3] << 24); 67 return true; 68 } 69 70 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 71 const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D); 72 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 73 return *(RegInfo->getRegClass(RC).begin() + RegNo); 74 } 75 76 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, 77 unsigned RegNo, 78 uint64_t Address, 79 const void *Decoder); 80 81 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, 82 unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 86 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, 87 uint64_t Address, const void *Decoder); 88 89 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val, 90 uint64_t Address, const void *Decoder); 91 92 static DecodeStatus Decode2RInstruction(MCInst &Inst, 93 unsigned Insn, 94 uint64_t Address, 95 const void *Decoder); 96 97 static DecodeStatus Decode2RImmInstruction(MCInst &Inst, 98 unsigned Insn, 99 uint64_t Address, 100 const void *Decoder); 101 102 static DecodeStatus DecodeR2RInstruction(MCInst &Inst, 103 unsigned Insn, 104 uint64_t Address, 105 const void *Decoder); 106 107 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, 108 unsigned Insn, 109 uint64_t Address, 110 const void *Decoder); 111 112 static DecodeStatus DecodeRUSInstruction(MCInst &Inst, 113 unsigned Insn, 114 uint64_t Address, 115 const void *Decoder); 116 117 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, 118 unsigned Insn, 119 uint64_t Address, 120 const void *Decoder); 121 122 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst, 123 unsigned Insn, 124 uint64_t Address, 125 const void *Decoder); 126 127 static DecodeStatus DecodeL2RInstruction(MCInst &Inst, 128 unsigned Insn, 129 uint64_t Address, 130 const void *Decoder); 131 132 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst, 133 unsigned Insn, 134 uint64_t Address, 135 const void *Decoder); 136 137 static DecodeStatus Decode3RInstruction(MCInst &Inst, 138 unsigned Insn, 139 uint64_t Address, 140 const void *Decoder); 141 142 static DecodeStatus Decode3RImmInstruction(MCInst &Inst, 143 unsigned Insn, 144 uint64_t Address, 145 const void *Decoder); 146 147 static DecodeStatus Decode2RUSInstruction(MCInst &Inst, 148 unsigned Insn, 149 uint64_t Address, 150 const void *Decoder); 151 152 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst, 153 unsigned Insn, 154 uint64_t Address, 155 const void *Decoder); 156 157 static DecodeStatus DecodeL3RInstruction(MCInst &Inst, 158 unsigned Insn, 159 uint64_t Address, 160 const void *Decoder); 161 162 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst, 163 unsigned Insn, 164 uint64_t Address, 165 const void *Decoder); 166 167 static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst, 168 unsigned Insn, 169 uint64_t Address, 170 const void *Decoder); 171 172 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst, 173 unsigned Insn, 174 uint64_t Address, 175 const void *Decoder); 176 177 static DecodeStatus DecodeL6RInstruction(MCInst &Inst, 178 unsigned Insn, 179 uint64_t Address, 180 const void *Decoder); 181 182 static DecodeStatus DecodeL5RInstruction(MCInst &Inst, 183 unsigned Insn, 184 uint64_t Address, 185 const void *Decoder); 186 187 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst, 188 unsigned Insn, 189 uint64_t Address, 190 const void *Decoder); 191 192 static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, 193 unsigned Insn, 194 uint64_t Address, 195 const void *Decoder); 196 197 #include "XCoreGenDisassemblerTables.inc" 198 199 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, 200 unsigned RegNo, 201 uint64_t Address, 202 const void *Decoder) 203 { 204 if (RegNo > 11) 205 return MCDisassembler::Fail; 206 unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo); 207 Inst.addOperand(MCOperand::createReg(Reg)); 208 return MCDisassembler::Success; 209 } 210 211 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, 212 unsigned RegNo, 213 uint64_t Address, 214 const void *Decoder) 215 { 216 if (RegNo > 15) 217 return MCDisassembler::Fail; 218 unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo); 219 Inst.addOperand(MCOperand::createReg(Reg)); 220 return MCDisassembler::Success; 221 } 222 223 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, 224 uint64_t Address, const void *Decoder) { 225 if (Val > 11) 226 return MCDisassembler::Fail; 227 static const unsigned Values[] = { 228 32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32 229 }; 230 Inst.addOperand(MCOperand::createImm(Values[Val])); 231 return MCDisassembler::Success; 232 } 233 234 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder) { 236 Inst.addOperand(MCOperand::createImm(-(int64_t)Val)); 237 return MCDisassembler::Success; 238 } 239 240 static DecodeStatus 241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { 242 unsigned Combined = fieldFromInstruction(Insn, 6, 5); 243 if (Combined < 27) 244 return MCDisassembler::Fail; 245 if (fieldFromInstruction(Insn, 5, 1)) { 246 if (Combined == 31) 247 return MCDisassembler::Fail; 248 Combined += 5; 249 } 250 Combined -= 27; 251 unsigned Op1High = Combined % 3; 252 unsigned Op2High = Combined / 3; 253 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2); 254 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); 255 return MCDisassembler::Success; 256 } 257 258 static DecodeStatus 259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, 260 unsigned &Op3) { 261 unsigned Combined = fieldFromInstruction(Insn, 6, 5); 262 if (Combined >= 27) 263 return MCDisassembler::Fail; 264 265 unsigned Op1High = Combined % 3; 266 unsigned Op2High = (Combined / 3) % 3; 267 unsigned Op3High = Combined / 9; 268 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2); 269 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); 270 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2); 271 return MCDisassembler::Success; 272 } 273 274 static DecodeStatus 275 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, 276 const void *Decoder) { 277 // Try and decode as a 3R instruction. 278 unsigned Opcode = fieldFromInstruction(Insn, 11, 5); 279 switch (Opcode) { 280 case 0x0: 281 Inst.setOpcode(XCore::STW_2rus); 282 return Decode2RUSInstruction(Inst, Insn, Address, Decoder); 283 case 0x1: 284 Inst.setOpcode(XCore::LDW_2rus); 285 return Decode2RUSInstruction(Inst, Insn, Address, Decoder); 286 case 0x2: 287 Inst.setOpcode(XCore::ADD_3r); 288 return Decode3RInstruction(Inst, Insn, Address, Decoder); 289 case 0x3: 290 Inst.setOpcode(XCore::SUB_3r); 291 return Decode3RInstruction(Inst, Insn, Address, Decoder); 292 case 0x4: 293 Inst.setOpcode(XCore::SHL_3r); 294 return Decode3RInstruction(Inst, Insn, Address, Decoder); 295 case 0x5: 296 Inst.setOpcode(XCore::SHR_3r); 297 return Decode3RInstruction(Inst, Insn, Address, Decoder); 298 case 0x6: 299 Inst.setOpcode(XCore::EQ_3r); 300 return Decode3RInstruction(Inst, Insn, Address, Decoder); 301 case 0x7: 302 Inst.setOpcode(XCore::AND_3r); 303 return Decode3RInstruction(Inst, Insn, Address, Decoder); 304 case 0x8: 305 Inst.setOpcode(XCore::OR_3r); 306 return Decode3RInstruction(Inst, Insn, Address, Decoder); 307 case 0x9: 308 Inst.setOpcode(XCore::LDW_3r); 309 return Decode3RInstruction(Inst, Insn, Address, Decoder); 310 case 0x10: 311 Inst.setOpcode(XCore::LD16S_3r); 312 return Decode3RInstruction(Inst, Insn, Address, Decoder); 313 case 0x11: 314 Inst.setOpcode(XCore::LD8U_3r); 315 return Decode3RInstruction(Inst, Insn, Address, Decoder); 316 case 0x12: 317 Inst.setOpcode(XCore::ADD_2rus); 318 return Decode2RUSInstruction(Inst, Insn, Address, Decoder); 319 case 0x13: 320 Inst.setOpcode(XCore::SUB_2rus); 321 return Decode2RUSInstruction(Inst, Insn, Address, Decoder); 322 case 0x14: 323 Inst.setOpcode(XCore::SHL_2rus); 324 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder); 325 case 0x15: 326 Inst.setOpcode(XCore::SHR_2rus); 327 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder); 328 case 0x16: 329 Inst.setOpcode(XCore::EQ_2rus); 330 return Decode2RUSInstruction(Inst, Insn, Address, Decoder); 331 case 0x17: 332 Inst.setOpcode(XCore::TSETR_3r); 333 return Decode3RImmInstruction(Inst, Insn, Address, Decoder); 334 case 0x18: 335 Inst.setOpcode(XCore::LSS_3r); 336 return Decode3RInstruction(Inst, Insn, Address, Decoder); 337 case 0x19: 338 Inst.setOpcode(XCore::LSU_3r); 339 return Decode3RInstruction(Inst, Insn, Address, Decoder); 340 } 341 return MCDisassembler::Fail; 342 } 343 344 static DecodeStatus 345 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 346 const void *Decoder) { 347 unsigned Op1, Op2; 348 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 349 if (S != MCDisassembler::Success) 350 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 351 352 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 353 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 354 return S; 355 } 356 357 static DecodeStatus 358 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 359 const void *Decoder) { 360 unsigned Op1, Op2; 361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 362 if (S != MCDisassembler::Success) 363 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 364 365 Inst.addOperand(MCOperand::createImm(Op1)); 366 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 367 return S; 368 } 369 370 static DecodeStatus 371 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 372 const void *Decoder) { 373 unsigned Op1, Op2; 374 DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1); 375 if (S != MCDisassembler::Success) 376 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 377 378 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 379 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 380 return S; 381 } 382 383 static DecodeStatus 384 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 385 const void *Decoder) { 386 unsigned Op1, Op2; 387 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 388 if (S != MCDisassembler::Success) 389 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 390 391 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 392 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 393 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 394 return S; 395 } 396 397 static DecodeStatus 398 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 399 const void *Decoder) { 400 unsigned Op1, Op2; 401 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 402 if (S != MCDisassembler::Success) 403 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 404 405 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 406 Inst.addOperand(MCOperand::createImm(Op2)); 407 return S; 408 } 409 410 static DecodeStatus 411 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 412 const void *Decoder) { 413 unsigned Op1, Op2; 414 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 415 if (S != MCDisassembler::Success) 416 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 417 418 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 419 DecodeBitpOperand(Inst, Op2, Address, Decoder); 420 return S; 421 } 422 423 static DecodeStatus 424 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 425 const void *Decoder) { 426 unsigned Op1, Op2; 427 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 428 if (S != MCDisassembler::Success) 429 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 430 431 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 432 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 433 DecodeBitpOperand(Inst, Op2, Address, Decoder); 434 return S; 435 } 436 437 static DecodeStatus 438 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, 439 const void *Decoder) { 440 // Try and decode as a L3R / L2RUS instruction. 441 unsigned Opcode = fieldFromInstruction(Insn, 16, 4) | 442 fieldFromInstruction(Insn, 27, 5) << 4; 443 switch (Opcode) { 444 case 0x0c: 445 Inst.setOpcode(XCore::STW_l3r); 446 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 447 case 0x1c: 448 Inst.setOpcode(XCore::XOR_l3r); 449 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 450 case 0x2c: 451 Inst.setOpcode(XCore::ASHR_l3r); 452 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 453 case 0x3c: 454 Inst.setOpcode(XCore::LDAWF_l3r); 455 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 456 case 0x4c: 457 Inst.setOpcode(XCore::LDAWB_l3r); 458 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 459 case 0x5c: 460 Inst.setOpcode(XCore::LDA16F_l3r); 461 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 462 case 0x6c: 463 Inst.setOpcode(XCore::LDA16B_l3r); 464 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 465 case 0x7c: 466 Inst.setOpcode(XCore::MUL_l3r); 467 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 468 case 0x8c: 469 Inst.setOpcode(XCore::DIVS_l3r); 470 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 471 case 0x9c: 472 Inst.setOpcode(XCore::DIVU_l3r); 473 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 474 case 0x10c: 475 Inst.setOpcode(XCore::ST16_l3r); 476 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 477 case 0x11c: 478 Inst.setOpcode(XCore::ST8_l3r); 479 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 480 case 0x12c: 481 Inst.setOpcode(XCore::ASHR_l2rus); 482 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); 483 case 0x12d: 484 Inst.setOpcode(XCore::OUTPW_l2rus); 485 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); 486 case 0x12e: 487 Inst.setOpcode(XCore::INPW_l2rus); 488 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); 489 case 0x13c: 490 Inst.setOpcode(XCore::LDAWF_l2rus); 491 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder); 492 case 0x14c: 493 Inst.setOpcode(XCore::LDAWB_l2rus); 494 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder); 495 case 0x15c: 496 Inst.setOpcode(XCore::CRC_l3r); 497 return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder); 498 case 0x18c: 499 Inst.setOpcode(XCore::REMS_l3r); 500 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 501 case 0x19c: 502 Inst.setOpcode(XCore::REMU_l3r); 503 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 504 } 505 return MCDisassembler::Fail; 506 } 507 508 static DecodeStatus 509 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 510 const void *Decoder) { 511 unsigned Op1, Op2; 512 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16), 513 Op1, Op2); 514 if (S != MCDisassembler::Success) 515 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); 516 517 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 518 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 519 return S; 520 } 521 522 static DecodeStatus 523 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 524 const void *Decoder) { 525 unsigned Op1, Op2; 526 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16), 527 Op1, Op2); 528 if (S != MCDisassembler::Success) 529 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); 530 531 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 532 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 533 return S; 534 } 535 536 static DecodeStatus 537 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 538 const void *Decoder) { 539 unsigned Op1, Op2, Op3; 540 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 541 if (S == MCDisassembler::Success) { 542 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 543 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 544 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 545 } 546 return S; 547 } 548 549 static DecodeStatus 550 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 551 const void *Decoder) { 552 unsigned Op1, Op2, Op3; 553 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 554 if (S == MCDisassembler::Success) { 555 Inst.addOperand(MCOperand::createImm(Op1)); 556 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 557 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 558 } 559 return S; 560 } 561 562 static DecodeStatus 563 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 564 const void *Decoder) { 565 unsigned Op1, Op2, Op3; 566 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 567 if (S == MCDisassembler::Success) { 568 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 569 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 570 Inst.addOperand(MCOperand::createImm(Op3)); 571 } 572 return S; 573 } 574 575 static DecodeStatus 576 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 577 const void *Decoder) { 578 unsigned Op1, Op2, Op3; 579 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 580 if (S == MCDisassembler::Success) { 581 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 582 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 583 DecodeBitpOperand(Inst, Op3, Address, Decoder); 584 } 585 return S; 586 } 587 588 static DecodeStatus 589 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 590 const void *Decoder) { 591 unsigned Op1, Op2, Op3; 592 DecodeStatus S = 593 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 594 if (S == MCDisassembler::Success) { 595 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 596 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 597 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 598 } 599 return S; 600 } 601 602 static DecodeStatus 603 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 604 const void *Decoder) { 605 unsigned Op1, Op2, Op3; 606 DecodeStatus S = 607 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 608 if (S == MCDisassembler::Success) { 609 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 610 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 611 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 612 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 613 } 614 return S; 615 } 616 617 static DecodeStatus 618 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 619 const void *Decoder) { 620 unsigned Op1, Op2, Op3; 621 DecodeStatus S = 622 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 623 if (S == MCDisassembler::Success) { 624 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 625 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 626 Inst.addOperand(MCOperand::createImm(Op3)); 627 } 628 return S; 629 } 630 631 static DecodeStatus 632 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 633 const void *Decoder) { 634 unsigned Op1, Op2, Op3; 635 DecodeStatus S = 636 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 637 if (S == MCDisassembler::Success) { 638 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 639 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 640 DecodeBitpOperand(Inst, Op3, Address, Decoder); 641 } 642 return S; 643 } 644 645 static DecodeStatus 646 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 647 const void *Decoder) { 648 unsigned Op1, Op2, Op3, Op4, Op5, Op6; 649 DecodeStatus S = 650 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 651 if (S != MCDisassembler::Success) 652 return S; 653 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); 654 if (S != MCDisassembler::Success) 655 return S; 656 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 657 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 658 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 659 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 660 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); 661 DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder); 662 return S; 663 } 664 665 static DecodeStatus 666 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, 667 const void *Decoder) { 668 // Try and decode as a L6R instruction. 669 Inst.clear(); 670 unsigned Opcode = fieldFromInstruction(Insn, 27, 5); 671 switch (Opcode) { 672 case 0x00: 673 Inst.setOpcode(XCore::LMUL_l6r); 674 return DecodeL6RInstruction(Inst, Insn, Address, Decoder); 675 } 676 return MCDisassembler::Fail; 677 } 678 679 static DecodeStatus 680 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 681 const void *Decoder) { 682 unsigned Op1, Op2, Op3, Op4, Op5; 683 DecodeStatus S = 684 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 685 if (S != MCDisassembler::Success) 686 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); 687 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); 688 if (S != MCDisassembler::Success) 689 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); 690 691 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 692 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 693 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 694 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 695 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); 696 return S; 697 } 698 699 static DecodeStatus 700 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 701 const void *Decoder) { 702 unsigned Op1, Op2, Op3; 703 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); 704 DecodeStatus S = 705 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 706 if (S == MCDisassembler::Success) { 707 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 708 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 709 } 710 if (S == MCDisassembler::Success) { 711 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 712 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 713 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 714 } 715 return S; 716 } 717 718 static DecodeStatus 719 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 720 const void *Decoder) { 721 unsigned Op1, Op2, Op3; 722 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); 723 DecodeStatus S = 724 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 725 if (S == MCDisassembler::Success) { 726 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 727 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 728 } 729 if (S == MCDisassembler::Success) { 730 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 731 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 732 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 733 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 734 } 735 return S; 736 } 737 738 MCDisassembler::DecodeStatus XCoreDisassembler::getInstruction( 739 MCInst &instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, 740 raw_ostream &vStream, raw_ostream &cStream) const { 741 uint16_t insn16; 742 743 if (!readInstruction16(Bytes, Address, Size, insn16)) { 744 return Fail; 745 } 746 747 // Calling the auto-generated decoder function. 748 DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16, 749 Address, this, STI); 750 if (Result != Fail) { 751 Size = 2; 752 return Result; 753 } 754 755 uint32_t insn32; 756 757 if (!readInstruction32(Bytes, Address, Size, insn32)) { 758 return Fail; 759 } 760 761 // Calling the auto-generated decoder function. 762 Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI); 763 if (Result != Fail) { 764 Size = 4; 765 return Result; 766 } 767 768 return Fail; 769 } 770 771 namespace llvm { 772 extern Target TheXCoreTarget; 773 } 774 775 static MCDisassembler *createXCoreDisassembler(const Target &T, 776 const MCSubtargetInfo &STI, 777 MCContext &Ctx) { 778 return new XCoreDisassembler(STI, Ctx); 779 } 780 781 extern "C" void LLVMInitializeXCoreDisassembler() { 782 // Register the disassembler. 783 TargetRegistry::RegisterMCDisassembler(TheXCoreTarget, 784 createXCoreDisassembler); 785 } 786
