| /external/llvm/test/Transforms/InstCombine/ |
| vec_shuffle.ll | 195 %div = udiv <4 x i16> %tmp1, %vecinit11
|
| /external/v8/src/arm64/ |
| constants-arm64.h | [all...] |
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_neon_Resize.S | 118 udiv r1, r0, r2
|
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/lib/gcc/x86_64-w64-mingw32/4.8.3/plugin/include/ |
| genrtl.h | 975 gen_rtx_fmt_ee (UDIV, (MODE), (ARG0), (ARG1))
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
| FastISel.cpp | [all...] |
| TargetLowering.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 124 case ISD::UDIV:
[all...] |
| LegalizeVectorOps.cpp | 265 case ISD::UDIV:
[all...] |
| SelectionDAGBuilder.h | 784 void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCasts.cpp | 183 case Instruction::UDiv:
364 case Instruction::UDiv:
366 // UDiv and URem can be truncated if all the truncated bits are zero.
[all...] |
| InstCombineCompares.cpp | [all...] |
| /toolchain/binutils/binutils-2.25/cpu/ |
| m32r.cpu | [all...] |
| /external/llvm/lib/IR/ |
| Constants.cpp | 359 case Instruction::UDiv:
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 272 setOperationAction(ISD::UDIV, MVT::i32, Expand);
312 setOperationAction(ISD::UDIV, VT, Expand);
[all...] |
| /external/llvm/lib/Transforms/Vectorize/ |
| SLPVectorizer.cpp | [all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_2_7/ |
| BitcodeReader.cpp | 516 case bitc::BINOP_UDIV: return Instruction::UDiv;
[all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_3_0/ |
| BitcodeReader.cpp | 753 case bitc::BINOP_UDIV: return Instruction::UDiv;
[all...] |
| /art/compiler/utils/arm/ |
| assembler_arm.h | 566 virtual void udiv(Register rd, Register rn, Register rm, Condition cond = AL) = 0;
[all...] |
| assembler_arm32.cc | 216 void Arm32Assembler::udiv(Register rd, Register rn, Register rm, Condition cond) { function in class:art::arm::Arm32Assembler
[all...] |
| /external/llvm/docs/ |
| LangRef.rst | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 195 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
[all...] |
| /external/llvm/lib/Analysis/ |
| ValueTracking.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips32r6InstrInfo.td | 434 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, udiv>;
[all...] |
| MipsMSAInstrInfo.td | [all...] |
