| /external/clang/lib/Lex/ |
| PPExpressions.cpp | 607 unsigned ShAmt = static_cast<unsigned>(RHS.Val.getLimitedValue());
608 if (ShAmt >= LHS.getBitWidth())
609 Overflow = true, ShAmt = LHS.getBitWidth()-1;
610 Res = LHS.Val >> ShAmt;
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 380 Constant *ShAmt = ConstantExpr::getZExt(COp1, TrOp->getType());
382 Value *NSh = Builder->CreateBinOp(I.getOpcode(), TrOp, ShAmt,I.getName());
708 unsigned ShAmt = Op1C->getZExtValue();
713 APInt::getHighBitsSet(Op1C->getBitWidth(), ShAmt),
721 ComputeNumSignBits(I.getOperand(0), 0, &I) > ShAmt) {
751 unsigned ShAmt = Op1C->getZExtValue();
761 isPowerOf2_32(BitWidth) && Log2_32(BitWidth) == ShAmt) {
771 MaskedValueIsZero(Op0, APInt::getLowBitsSet(Op1C->getBitWidth(), ShAmt),
795 unsigned ShAmt = Op1C->getZExtValue();
[all...] |
| InstCombineMulDivRem.cpp | [all...] |
| InstCombineAddSub.cpp | [all...] |
| InstCombineAndOrXor.cpp | [all...] |
| InstCombineCasts.cpp | [all...] |
| InstCombineCompares.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 572 SDValue Lo, Hi, ShAmt;
575 ShAmt = DAG.getConstant(
577 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
586 ShAmt = DAG.getConstant(
589 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
606 ShAmt =
609 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
610 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
[all...] |
| TargetLowering.cpp | 620 unsigned ShAmt = SA->getZExtValue();
624 if (ShAmt >= BitWidth)
627 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
632 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
635 int Diff = ShAmt-C1;
649 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
659 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
662 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
666 TLO.DAG.getConstant(ShAmt, dl, ShTy))
[all...] |
| SelectionDAG.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/IR/ |
| ConstantFold.cpp | 270 unsigned ShAmt = Amt->getZExtValue();
272 if ((ShAmt & 7) != 0)
274 ShAmt >>= 3;
277 if (ByteStart >= CSize-ShAmt)
281 if (ByteStart+ByteSize+ShAmt <= CSize)
282 return ExtractConstantBytes(CE->getOperand(0), ByteStart+ShAmt, ByteSize);
292 unsigned ShAmt = Amt->getZExtValue();
294 if ((ShAmt & 7) != 0)
296 ShAmt >>= 3;
299 if (ByteStart+ByteSize <= ShAmt)
[all...] |
| /external/llvm/include/llvm/IR/ |
| IRBuilder.h | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| ScalarReplAggregates.cpp | [all...] |
| /external/llvm/lib/Analysis/ |
| ValueTracking.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | [all...] |
| ARMISelDAGToDAG.cpp | 96 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
473 unsigned ShAmt) {
480 (ShAmt == 2 || (Subtarget->isSwift() && ShAmt == 1));
673 unsigned ShAmt = Log2_32(RHSC);
675 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
701 unsigned ShAmt = 0;
711 ShAmt = Sh->getZExtValue();
712 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
715 ShAmt = 0
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
