1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file 10 /// This file implements a TargetTransformInfo analysis pass specific to the 11 /// X86 target machine. It uses the target's detailed information to provide 12 /// more precise answers to certain TTI queries, while letting the target 13 /// independent and default TTI implementations handle the rest. 14 /// 15 //===----------------------------------------------------------------------===// 16 17 #include "X86TargetTransformInfo.h" 18 #include "llvm/Analysis/TargetTransformInfo.h" 19 #include "llvm/CodeGen/BasicTTIImpl.h" 20 #include "llvm/IR/IntrinsicInst.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Target/CostTable.h" 23 #include "llvm/Target/TargetLowering.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "x86tti" 28 29 //===----------------------------------------------------------------------===// 30 // 31 // X86 cost model. 32 // 33 //===----------------------------------------------------------------------===// 34 35 TargetTransformInfo::PopcntSupportKind 36 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 37 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 38 // TODO: Currently the __builtin_popcount() implementation using SSE3 39 // instructions is inefficient. Once the problem is fixed, we should 40 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 41 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 42 } 43 44 unsigned X86TTIImpl::getNumberOfRegisters(bool Vector) { 45 if (Vector && !ST->hasSSE1()) 46 return 0; 47 48 if (ST->is64Bit()) { 49 if (Vector && ST->hasAVX512()) 50 return 32; 51 return 16; 52 } 53 return 8; 54 } 55 56 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) { 57 if (Vector) { 58 if (ST->hasAVX512()) return 512; 59 if (ST->hasAVX()) return 256; 60 if (ST->hasSSE1()) return 128; 61 return 0; 62 } 63 64 if (ST->is64Bit()) 65 return 64; 66 67 return 32; 68 } 69 70 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 71 // If the loop will not be vectorized, don't interleave the loop. 72 // Let regular unroll to unroll the loop, which saves the overflow 73 // check and memory check cost. 74 if (VF == 1) 75 return 1; 76 77 if (ST->isAtom()) 78 return 1; 79 80 // Sandybridge and Haswell have multiple execution ports and pipelined 81 // vector units. 82 if (ST->hasAVX()) 83 return 4; 84 85 return 2; 86 } 87 88 int X86TTIImpl::getArithmeticInstrCost( 89 unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info, 90 TTI::OperandValueKind Op2Info, TTI::OperandValueProperties Opd1PropInfo, 91 TTI::OperandValueProperties Opd2PropInfo) { 92 // Legalize the type. 93 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 94 95 int ISD = TLI->InstructionOpcodeToISD(Opcode); 96 assert(ISD && "Invalid opcode"); 97 98 if (ISD == ISD::SDIV && 99 Op2Info == TargetTransformInfo::OK_UniformConstantValue && 100 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 101 // On X86, vector signed division by constants power-of-two are 102 // normally expanded to the sequence SRA + SRL + ADD + SRA. 103 // The OperandValue properties many not be same as that of previous 104 // operation;conservatively assume OP_None. 105 int Cost = 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, 106 Op2Info, TargetTransformInfo::OP_None, 107 TargetTransformInfo::OP_None); 108 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 109 TargetTransformInfo::OP_None, 110 TargetTransformInfo::OP_None); 111 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info, 112 TargetTransformInfo::OP_None, 113 TargetTransformInfo::OP_None); 114 115 return Cost; 116 } 117 118 static const CostTblEntry AVX2UniformConstCostTable[] = { 119 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 120 121 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 122 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 123 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 124 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 125 }; 126 127 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 128 ST->hasAVX2()) { 129 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 130 LT.second)) 131 return LT.first * Entry->Cost; 132 } 133 134 static const CostTblEntry AVX512CostTable[] = { 135 { ISD::SHL, MVT::v16i32, 1 }, 136 { ISD::SRL, MVT::v16i32, 1 }, 137 { ISD::SRA, MVT::v16i32, 1 }, 138 { ISD::SHL, MVT::v8i64, 1 }, 139 { ISD::SRL, MVT::v8i64, 1 }, 140 { ISD::SRA, MVT::v8i64, 1 }, 141 }; 142 143 if (ST->hasAVX512()) { 144 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 145 return LT.first * Entry->Cost; 146 } 147 148 static const CostTblEntry AVX2CostTable[] = { 149 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 150 // customize them to detect the cases where shift amount is a scalar one. 151 { ISD::SHL, MVT::v4i32, 1 }, 152 { ISD::SRL, MVT::v4i32, 1 }, 153 { ISD::SRA, MVT::v4i32, 1 }, 154 { ISD::SHL, MVT::v8i32, 1 }, 155 { ISD::SRL, MVT::v8i32, 1 }, 156 { ISD::SRA, MVT::v8i32, 1 }, 157 { ISD::SHL, MVT::v2i64, 1 }, 158 { ISD::SRL, MVT::v2i64, 1 }, 159 { ISD::SHL, MVT::v4i64, 1 }, 160 { ISD::SRL, MVT::v4i64, 1 }, 161 }; 162 163 // Look for AVX2 lowering tricks. 164 if (ST->hasAVX2()) { 165 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 166 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 167 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 168 // On AVX2, a packed v16i16 shift left by a constant build_vector 169 // is lowered into a vector multiply (vpmullw). 170 return LT.first; 171 172 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 173 return LT.first * Entry->Cost; 174 } 175 176 static const CostTblEntry XOPCostTable[] = { 177 // 128bit shifts take 1cy, but right shifts require negation beforehand. 178 { ISD::SHL, MVT::v16i8, 1 }, 179 { ISD::SRL, MVT::v16i8, 2 }, 180 { ISD::SRA, MVT::v16i8, 2 }, 181 { ISD::SHL, MVT::v8i16, 1 }, 182 { ISD::SRL, MVT::v8i16, 2 }, 183 { ISD::SRA, MVT::v8i16, 2 }, 184 { ISD::SHL, MVT::v4i32, 1 }, 185 { ISD::SRL, MVT::v4i32, 2 }, 186 { ISD::SRA, MVT::v4i32, 2 }, 187 { ISD::SHL, MVT::v2i64, 1 }, 188 { ISD::SRL, MVT::v2i64, 2 }, 189 { ISD::SRA, MVT::v2i64, 2 }, 190 // 256bit shifts require splitting if AVX2 didn't catch them above. 191 { ISD::SHL, MVT::v32i8, 2 }, 192 { ISD::SRL, MVT::v32i8, 4 }, 193 { ISD::SRA, MVT::v32i8, 4 }, 194 { ISD::SHL, MVT::v16i16, 2 }, 195 { ISD::SRL, MVT::v16i16, 4 }, 196 { ISD::SRA, MVT::v16i16, 4 }, 197 { ISD::SHL, MVT::v8i32, 2 }, 198 { ISD::SRL, MVT::v8i32, 4 }, 199 { ISD::SRA, MVT::v8i32, 4 }, 200 { ISD::SHL, MVT::v4i64, 2 }, 201 { ISD::SRL, MVT::v4i64, 4 }, 202 { ISD::SRA, MVT::v4i64, 4 }, 203 }; 204 205 // Look for XOP lowering tricks. 206 if (ST->hasXOP()) { 207 if (const auto *Entry = CostTableLookup(XOPCostTable, ISD, LT.second)) 208 return LT.first * Entry->Cost; 209 } 210 211 static const CostTblEntry AVX2CustomCostTable[] = { 212 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 213 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 214 215 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 216 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 217 218 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 219 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 220 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 221 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 222 223 // Vectorizing division is a bad idea. See the SSE2 table for more comments. 224 { ISD::SDIV, MVT::v32i8, 32*20 }, 225 { ISD::SDIV, MVT::v16i16, 16*20 }, 226 { ISD::SDIV, MVT::v8i32, 8*20 }, 227 { ISD::SDIV, MVT::v4i64, 4*20 }, 228 { ISD::UDIV, MVT::v32i8, 32*20 }, 229 { ISD::UDIV, MVT::v16i16, 16*20 }, 230 { ISD::UDIV, MVT::v8i32, 8*20 }, 231 { ISD::UDIV, MVT::v4i64, 4*20 }, 232 }; 233 234 // Look for AVX2 lowering tricks for custom cases. 235 if (ST->hasAVX2()) { 236 if (const auto *Entry = CostTableLookup(AVX2CustomCostTable, ISD, 237 LT.second)) 238 return LT.first * Entry->Cost; 239 } 240 241 static const CostTblEntry 242 SSE2UniformConstCostTable[] = { 243 // We don't correctly identify costs of casts because they are marked as 244 // custom. 245 // Constant splats are cheaper for the following instructions. 246 { ISD::SHL, MVT::v16i8, 1 }, // psllw. 247 { ISD::SHL, MVT::v32i8, 2 }, // psllw. 248 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 249 { ISD::SHL, MVT::v16i16, 2 }, // psllw. 250 { ISD::SHL, MVT::v4i32, 1 }, // pslld 251 { ISD::SHL, MVT::v8i32, 2 }, // pslld 252 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 253 { ISD::SHL, MVT::v4i64, 2 }, // psllq. 254 255 { ISD::SRL, MVT::v16i8, 1 }, // psrlw. 256 { ISD::SRL, MVT::v32i8, 2 }, // psrlw. 257 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 258 { ISD::SRL, MVT::v16i16, 2 }, // psrlw. 259 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 260 { ISD::SRL, MVT::v8i32, 2 }, // psrld. 261 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 262 { ISD::SRL, MVT::v4i64, 2 }, // psrlq. 263 264 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 265 { ISD::SRA, MVT::v32i8, 8 }, // psrlw, pand, pxor, psubb. 266 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 267 { ISD::SRA, MVT::v16i16, 2 }, // psraw. 268 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 269 { ISD::SRA, MVT::v8i32, 2 }, // psrad. 270 { ISD::SRA, MVT::v2i64, 4 }, // 2 x psrad + shuffle. 271 { ISD::SRA, MVT::v4i64, 8 }, // 2 x psrad + shuffle. 272 273 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 274 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 275 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 276 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 277 }; 278 279 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 280 ST->hasSSE2()) { 281 // pmuldq sequence. 282 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 283 return LT.first * 15; 284 285 if (const auto *Entry = CostTableLookup(SSE2UniformConstCostTable, ISD, 286 LT.second)) 287 return LT.first * Entry->Cost; 288 } 289 290 if (ISD == ISD::SHL && 291 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 292 MVT VT = LT.second; 293 // Vector shift left by non uniform constant can be lowered 294 // into vector multiply (pmullw/pmulld). 295 if ((VT == MVT::v8i16 && ST->hasSSE2()) || 296 (VT == MVT::v4i32 && ST->hasSSE41())) 297 return LT.first; 298 299 // v16i16 and v8i32 shifts by non-uniform constants are lowered into a 300 // sequence of extract + two vector multiply + insert. 301 if ((VT == MVT::v8i32 || VT == MVT::v16i16) && 302 (ST->hasAVX() && !ST->hasAVX2())) 303 ISD = ISD::MUL; 304 305 // A vector shift left by non uniform constant is converted 306 // into a vector multiply; the new multiply is eventually 307 // lowered into a sequence of shuffles and 2 x pmuludq. 308 if (VT == MVT::v4i32 && ST->hasSSE2()) 309 ISD = ISD::MUL; 310 } 311 312 static const CostTblEntry SSE2CostTable[] = { 313 // We don't correctly identify costs of casts because they are marked as 314 // custom. 315 // For some cases, where the shift amount is a scalar we would be able 316 // to generate better code. Unfortunately, when this is the case the value 317 // (the splat) will get hoisted out of the loop, thereby making it invisible 318 // to ISel. The cost model must return worst case assumptions because it is 319 // used for vectorization and we don't want to make vectorized code worse 320 // than scalar code. 321 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 322 { ISD::SHL, MVT::v32i8, 2*26 }, // cmpgtb sequence. 323 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 324 { ISD::SHL, MVT::v16i16, 2*32 }, // cmpgtb sequence. 325 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 326 { ISD::SHL, MVT::v8i32, 2*2*5 }, // We optimized this using mul. 327 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 328 { ISD::SHL, MVT::v4i64, 2*4 }, // splat+shuffle sequence. 329 330 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 331 { ISD::SRL, MVT::v32i8, 2*26 }, // cmpgtb sequence. 332 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 333 { ISD::SRL, MVT::v16i16, 2*32 }, // cmpgtb sequence. 334 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 335 { ISD::SRL, MVT::v8i32, 2*16 }, // Shift each lane + blend. 336 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 337 { ISD::SRL, MVT::v4i64, 2*4 }, // splat+shuffle sequence. 338 339 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 340 { ISD::SRA, MVT::v32i8, 2*54 }, // unpacked cmpgtb sequence. 341 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 342 { ISD::SRA, MVT::v16i16, 2*32 }, // cmpgtb sequence. 343 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 344 { ISD::SRA, MVT::v8i32, 2*16 }, // Shift each lane + blend. 345 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 346 { ISD::SRA, MVT::v4i64, 2*12 }, // srl/xor/sub sequence. 347 348 // It is not a good idea to vectorize division. We have to scalarize it and 349 // in the process we will often end up having to spilling regular 350 // registers. The overhead of division is going to dominate most kernels 351 // anyways so try hard to prevent vectorization of division - it is 352 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 353 // to hide "20 cycles" for each lane. 354 { ISD::SDIV, MVT::v16i8, 16*20 }, 355 { ISD::SDIV, MVT::v8i16, 8*20 }, 356 { ISD::SDIV, MVT::v4i32, 4*20 }, 357 { ISD::SDIV, MVT::v2i64, 2*20 }, 358 { ISD::UDIV, MVT::v16i8, 16*20 }, 359 { ISD::UDIV, MVT::v8i16, 8*20 }, 360 { ISD::UDIV, MVT::v4i32, 4*20 }, 361 { ISD::UDIV, MVT::v2i64, 2*20 }, 362 }; 363 364 if (ST->hasSSE2()) { 365 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 366 return LT.first * Entry->Cost; 367 } 368 369 static const CostTblEntry AVX1CostTable[] = { 370 // We don't have to scalarize unsupported ops. We can issue two half-sized 371 // operations and we only need to extract the upper YMM half. 372 // Two ops + 1 extract + 1 insert = 4. 373 { ISD::MUL, MVT::v16i16, 4 }, 374 { ISD::MUL, MVT::v8i32, 4 }, 375 { ISD::SUB, MVT::v8i32, 4 }, 376 { ISD::ADD, MVT::v8i32, 4 }, 377 { ISD::SUB, MVT::v4i64, 4 }, 378 { ISD::ADD, MVT::v4i64, 4 }, 379 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 380 // are lowered as a series of long multiplies(3), shifts(4) and adds(2) 381 // Because we believe v4i64 to be a legal type, we must also include the 382 // split factor of two in the cost table. Therefore, the cost here is 18 383 // instead of 9. 384 { ISD::MUL, MVT::v4i64, 18 }, 385 }; 386 387 // Look for AVX1 lowering tricks. 388 if (ST->hasAVX() && !ST->hasAVX2()) { 389 MVT VT = LT.second; 390 391 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, VT)) 392 return LT.first * Entry->Cost; 393 } 394 395 // Custom lowering of vectors. 396 static const CostTblEntry CustomLowered[] = { 397 // A v2i64/v4i64 and multiply is custom lowered as a series of long 398 // multiplies(3), shifts(4) and adds(2). 399 { ISD::MUL, MVT::v2i64, 9 }, 400 { ISD::MUL, MVT::v4i64, 9 }, 401 }; 402 if (const auto *Entry = CostTableLookup(CustomLowered, ISD, LT.second)) 403 return LT.first * Entry->Cost; 404 405 // Special lowering of v4i32 mul on sse2, sse3: Lower v4i32 mul as 2x shuffle, 406 // 2x pmuludq, 2x shuffle. 407 if (ISD == ISD::MUL && LT.second == MVT::v4i32 && ST->hasSSE2() && 408 !ST->hasSSE41()) 409 return LT.first * 6; 410 411 // Fallback to the default implementation. 412 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info); 413 } 414 415 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, 416 Type *SubTp) { 417 // We only estimate the cost of reverse and alternate shuffles. 418 if (Kind != TTI::SK_Reverse && Kind != TTI::SK_Alternate) 419 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 420 421 if (Kind == TTI::SK_Reverse) { 422 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 423 int Cost = 1; 424 if (LT.second.getSizeInBits() > 128) 425 Cost = 3; // Extract + insert + copy. 426 427 // Multiple by the number of parts. 428 return Cost * LT.first; 429 } 430 431 if (Kind == TTI::SK_Alternate) { 432 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 433 // 64-bit packed integer vectors (v2i32) are promoted to type v2i64. 434 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 435 436 // The backend knows how to generate a single VEX.256 version of 437 // instruction VPBLENDW if the target supports AVX2. 438 if (ST->hasAVX2() && LT.second == MVT::v16i16) 439 return LT.first; 440 441 static const CostTblEntry AVXAltShuffleTbl[] = { 442 {ISD::VECTOR_SHUFFLE, MVT::v4i64, 1}, // vblendpd 443 {ISD::VECTOR_SHUFFLE, MVT::v4f64, 1}, // vblendpd 444 445 {ISD::VECTOR_SHUFFLE, MVT::v8i32, 1}, // vblendps 446 {ISD::VECTOR_SHUFFLE, MVT::v8f32, 1}, // vblendps 447 448 // This shuffle is custom lowered into a sequence of: 449 // 2x vextractf128 , 2x vpblendw , 1x vinsertf128 450 {ISD::VECTOR_SHUFFLE, MVT::v16i16, 5}, 451 452 // This shuffle is custom lowered into a long sequence of: 453 // 2x vextractf128 , 4x vpshufb , 2x vpor , 1x vinsertf128 454 {ISD::VECTOR_SHUFFLE, MVT::v32i8, 9} 455 }; 456 457 if (ST->hasAVX()) 458 if (const auto *Entry = CostTableLookup(AVXAltShuffleTbl, 459 ISD::VECTOR_SHUFFLE, LT.second)) 460 return LT.first * Entry->Cost; 461 462 static const CostTblEntry SSE41AltShuffleTbl[] = { 463 // These are lowered into movsd. 464 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, 465 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, 466 467 // packed float vectors with four elements are lowered into BLENDI dag 468 // nodes. A v4i32/v4f32 BLENDI generates a single 'blendps'/'blendpd'. 469 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 1}, 470 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1}, 471 472 // This shuffle generates a single pshufw. 473 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 1}, 474 475 // There is no instruction that matches a v16i8 alternate shuffle. 476 // The backend will expand it into the sequence 'pshufb + pshufb + or'. 477 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 3} 478 }; 479 480 if (ST->hasSSE41()) 481 if (const auto *Entry = CostTableLookup(SSE41AltShuffleTbl, ISD::VECTOR_SHUFFLE, 482 LT.second)) 483 return LT.first * Entry->Cost; 484 485 static const CostTblEntry SSSE3AltShuffleTbl[] = { 486 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, // movsd 487 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, // movsd 488 489 // SSE3 doesn't have 'blendps'. The following shuffles are expanded into 490 // the sequence 'shufps + pshufd' 491 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2}, 492 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2}, 493 494 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 3}, // pshufb + pshufb + or 495 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 3} // pshufb + pshufb + or 496 }; 497 498 if (ST->hasSSSE3()) 499 if (const auto *Entry = CostTableLookup(SSSE3AltShuffleTbl, 500 ISD::VECTOR_SHUFFLE, LT.second)) 501 return LT.first * Entry->Cost; 502 503 static const CostTblEntry SSEAltShuffleTbl[] = { 504 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, // movsd 505 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, // movsd 506 507 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2}, // shufps + pshufd 508 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2}, // shufps + pshufd 509 510 // This is expanded into a long sequence of four extract + four insert. 511 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 8}, // 4 x pextrw + 4 pinsrw. 512 513 // 8 x (pinsrw + pextrw + and + movb + movzb + or) 514 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 48} 515 }; 516 517 // Fall-back (SSE3 and SSE2). 518 if (const auto *Entry = CostTableLookup(SSEAltShuffleTbl, 519 ISD::VECTOR_SHUFFLE, LT.second)) 520 return LT.first * Entry->Cost; 521 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 522 } 523 524 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 525 } 526 527 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) { 528 int ISD = TLI->InstructionOpcodeToISD(Opcode); 529 assert(ISD && "Invalid opcode"); 530 531 // FIXME: Need a better design of the cost table to handle non-simple types of 532 // potential massive combinations (elem_num x src_type x dst_type). 533 534 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 535 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 536 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 537 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 538 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 539 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 540 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 541 542 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 543 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 544 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 545 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 546 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 547 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 548 }; 549 550 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 551 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 552 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 553 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 554 555 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, 556 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, 557 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 }, 558 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 559 560 // v16i1 -> v16i32 - load + broadcast 561 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 562 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 563 564 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 565 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 566 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 567 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 568 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 569 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 570 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 571 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 572 573 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 574 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 575 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 576 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 577 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 578 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 579 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 580 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 581 582 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 583 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 584 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 585 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 586 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 587 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 588 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 589 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 590 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 591 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 592 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 593 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 594 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 595 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 596 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 597 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 598 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 599 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 600 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 601 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 12 }, 602 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 26 }, 603 604 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 605 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 606 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 607 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 608 }; 609 610 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 611 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 612 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 613 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 614 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 615 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 616 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 617 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 618 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 619 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 620 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 621 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 622 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 623 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 624 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 625 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 626 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 627 628 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 629 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 630 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 631 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 632 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 633 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 }, 634 635 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 636 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 637 638 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 639 }; 640 641 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 642 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 643 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 644 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 645 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 646 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 7 }, 647 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 648 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 649 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 650 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 651 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 652 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 }, 653 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 654 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 }, 655 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 656 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 657 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 658 659 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 660 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 661 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 }, 662 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 663 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 664 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 665 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 }, 666 667 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 668 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 669 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 670 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 671 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 672 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 673 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 674 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 675 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 676 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 677 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 678 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 679 680 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 681 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 682 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 683 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 684 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 685 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 686 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 687 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 688 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 689 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 690 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 691 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 692 // The generic code to compute the scalar overhead is currently broken. 693 // Workaround this limitation by estimating the scalarization overhead 694 // here. We have roughly 10 instructions per scalar element. 695 // Multiply that by the vector width. 696 // FIXME: remove that when PR19268 is fixed. 697 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 698 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 4*10 }, 699 700 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 }, 701 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 }, 702 // This node is expanded into scalarized operations but BasicTTI is overly 703 // optimistic estimating its cost. It computes 3 per element (one 704 // vector-extract, one scalar conversion and one vector-insert). The 705 // problem is that the inserts form a read-modify-write chain so latency 706 // should be factored in too. Inflating the cost per element by 1. 707 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 708 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 709 }; 710 711 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 712 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 713 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 714 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 715 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 716 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 717 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 718 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 719 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 720 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 721 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 722 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 723 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 724 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 725 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 726 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 727 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 728 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 729 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 730 731 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 732 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 733 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 734 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 30 }, 735 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 736 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 737 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 738 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 739 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, 740 }; 741 742 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 743 // These are somewhat magic numbers justified by looking at the output of 744 // Intel's IACA, running some kernels and making sure when we take 745 // legalization into account the throughput will be overestimated. 746 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 747 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 748 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 749 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 750 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 751 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 752 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 753 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 754 // There are faster sequences for float conversions. 755 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 756 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 757 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 758 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 759 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 760 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 }, 761 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 762 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 763 764 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 765 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 766 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 767 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 768 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 769 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 770 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 771 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 772 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 773 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 774 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 775 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 776 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 777 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 778 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 779 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 780 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 781 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 782 783 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 784 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 785 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 786 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 787 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 788 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 789 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 790 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, 791 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 4 }, 792 }; 793 794 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 795 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 796 797 if (ST->hasSSE2() && !ST->hasAVX()) { 798 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 799 LTDest.second, LTSrc.second)) 800 return LTSrc.first * Entry->Cost; 801 } 802 803 EVT SrcTy = TLI->getValueType(DL, Src); 804 EVT DstTy = TLI->getValueType(DL, Dst); 805 806 // The function getSimpleVT only handles simple value types. 807 if (!SrcTy.isSimple() || !DstTy.isSimple()) 808 return BaseT::getCastInstrCost(Opcode, Dst, Src); 809 810 if (ST->hasDQI()) 811 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 812 DstTy.getSimpleVT(), 813 SrcTy.getSimpleVT())) 814 return Entry->Cost; 815 816 if (ST->hasAVX512()) 817 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 818 DstTy.getSimpleVT(), 819 SrcTy.getSimpleVT())) 820 return Entry->Cost; 821 822 if (ST->hasAVX2()) { 823 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 824 DstTy.getSimpleVT(), 825 SrcTy.getSimpleVT())) 826 return Entry->Cost; 827 } 828 829 if (ST->hasAVX()) { 830 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 831 DstTy.getSimpleVT(), 832 SrcTy.getSimpleVT())) 833 return Entry->Cost; 834 } 835 836 if (ST->hasSSE41()) { 837 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 838 DstTy.getSimpleVT(), 839 SrcTy.getSimpleVT())) 840 return Entry->Cost; 841 } 842 843 if (ST->hasSSE2()) { 844 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 845 DstTy.getSimpleVT(), 846 SrcTy.getSimpleVT())) 847 return Entry->Cost; 848 } 849 850 return BaseT::getCastInstrCost(Opcode, Dst, Src); 851 } 852 853 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) { 854 // Legalize the type. 855 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 856 857 MVT MTy = LT.second; 858 859 int ISD = TLI->InstructionOpcodeToISD(Opcode); 860 assert(ISD && "Invalid opcode"); 861 862 static const CostTblEntry SSE42CostTbl[] = { 863 { ISD::SETCC, MVT::v2f64, 1 }, 864 { ISD::SETCC, MVT::v4f32, 1 }, 865 { ISD::SETCC, MVT::v2i64, 1 }, 866 { ISD::SETCC, MVT::v4i32, 1 }, 867 { ISD::SETCC, MVT::v8i16, 1 }, 868 { ISD::SETCC, MVT::v16i8, 1 }, 869 }; 870 871 static const CostTblEntry AVX1CostTbl[] = { 872 { ISD::SETCC, MVT::v4f64, 1 }, 873 { ISD::SETCC, MVT::v8f32, 1 }, 874 // AVX1 does not support 8-wide integer compare. 875 { ISD::SETCC, MVT::v4i64, 4 }, 876 { ISD::SETCC, MVT::v8i32, 4 }, 877 { ISD::SETCC, MVT::v16i16, 4 }, 878 { ISD::SETCC, MVT::v32i8, 4 }, 879 }; 880 881 static const CostTblEntry AVX2CostTbl[] = { 882 { ISD::SETCC, MVT::v4i64, 1 }, 883 { ISD::SETCC, MVT::v8i32, 1 }, 884 { ISD::SETCC, MVT::v16i16, 1 }, 885 { ISD::SETCC, MVT::v32i8, 1 }, 886 }; 887 888 static const CostTblEntry AVX512CostTbl[] = { 889 { ISD::SETCC, MVT::v8i64, 1 }, 890 { ISD::SETCC, MVT::v16i32, 1 }, 891 { ISD::SETCC, MVT::v8f64, 1 }, 892 { ISD::SETCC, MVT::v16f32, 1 }, 893 }; 894 895 if (ST->hasAVX512()) 896 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 897 return LT.first * Entry->Cost; 898 899 if (ST->hasAVX2()) 900 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 901 return LT.first * Entry->Cost; 902 903 if (ST->hasAVX()) 904 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 905 return LT.first * Entry->Cost; 906 907 if (ST->hasSSE42()) 908 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 909 return LT.first * Entry->Cost; 910 911 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy); 912 } 913 914 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 915 assert(Val->isVectorTy() && "This must be a vector type"); 916 917 if (Index != -1U) { 918 // Legalize the type. 919 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 920 921 // This type is legalized to a scalar type. 922 if (!LT.second.isVector()) 923 return 0; 924 925 // The type may be split. Normalize the index to the new type. 926 unsigned Width = LT.second.getVectorNumElements(); 927 Index = Index % Width; 928 929 // Floating point scalars are already located in index #0. 930 if (Val->getScalarType()->isFloatingPointTy() && Index == 0) 931 return 0; 932 } 933 934 return BaseT::getVectorInstrCost(Opcode, Val, Index); 935 } 936 937 int X86TTIImpl::getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) { 938 assert (Ty->isVectorTy() && "Can only scalarize vectors"); 939 int Cost = 0; 940 941 for (int i = 0, e = Ty->getVectorNumElements(); i < e; ++i) { 942 if (Insert) 943 Cost += getVectorInstrCost(Instruction::InsertElement, Ty, i); 944 if (Extract) 945 Cost += getVectorInstrCost(Instruction::ExtractElement, Ty, i); 946 } 947 948 return Cost; 949 } 950 951 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 952 unsigned AddressSpace) { 953 // Handle non-power-of-two vectors such as <3 x float> 954 if (VectorType *VTy = dyn_cast<VectorType>(Src)) { 955 unsigned NumElem = VTy->getVectorNumElements(); 956 957 // Handle a few common cases: 958 // <3 x float> 959 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 960 // Cost = 64 bit store + extract + 32 bit store. 961 return 3; 962 963 // <3 x double> 964 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 965 // Cost = 128 bit store + unpack + 64 bit store. 966 return 3; 967 968 // Assume that all other non-power-of-two numbers are scalarized. 969 if (!isPowerOf2_32(NumElem)) { 970 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 971 AddressSpace); 972 int SplitCost = getScalarizationOverhead(Src, Opcode == Instruction::Load, 973 Opcode == Instruction::Store); 974 return NumElem * Cost + SplitCost; 975 } 976 } 977 978 // Legalize the type. 979 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 980 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 981 "Invalid Opcode"); 982 983 // Each load/store unit costs 1. 984 int Cost = LT.first * 1; 985 986 // On Sandybridge 256bit load/stores are double pumped 987 // (but not on Haswell). 988 if (LT.second.getSizeInBits() > 128 && !ST->hasAVX2()) 989 Cost*=2; 990 991 return Cost; 992 } 993 994 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 995 unsigned Alignment, 996 unsigned AddressSpace) { 997 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy); 998 if (!SrcVTy) 999 // To calculate scalar take the regular cost, without mask 1000 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace); 1001 1002 unsigned NumElem = SrcVTy->getVectorNumElements(); 1003 VectorType *MaskTy = 1004 VectorType::get(Type::getInt8Ty(getGlobalContext()), NumElem); 1005 if ((Opcode == Instruction::Load && !isLegalMaskedLoad(SrcVTy)) || 1006 (Opcode == Instruction::Store && !isLegalMaskedStore(SrcVTy)) || 1007 !isPowerOf2_32(NumElem)) { 1008 // Scalarization 1009 int MaskSplitCost = getScalarizationOverhead(MaskTy, false, true); 1010 int ScalarCompareCost = getCmpSelInstrCost( 1011 Instruction::ICmp, Type::getInt8Ty(getGlobalContext()), nullptr); 1012 int BranchCost = getCFInstrCost(Instruction::Br); 1013 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 1014 1015 int ValueSplitCost = getScalarizationOverhead( 1016 SrcVTy, Opcode == Instruction::Load, Opcode == Instruction::Store); 1017 int MemopCost = 1018 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 1019 Alignment, AddressSpace); 1020 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 1021 } 1022 1023 // Legalize the type. 1024 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 1025 auto VT = TLI->getValueType(DL, SrcVTy); 1026 int Cost = 0; 1027 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 1028 LT.second.getVectorNumElements() == NumElem) 1029 // Promotion requires expand/truncate for data and a shuffle for mask. 1030 Cost += getShuffleCost(TTI::SK_Alternate, SrcVTy, 0, nullptr) + 1031 getShuffleCost(TTI::SK_Alternate, MaskTy, 0, nullptr); 1032 1033 else if (LT.second.getVectorNumElements() > NumElem) { 1034 VectorType *NewMaskTy = VectorType::get(MaskTy->getVectorElementType(), 1035 LT.second.getVectorNumElements()); 1036 // Expanding requires fill mask with zeroes 1037 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy); 1038 } 1039 if (!ST->hasAVX512()) 1040 return Cost + LT.first*4; // Each maskmov costs 4 1041 1042 // AVX-512 masked load/store is cheapper 1043 return Cost+LT.first; 1044 } 1045 1046 int X86TTIImpl::getAddressComputationCost(Type *Ty, bool IsComplex) { 1047 // Address computations in vectorized code with non-consecutive addresses will 1048 // likely result in more instructions compared to scalar code where the 1049 // computation can more often be merged into the index mode. The resulting 1050 // extra micro-ops can significantly decrease throughput. 1051 unsigned NumVectorInstToHideOverhead = 10; 1052 1053 if (Ty->isVectorTy() && IsComplex) 1054 return NumVectorInstToHideOverhead; 1055 1056 return BaseT::getAddressComputationCost(Ty, IsComplex); 1057 } 1058 1059 int X86TTIImpl::getReductionCost(unsigned Opcode, Type *ValTy, 1060 bool IsPairwise) { 1061 1062 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 1063 1064 MVT MTy = LT.second; 1065 1066 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1067 assert(ISD && "Invalid opcode"); 1068 1069 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 1070 // and make it as the cost. 1071 1072 static const CostTblEntry SSE42CostTblPairWise[] = { 1073 { ISD::FADD, MVT::v2f64, 2 }, 1074 { ISD::FADD, MVT::v4f32, 4 }, 1075 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 1076 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 1077 { ISD::ADD, MVT::v8i16, 5 }, 1078 }; 1079 1080 static const CostTblEntry AVX1CostTblPairWise[] = { 1081 { ISD::FADD, MVT::v4f32, 4 }, 1082 { ISD::FADD, MVT::v4f64, 5 }, 1083 { ISD::FADD, MVT::v8f32, 7 }, 1084 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 1085 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 1086 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8". 1087 { ISD::ADD, MVT::v8i16, 5 }, 1088 { ISD::ADD, MVT::v8i32, 5 }, 1089 }; 1090 1091 static const CostTblEntry SSE42CostTblNoPairWise[] = { 1092 { ISD::FADD, MVT::v2f64, 2 }, 1093 { ISD::FADD, MVT::v4f32, 4 }, 1094 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 1095 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 1096 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 1097 }; 1098 1099 static const CostTblEntry AVX1CostTblNoPairWise[] = { 1100 { ISD::FADD, MVT::v4f32, 3 }, 1101 { ISD::FADD, MVT::v4f64, 3 }, 1102 { ISD::FADD, MVT::v8f32, 4 }, 1103 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 1104 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "2.8". 1105 { ISD::ADD, MVT::v4i64, 3 }, 1106 { ISD::ADD, MVT::v8i16, 4 }, 1107 { ISD::ADD, MVT::v8i32, 5 }, 1108 }; 1109 1110 if (IsPairwise) { 1111 if (ST->hasAVX()) 1112 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 1113 return LT.first * Entry->Cost; 1114 1115 if (ST->hasSSE42()) 1116 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy)) 1117 return LT.first * Entry->Cost; 1118 } else { 1119 if (ST->hasAVX()) 1120 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 1121 return LT.first * Entry->Cost; 1122 1123 if (ST->hasSSE42()) 1124 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy)) 1125 return LT.first * Entry->Cost; 1126 } 1127 1128 return BaseT::getReductionCost(Opcode, ValTy, IsPairwise); 1129 } 1130 1131 /// \brief Calculate the cost of materializing a 64-bit value. This helper 1132 /// method might only calculate a fraction of a larger immediate. Therefore it 1133 /// is valid to return a cost of ZERO. 1134 int X86TTIImpl::getIntImmCost(int64_t Val) { 1135 if (Val == 0) 1136 return TTI::TCC_Free; 1137 1138 if (isInt<32>(Val)) 1139 return TTI::TCC_Basic; 1140 1141 return 2 * TTI::TCC_Basic; 1142 } 1143 1144 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { 1145 assert(Ty->isIntegerTy()); 1146 1147 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 1148 if (BitSize == 0) 1149 return ~0U; 1150 1151 // Never hoist constants larger than 128bit, because this might lead to 1152 // incorrect code generation or assertions in codegen. 1153 // Fixme: Create a cost model for types larger than i128 once the codegen 1154 // issues have been fixed. 1155 if (BitSize > 128) 1156 return TTI::TCC_Free; 1157 1158 if (Imm == 0) 1159 return TTI::TCC_Free; 1160 1161 // Sign-extend all constants to a multiple of 64-bit. 1162 APInt ImmVal = Imm; 1163 if (BitSize & 0x3f) 1164 ImmVal = Imm.sext((BitSize + 63) & ~0x3fU); 1165 1166 // Split the constant into 64-bit chunks and calculate the cost for each 1167 // chunk. 1168 int Cost = 0; 1169 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 1170 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 1171 int64_t Val = Tmp.getSExtValue(); 1172 Cost += getIntImmCost(Val); 1173 } 1174 // We need at least one instruction to materialze the constant. 1175 return std::max(1, Cost); 1176 } 1177 1178 int X86TTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, 1179 Type *Ty) { 1180 assert(Ty->isIntegerTy()); 1181 1182 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 1183 // There is no cost model for constants with a bit size of 0. Return TCC_Free 1184 // here, so that constant hoisting will ignore this constant. 1185 if (BitSize == 0) 1186 return TTI::TCC_Free; 1187 1188 unsigned ImmIdx = ~0U; 1189 switch (Opcode) { 1190 default: 1191 return TTI::TCC_Free; 1192 case Instruction::GetElementPtr: 1193 // Always hoist the base address of a GetElementPtr. This prevents the 1194 // creation of new constants for every base constant that gets constant 1195 // folded with the offset. 1196 if (Idx == 0) 1197 return 2 * TTI::TCC_Basic; 1198 return TTI::TCC_Free; 1199 case Instruction::Store: 1200 ImmIdx = 0; 1201 break; 1202 case Instruction::ICmp: 1203 // This is an imperfect hack to prevent constant hoisting of 1204 // compares that might be trying to check if a 64-bit value fits in 1205 // 32-bits. The backend can optimize these cases using a right shift by 32. 1206 // Ideally we would check the compare predicate here. There also other 1207 // similar immediates the backend can use shifts for. 1208 if (Idx == 1 && Imm.getBitWidth() == 64) { 1209 uint64_t ImmVal = Imm.getZExtValue(); 1210 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 1211 return TTI::TCC_Free; 1212 } 1213 ImmIdx = 1; 1214 break; 1215 case Instruction::And: 1216 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 1217 // by using a 32-bit operation with implicit zero extension. Detect such 1218 // immediates here as the normal path expects bit 31 to be sign extended. 1219 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 1220 return TTI::TCC_Free; 1221 // Fallthrough 1222 case Instruction::Add: 1223 case Instruction::Sub: 1224 case Instruction::Mul: 1225 case Instruction::UDiv: 1226 case Instruction::SDiv: 1227 case Instruction::URem: 1228 case Instruction::SRem: 1229 case Instruction::Or: 1230 case Instruction::Xor: 1231 ImmIdx = 1; 1232 break; 1233 // Always return TCC_Free for the shift value of a shift instruction. 1234 case Instruction::Shl: 1235 case Instruction::LShr: 1236 case Instruction::AShr: 1237 if (Idx == 1) 1238 return TTI::TCC_Free; 1239 break; 1240 case Instruction::Trunc: 1241 case Instruction::ZExt: 1242 case Instruction::SExt: 1243 case Instruction::IntToPtr: 1244 case Instruction::PtrToInt: 1245 case Instruction::BitCast: 1246 case Instruction::PHI: 1247 case Instruction::Call: 1248 case Instruction::Select: 1249 case Instruction::Ret: 1250 case Instruction::Load: 1251 break; 1252 } 1253 1254 if (Idx == ImmIdx) { 1255 int NumConstants = (BitSize + 63) / 64; 1256 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty); 1257 return (Cost <= NumConstants * TTI::TCC_Basic) 1258 ? static_cast<int>(TTI::TCC_Free) 1259 : Cost; 1260 } 1261 1262 return X86TTIImpl::getIntImmCost(Imm, Ty); 1263 } 1264 1265 int X86TTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, 1266 Type *Ty) { 1267 assert(Ty->isIntegerTy()); 1268 1269 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 1270 // There is no cost model for constants with a bit size of 0. Return TCC_Free 1271 // here, so that constant hoisting will ignore this constant. 1272 if (BitSize == 0) 1273 return TTI::TCC_Free; 1274 1275 switch (IID) { 1276 default: 1277 return TTI::TCC_Free; 1278 case Intrinsic::sadd_with_overflow: 1279 case Intrinsic::uadd_with_overflow: 1280 case Intrinsic::ssub_with_overflow: 1281 case Intrinsic::usub_with_overflow: 1282 case Intrinsic::smul_with_overflow: 1283 case Intrinsic::umul_with_overflow: 1284 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 1285 return TTI::TCC_Free; 1286 break; 1287 case Intrinsic::experimental_stackmap: 1288 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 1289 return TTI::TCC_Free; 1290 break; 1291 case Intrinsic::experimental_patchpoint_void: 1292 case Intrinsic::experimental_patchpoint_i64: 1293 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 1294 return TTI::TCC_Free; 1295 break; 1296 } 1297 return X86TTIImpl::getIntImmCost(Imm, Ty); 1298 } 1299 1300 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy) { 1301 Type *ScalarTy = DataTy->getScalarType(); 1302 int DataWidth = isa<PointerType>(ScalarTy) ? 1303 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits(); 1304 1305 return (DataWidth >= 32 && ST->hasAVX2()); 1306 } 1307 1308 bool X86TTIImpl::isLegalMaskedStore(Type *DataType) { 1309 return isLegalMaskedLoad(DataType); 1310 } 1311 1312 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy) { 1313 // This function is called now in two cases: from the Loop Vectorizer 1314 // and from the Scalarizer. 1315 // When the Loop Vectorizer asks about legality of the feature, 1316 // the vectorization factor is not calculated yet. The Loop Vectorizer 1317 // sends a scalar type and the decision is based on the width of the 1318 // scalar element. 1319 // Later on, the cost model will estimate usage this intrinsic based on 1320 // the vector type. 1321 // The Scalarizer asks again about legality. It sends a vector type. 1322 // In this case we can reject non-power-of-2 vectors. 1323 if (isa<VectorType>(DataTy) && !isPowerOf2_32(DataTy->getVectorNumElements())) 1324 return false; 1325 Type *ScalarTy = DataTy->getScalarType(); 1326 int DataWidth = isa<PointerType>(ScalarTy) ? 1327 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits(); 1328 1329 // AVX-512 allows gather and scatter 1330 return DataWidth >= 32 && ST->hasAVX512(); 1331 } 1332 1333 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType) { 1334 return isLegalMaskedGather(DataType); 1335 } 1336 1337 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 1338 const Function *Callee) const { 1339 const TargetMachine &TM = getTLI()->getTargetMachine(); 1340 1341 // Work this as a subsetting of subtarget features. 1342 const FeatureBitset &CallerBits = 1343 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 1344 const FeatureBitset &CalleeBits = 1345 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 1346 1347 // FIXME: This is likely too limiting as it will include subtarget features 1348 // that we might not care about for inlining, but it is conservatively 1349 // correct. 1350 return (CallerBits & CalleeBits) == CalleeBits; 1351 } 1352
