1 //===--------------- PPCVSXFMAMutate.cpp - VSX FMA Mutation ---------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This pass mutates the form of VSX FMA instructions to avoid unnecessary 11 // copies. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "PPCInstrInfo.h" 16 #include "MCTargetDesc/PPCPredicates.h" 17 #include "PPC.h" 18 #include "PPCInstrBuilder.h" 19 #include "PPCMachineFunctionInfo.h" 20 #include "PPCTargetMachine.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/ADT/Statistic.h" 23 #include "llvm/CodeGen/LiveIntervalAnalysis.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunctionPass.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineMemOperand.h" 28 #include "llvm/CodeGen/MachineRegisterInfo.h" 29 #include "llvm/CodeGen/PseudoSourceValue.h" 30 #include "llvm/CodeGen/ScheduleDAG.h" 31 #include "llvm/CodeGen/SlotIndexes.h" 32 #include "llvm/MC/MCAsmInfo.h" 33 #include "llvm/Support/CommandLine.h" 34 #include "llvm/Support/Debug.h" 35 #include "llvm/Support/ErrorHandling.h" 36 #include "llvm/Support/TargetRegistry.h" 37 #include "llvm/Support/raw_ostream.h" 38 39 using namespace llvm; 40 41 static cl::opt<bool> DisableVSXFMAMutate("disable-ppc-vsx-fma-mutation", 42 cl::desc("Disable VSX FMA instruction mutation"), cl::Hidden); 43 44 #define DEBUG_TYPE "ppc-vsx-fma-mutate" 45 46 namespace llvm { namespace PPC { 47 int getAltVSXFMAOpcode(uint16_t Opcode); 48 } } 49 50 namespace { 51 // PPCVSXFMAMutate pass - For copies between VSX registers and non-VSX registers 52 // (Altivec and scalar floating-point registers), we need to transform the 53 // copies into subregister copies with other restrictions. 54 struct PPCVSXFMAMutate : public MachineFunctionPass { 55 static char ID; 56 PPCVSXFMAMutate() : MachineFunctionPass(ID) { 57 initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry()); 58 } 59 60 LiveIntervals *LIS; 61 const PPCInstrInfo *TII; 62 63 protected: 64 bool processBlock(MachineBasicBlock &MBB) { 65 bool Changed = false; 66 67 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 68 const TargetRegisterInfo *TRI = &TII->getRegisterInfo(); 69 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end(); 70 I != IE; ++I) { 71 MachineInstr *MI = I; 72 73 // The default (A-type) VSX FMA form kills the addend (it is taken from 74 // the target register, which is then updated to reflect the result of 75 // the FMA). If the instruction, however, kills one of the registers 76 // used for the product, then we can use the M-form instruction (which 77 // will take that value from the to-be-defined register). 78 79 int AltOpc = PPC::getAltVSXFMAOpcode(MI->getOpcode()); 80 if (AltOpc == -1) 81 continue; 82 83 // This pass is run after register coalescing, and so we're looking for 84 // a situation like this: 85 // ... 86 // %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9 87 // %vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16, 88 // %RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16 89 // ... 90 // %vreg9<def,tied1> = XSMADDADP %vreg9<tied0>, %vreg17, %vreg19, 91 // %RM<imp-use>; VSLRC:%vreg9,%vreg17,%vreg19 92 // ... 93 // Where we can eliminate the copy by changing from the A-type to the 94 // M-type instruction. Specifically, for this example, this means: 95 // %vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16, 96 // %RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16 97 // is replaced by: 98 // %vreg16<def,tied1> = XSMADDMDP %vreg16<tied0>, %vreg18, %vreg9, 99 // %RM<imp-use>; VSLRC:%vreg16,%vreg18,%vreg9 100 // and we remove: %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9 101 102 SlotIndex FMAIdx = LIS->getInstructionIndex(MI); 103 104 VNInfo *AddendValNo = 105 LIS->getInterval(MI->getOperand(1).getReg()).Query(FMAIdx).valueIn(); 106 107 // This can be null if the register is undef. 108 if (!AddendValNo) 109 continue; 110 111 MachineInstr *AddendMI = LIS->getInstructionFromIndex(AddendValNo->def); 112 113 // The addend and this instruction must be in the same block. 114 115 if (!AddendMI || AddendMI->getParent() != MI->getParent()) 116 continue; 117 118 // The addend must be a full copy within the same register class. 119 120 if (!AddendMI->isFullCopy()) 121 continue; 122 123 unsigned AddendSrcReg = AddendMI->getOperand(1).getReg(); 124 if (TargetRegisterInfo::isVirtualRegister(AddendSrcReg)) { 125 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) != 126 MRI.getRegClass(AddendSrcReg)) 127 continue; 128 } else { 129 // If AddendSrcReg is a physical register, make sure the destination 130 // register class contains it. 131 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg()) 132 ->contains(AddendSrcReg)) 133 continue; 134 } 135 136 // In theory, there could be other uses of the addend copy before this 137 // fma. We could deal with this, but that would require additional 138 // logic below and I suspect it will not occur in any relevant 139 // situations. Additionally, check whether the copy source is killed 140 // prior to the fma. In order to replace the addend here with the 141 // source of the copy, it must still be live here. We can't use 142 // interval testing for a physical register, so as long as we're 143 // walking the MIs we may as well test liveness here. 144 // 145 // FIXME: There is a case that occurs in practice, like this: 146 // %vreg9<def> = COPY %F1; VSSRC:%vreg9 147 // ... 148 // %vreg6<def> = COPY %vreg9; VSSRC:%vreg6,%vreg9 149 // %vreg7<def> = COPY %vreg9; VSSRC:%vreg7,%vreg9 150 // %vreg9<def,tied1> = XSMADDASP %vreg9<tied0>, %vreg1, %vreg4; VSSRC: 151 // %vreg6<def,tied1> = XSMADDASP %vreg6<tied0>, %vreg1, %vreg2; VSSRC: 152 // %vreg7<def,tied1> = XSMADDASP %vreg7<tied0>, %vreg1, %vreg3; VSSRC: 153 // which prevents an otherwise-profitable transformation. 154 bool OtherUsers = false, KillsAddendSrc = false; 155 for (auto J = std::prev(I), JE = MachineBasicBlock::iterator(AddendMI); 156 J != JE; --J) { 157 if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())) { 158 OtherUsers = true; 159 break; 160 } 161 if (J->modifiesRegister(AddendSrcReg, TRI) || 162 J->killsRegister(AddendSrcReg, TRI)) { 163 KillsAddendSrc = true; 164 break; 165 } 166 } 167 168 if (OtherUsers || KillsAddendSrc) 169 continue; 170 171 // Find one of the product operands that is killed by this instruction. 172 173 unsigned KilledProdOp = 0, OtherProdOp = 0; 174 if (LIS->getInterval(MI->getOperand(2).getReg()) 175 .Query(FMAIdx).isKill()) { 176 KilledProdOp = 2; 177 OtherProdOp = 3; 178 } else if (LIS->getInterval(MI->getOperand(3).getReg()) 179 .Query(FMAIdx).isKill()) { 180 KilledProdOp = 3; 181 OtherProdOp = 2; 182 } 183 184 // If there are no killed product operands, then this transformation is 185 // likely not profitable. 186 if (!KilledProdOp) 187 continue; 188 189 // If the addend copy is used only by this MI, then the addend source 190 // register is likely not live here. This could be fixed (based on the 191 // legality checks above, the live range for the addend source register 192 // could be extended), but it seems likely that such a trivial copy can 193 // be coalesced away later, and thus is not worth the effort. 194 if (TargetRegisterInfo::isVirtualRegister(AddendSrcReg) && 195 !LIS->getInterval(AddendSrcReg).liveAt(FMAIdx)) 196 continue; 197 198 // Transform: (O2 * O3) + O1 -> (O2 * O1) + O3. 199 200 unsigned KilledProdReg = MI->getOperand(KilledProdOp).getReg(); 201 unsigned OtherProdReg = MI->getOperand(OtherProdOp).getReg(); 202 203 unsigned AddSubReg = AddendMI->getOperand(1).getSubReg(); 204 unsigned KilledProdSubReg = MI->getOperand(KilledProdOp).getSubReg(); 205 unsigned OtherProdSubReg = MI->getOperand(OtherProdOp).getSubReg(); 206 207 bool AddRegKill = AddendMI->getOperand(1).isKill(); 208 bool KilledProdRegKill = MI->getOperand(KilledProdOp).isKill(); 209 bool OtherProdRegKill = MI->getOperand(OtherProdOp).isKill(); 210 211 bool AddRegUndef = AddendMI->getOperand(1).isUndef(); 212 bool KilledProdRegUndef = MI->getOperand(KilledProdOp).isUndef(); 213 bool OtherProdRegUndef = MI->getOperand(OtherProdOp).isUndef(); 214 215 unsigned OldFMAReg = MI->getOperand(0).getReg(); 216 217 // The transformation doesn't work well with things like: 218 // %vreg5 = A-form-op %vreg5, %vreg11, %vreg5; 219 // so leave such things alone. 220 if (OldFMAReg == KilledProdReg) 221 continue; 222 223 // If there isn't a class that fits, we can't perform the transform. 224 // This is needed for correctness with a mixture of VSX and Altivec 225 // instructions to make sure that a low VSX register is not assigned to 226 // the Altivec instruction. 227 if (!MRI.constrainRegClass(KilledProdReg, 228 MRI.getRegClass(OldFMAReg))) 229 continue; 230 231 assert(OldFMAReg == AddendMI->getOperand(0).getReg() && 232 "Addend copy not tied to old FMA output!"); 233 234 DEBUG(dbgs() << "VSX FMA Mutation:\n " << *MI;); 235 236 MI->getOperand(0).setReg(KilledProdReg); 237 MI->getOperand(1).setReg(KilledProdReg); 238 MI->getOperand(3).setReg(AddendSrcReg); 239 MI->getOperand(2).setReg(OtherProdReg); 240 241 MI->getOperand(0).setSubReg(KilledProdSubReg); 242 MI->getOperand(1).setSubReg(KilledProdSubReg); 243 MI->getOperand(3).setSubReg(AddSubReg); 244 MI->getOperand(2).setSubReg(OtherProdSubReg); 245 246 MI->getOperand(1).setIsKill(KilledProdRegKill); 247 MI->getOperand(3).setIsKill(AddRegKill); 248 MI->getOperand(2).setIsKill(OtherProdRegKill); 249 250 MI->getOperand(1).setIsUndef(KilledProdRegUndef); 251 MI->getOperand(3).setIsUndef(AddRegUndef); 252 MI->getOperand(2).setIsUndef(OtherProdRegUndef); 253 254 MI->setDesc(TII->get(AltOpc)); 255 256 DEBUG(dbgs() << " -> " << *MI); 257 258 // The killed product operand was killed here, so we can reuse it now 259 // for the result of the fma. 260 261 LiveInterval &FMAInt = LIS->getInterval(OldFMAReg); 262 VNInfo *FMAValNo = FMAInt.getVNInfoAt(FMAIdx.getRegSlot()); 263 for (auto UI = MRI.reg_nodbg_begin(OldFMAReg), UE = MRI.reg_nodbg_end(); 264 UI != UE;) { 265 MachineOperand &UseMO = *UI; 266 MachineInstr *UseMI = UseMO.getParent(); 267 ++UI; 268 269 // Don't replace the result register of the copy we're about to erase. 270 if (UseMI == AddendMI) 271 continue; 272 273 UseMO.substVirtReg(KilledProdReg, KilledProdSubReg, *TRI); 274 } 275 276 // Extend the live intervals of the killed product operand to hold the 277 // fma result. 278 279 LiveInterval &NewFMAInt = LIS->getInterval(KilledProdReg); 280 for (LiveInterval::iterator AI = FMAInt.begin(), AE = FMAInt.end(); 281 AI != AE; ++AI) { 282 // Don't add the segment that corresponds to the original copy. 283 if (AI->valno == AddendValNo) 284 continue; 285 286 VNInfo *NewFMAValNo = 287 NewFMAInt.getNextValue(AI->start, 288 LIS->getVNInfoAllocator()); 289 290 NewFMAInt.addSegment(LiveInterval::Segment(AI->start, AI->end, 291 NewFMAValNo)); 292 } 293 DEBUG(dbgs() << " extended: " << NewFMAInt << '\n'); 294 295 // Extend the live interval of the addend source (it might end at the 296 // copy to be removed, or somewhere in between there and here). This 297 // is necessary only if it is a physical register. 298 if (!TargetRegisterInfo::isVirtualRegister(AddendSrcReg)) 299 for (MCRegUnitIterator Units(AddendSrcReg, TRI); Units.isValid(); 300 ++Units) { 301 unsigned Unit = *Units; 302 303 LiveRange &AddendSrcRange = LIS->getRegUnit(Unit); 304 AddendSrcRange.extendInBlock(LIS->getMBBStartIdx(&MBB), 305 FMAIdx.getRegSlot()); 306 DEBUG(dbgs() << " extended: " << AddendSrcRange << '\n'); 307 } 308 309 FMAInt.removeValNo(FMAValNo); 310 DEBUG(dbgs() << " trimmed: " << FMAInt << '\n'); 311 312 // Remove the (now unused) copy. 313 314 DEBUG(dbgs() << " removing: " << *AddendMI << '\n'); 315 LIS->RemoveMachineInstrFromMaps(AddendMI); 316 AddendMI->eraseFromParent(); 317 318 Changed = true; 319 } 320 321 return Changed; 322 } 323 324 public: 325 bool runOnMachineFunction(MachineFunction &MF) override { 326 // If we don't have VSX then go ahead and return without doing 327 // anything. 328 const PPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>(); 329 if (!STI.hasVSX()) 330 return false; 331 332 LIS = &getAnalysis<LiveIntervals>(); 333 334 TII = STI.getInstrInfo(); 335 336 bool Changed = false; 337 338 if (DisableVSXFMAMutate) 339 return Changed; 340 341 for (MachineFunction::iterator I = MF.begin(); I != MF.end();) { 342 MachineBasicBlock &B = *I++; 343 if (processBlock(B)) 344 Changed = true; 345 } 346 347 return Changed; 348 } 349 350 void getAnalysisUsage(AnalysisUsage &AU) const override { 351 AU.addRequired<LiveIntervals>(); 352 AU.addPreserved<LiveIntervals>(); 353 AU.addRequired<SlotIndexes>(); 354 AU.addPreserved<SlotIndexes>(); 355 MachineFunctionPass::getAnalysisUsage(AU); 356 } 357 }; 358 } 359 360 INITIALIZE_PASS_BEGIN(PPCVSXFMAMutate, DEBUG_TYPE, 361 "PowerPC VSX FMA Mutation", false, false) 362 INITIALIZE_PASS_DEPENDENCY(LiveIntervals) 363 INITIALIZE_PASS_DEPENDENCY(SlotIndexes) 364 INITIALIZE_PASS_END(PPCVSXFMAMutate, DEBUG_TYPE, 365 "PowerPC VSX FMA Mutation", false, false) 366 367 char &llvm::PPCVSXFMAMutateID = PPCVSXFMAMutate::ID; 368 369 char PPCVSXFMAMutate::ID = 0; 370 FunctionPass *llvm::createPPCVSXFMAMutatePass() { 371 return new PPCVSXFMAMutate(); 372 } 373
