| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerInterface.h | 124 int Rd, int Rn,
129 int Rd, int Rm, int Rs, int Rn) = 0;
144 virtual void BX(int cc, int Rn) = 0;
155 int Rn, uint32_t offset = __immed12_pre(0)) = 0;
157 int Rn, uint32_t offset = __immed12_pre(0)) = 0;
159 int Rn, uint32_t offset = __immed12_pre(0)) = 0;
161 int Rn, uint32_t offset = __immed12_pre(0)) = 0;
164 int Rn, uint32_t offset = __immed8_pre(0)) = 0;
166 int Rn, uint32_t offset = __immed8_pre(0)) = 0;
168 int Rn, uint32_t offset = __immed8_pre(0)) = 0
[all...] |
| ARMAssemblerInterface.cpp | 69 int Rn, uint32_t offset)
71 LDR(cc, Rd, Rn, offset);
74 int Rn, uint32_t offset)
76 STR(cc, Rd, Rn, offset);
79 int Rd, int Rn, uint32_t Op2)
81 dataProcessing(opADD, cc, s, Rd, Rn, Op2);
84 int Rd, int Rn, uint32_t Op2)
86 dataProcessing(opSUB, cc, s, Rd, Rn, Op2);
|
| Arm64Assembler.cpp | 341 int s, int Rd, int Rn, uint32_t Op2)
398 case opADD: *mPC++ = A64_ADD_W(Rd, Rn, Rm, shift, amount); break;
399 case opAND: *mPC++ = A64_AND_W(Rd, Rn, Rm, shift, amount); break;
400 case opORR: *mPC++ = A64_ORR_W(Rd, Rn, Rm, shift, amount); break;
401 case opMVN: *mPC++ = A64_ORN_W(Rd, Rn, Rm, shift, amount); break;
402 case opSUB: *mPC++ = A64_SUB_W(Rd, Rn, Rm, shift, amount, s);break;
409 int s, int Rd, int Rn, uint32_t Op2)
420 dataProcessingCommon(opcode, s, Wd, Rn, Op2);
424 dataProcessingCommon(opSUB, 1, mTmpReg3, Rn, Op2);
428 dataProcessingCommon(opSUB, s, Wd, Rn, Op2)
[all...] |
| ARMAssemblerProxy.cpp | 161 int Rd, int Rn, uint32_t Op2)
163 mTarget->dataProcessing(opcode, cc, s, Rd, Rn, Op2);
166 void ARMAssemblerProxy::MLA(int cc, int s, int Rd, int Rm, int Rs, int Rn) {
167 mTarget->MLA(cc, s, Rd, Rm, Rs, Rn);
195 void ARMAssemblerProxy::BX(int cc, int Rn) {
196 mTarget->BX(cc, Rn);
212 void ARMAssemblerProxy::LDR(int cc, int Rd, int Rn, uint32_t offset) {
213 mTarget->LDR(cc, Rd, Rn, offset);
215 void ARMAssemblerProxy::LDRB(int cc, int Rd, int Rn, uint32_t offset) {
216 mTarget->LDRB(cc, Rd, Rn, offset)
[all...] |
| Arm64Assembler.h | 99 int Rd, int Rn,
102 int Rd, int Rm, int Rs, int Rn);
116 virtual void BX(int cc, int Rn);
124 int Rn, uint32_t offset = 0);
126 int Rn, uint32_t Op2);
128 int Rn, uint32_t Op2);
130 int Rn, uint32_t offset = 0);
133 int Rn, uint32_t offset = 0);
135 int Rn, uint32_t offset = 0);
137 int Rn, uint32_t offset = 0)
[all...] |
| ARMAssemblerProxy.h | 80 int Rd, int Rn,
83 int Rd, int Rm, int Rs, int Rn);
97 virtual void BX(int cc, int Rn);
105 int Rn, uint32_t offset = __immed12_pre(0));
107 int Rn, uint32_t offset = __immed12_pre(0));
109 int Rn, uint32_t offset = __immed12_pre(0));
111 int Rn, uint32_t offset = __immed12_pre(0));
113 int Rn, uint32_t offset = __immed8_pre(0));
115 int Rn, uint32_t offset = __immed8_pre(0));
117 int Rn, uint32_t offset = __immed8_pre(0))
[all...] |
| ARMAssembler.h | 91 int Rd, int Rn,
94 int Rd, int Rm, int Rs, int Rn);
108 virtual void BX(int cc, int Rn);
116 int Rn, uint32_t offset = __immed12_pre(0));
118 int Rn, uint32_t offset = __immed12_pre(0));
120 int Rn, uint32_t offset = __immed12_pre(0));
122 int Rn, uint32_t offset = __immed12_pre(0));
124 int Rn, uint32_t offset = __immed8_pre(0));
126 int Rn, uint32_t offset = __immed8_pre(0));
128 int Rn, uint32_t offset = __immed8_pre(0))
[all...] |
| MIPS64Assembler.cpp | 402 int s, int Rd, int Rn, uint32_t Op2)
418 mMips->AND(Rd, Rn, src);
420 mMips->ANDI(Rd, Rn, src);
427 mMips->ADDU(Rd, Rn, src);
429 mMips->ADDIU(Rd, Rn, src);
436 mMips->SUBU(Rd, Rn, src);
438 mMips->SUBIU(Rd, Rn, src);
445 mMips->DADDU(Rd, Rn, src);
447 mMips->DADDIU(Rd, Rn, src);
454 mMips->DSUBU(Rd, Rn, src)
[all...] |
| ARMAssembler.cpp | 217 int s, int Rd, int Rn, uint32_t Op2)
219 *mPC++ = (cc<<28) | (opcode<<21) | (s<<20) | (Rn<<16) | (Rd<<12) | Op2;
229 int Rd, int Rm, int Rs, int Rn) {
231 LOG_FATAL_IF(Rd==Rm, "MLA(r%u,r%u,r%u,r%u)", Rd,Rm,Rs,Rn);
233 (Rd<<16) | (Rn<<12) | (Rs<<8) | 0x90 | Rm;
288 void ARMAssembler::BX(int cc, int Rn)
290 *mPC++ = (cc<<28) | 0x12FFF10 | Rn;
299 void ARMAssembler::LDR(int cc, int Rd, int Rn, uint32_t offset) {
300 *mPC++ = (cc<<28) | (1<<26) | (1<<20) | (Rn<<16) | (Rd<<12) | offset;
302 void ARMAssembler::LDRB(int cc, int Rd, int Rn, uint32_t offset)
[all...] |
| MIPS64Assembler.h | 96 int Rd, int Rn,
99 int Rd, int Rm, int Rs, int Rn);
113 virtual void BX(int cc, int Rn);
121 int Rn, uint32_t offset = 0);
123 int Rn, uint32_t offset = 0);
125 int Rn, uint32_t offset = 0);
127 int Rn, uint32_t offset = 0);
129 int Rn, uint32_t offset = 0);
131 int Rn, uint32_t offset = 0);
133 int Rn, uint32_t offset = 0)
[all...] |
| MIPSAssembler.cpp | 418 int s, int Rd, int Rn, uint32_t Op2)
435 mMips->AND(Rd, Rn, src);
437 mMips->ANDI(Rd, Rn, src);
444 mMips->ADDU(Rd, Rn, src);
446 mMips->ADDIU(Rd, Rn, src);
453 mMips->SUBU(Rd, Rn, src);
455 mMips->SUBIU(Rd, Rn, src);
461 mMips->XOR(Rd, Rn, src);
463 mMips->XORI(Rd, Rn, src);
469 mMips->OR(Rd, Rn, src)
[all...] |
| MIPSAssembler.h | 91 int Rd, int Rn,
94 int Rd, int Rm, int Rs, int Rn);
108 virtual void BX(int cc, int Rn);
116 int Rn, uint32_t offset = 0);
118 int Rn, uint32_t offset = 0);
120 int Rn, uint32_t offset = 0);
122 int Rn, uint32_t offset = 0);
124 int Rn, uint32_t offset = 0);
126 int Rn, uint32_t offset = 0);
128 int Rn, uint32_t offset = 0)
[all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| tic30.h | 190 #define Rn 0x0001
209 #define GAddr1 Rn | Direct | Indirect | Imm16
211 #define TAddr1 op3T1 | Rn | Indirect
212 #define TAddr2 op3T2 | Rn | Indirect
213 #define Reg Rn | ARn
247 { "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
251 { "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
252 { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
347 { "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
408 { "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt }
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| arm3-bad.l | 2 .*arm3-bad.s:4: Error: Rn must not overlap other operands -- `swp r0,r1,\[r0\]'
3 .*arm3-bad.s:5: Error: Rn must not overlap other operands -- `swp r1,r0,\[r0\]'
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| addsub.s | 27 .macro adjust_rm op, rd, rn, rm_r, rm_n, extend, amount
35 \op \rd, \rn, W\()\rm_n, \extend
37 \op \rd, \rn, W\()\rm_n, \extend #\amount
46 \op \rd, \rn, \rm_r\()\rm_n, \extend
48 \op \rd, \rn, \rm_r\()\rm_n, \extend #\amount
55 .macro do_addsub_ext type, op, Rn, reg, extend, amount
59 \op \reg\()16, \Rn, \reg\()1
62 adjust_rm \op, \reg\()16, \Rn, \reg, 1, \extend
64 adjust_rm \op, \reg\()16, \Rn, \reg, 1, \extend, \amount
71 \op \reg\()ZR, \Rn, \reg\()
[all...] |
| /art/disassembler/ |
| disassembler_arm.cc | 315 ArmRegister rn(instruction, 16);
316 if (rn.r == 0xf) {
322 args << "[" << rn << ", #" << offset << "]";
324 args << "[" << rn << ", #" << offset << "]!";
326 args << "[" << rn << "], #" << offset;
330 if (rn.r == 9) {
516 // |111|01|00|op|0|WL| Rn | |
525 ArmRegister Rn(instr, 16);
530 args << Rn << (W == 0 ? "" : "!") << ", ";
532 if (Rn.r != 13)
[all...] |
| /prebuilts/go/darwin-x86/src/crypto/rc4/ |
| rc4_arm.s | 12 #define Rn R2
26 MOVW n+8(FP), Rn
56 CMP Rk, Rn
|
| /prebuilts/go/linux-x86/src/crypto/rc4/ |
| rc4_arm.s | 12 #define Rn R2
26 MOVW n+8(FP), Rn
56 CMP Rk, Rn
|
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /system/core/libpixelflinger/tests/arch-arm64/assembler/ |
| arm64_assembler_test.cpp | 415 uint32_t Rn = 1, uint32_t Rm = 2, uint32_t Rs = 3)
429 regs[Rn] = test.RnValue;
450 case INSTR_ADD: a64asm->ADD(test.cond, test.setFlags, Rd,Rn,op2); break;
451 case INSTR_SUB: a64asm->SUB(test.cond, test.setFlags, Rd,Rn,op2); break;
452 case INSTR_RSB: a64asm->RSB(test.cond, test.setFlags, Rd,Rn,op2); break;
453 case INSTR_AND: a64asm->AND(test.cond, test.setFlags, Rd,Rn,op2); break;
454 case INSTR_ORR: a64asm->ORR(test.cond, test.setFlags, Rd,Rn,op2); break;
455 case INSTR_BIC: a64asm->BIC(test.cond, test.setFlags, Rd,Rn,op2); break;
457 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break;
458 case INSTR_CMP: a64asm->CMP(test.cond, Rn,op2); break
[all...] |
| /system/core/libpixelflinger/tests/arch-mips64/assembler/ |
| mips64_assembler_test.cpp | 373 uint32_t Rn = R_t0, uint32_t Rm = R_t1, uint32_t Rs = R_t2)
387 regs[Rn] = test.RnValue;
412 case INSTR_ADD: a64asm->ADD(test.cond, test.setFlags, Rd,Rn,op2); break;
413 case INSTR_SUB: a64asm->SUB(test.cond, test.setFlags, Rd,Rn,op2); break;
414 case INSTR_RSB: a64asm->RSB(test.cond, test.setFlags, Rd,Rn,op2); break;
415 case INSTR_AND: a64asm->AND(test.cond, test.setFlags, Rd,Rn,op2); break;
416 case INSTR_ORR: a64asm->ORR(test.cond, test.setFlags, Rd,Rn,op2); break;
417 case INSTR_BIC: a64asm->BIC(test.cond, test.setFlags, Rd,Rn,op2); break;
419 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break;
420 case INSTR_CMP: a64asm->CMP(test.cond, Rn,op2); break
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-tbl.h | 1237 {"adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
1238 {"adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
1239 {"sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF},
1241 {"sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF},
1259 {"add", 0xb000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
1260 {"adds", 0x2b000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
1261 {"cmn", 0x2b00001f, 0x7f20001f, addsub_shift, 0, CORE, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF},
1262 {"sub", 0x4b000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
1264 {"subs", 0x6b000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
1265 {"cmp", 0x6b00001f, 0x7f20001f, addsub_shift, 0, CORE, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF}
[all...] |
| /external/vixl/src/vixl/a64/ |
| assembler-a64.cc | 648 Emit(BR | Rn(xn));
654 Emit(BLR | Rn(xn));
660 Emit(RET | Rn(xn));
735 Emit(op | (vd.IsQ() ? NEON_Q : 0) | Rm(vm) | Rn(vn) | Rd(vd));
895 const Register& rn,
897 AddSub(rd, rn, operand, LeaveFlags, ADD);
902 const Register& rn,
904 AddSub(rd, rn, operand, SetFlags, ADD);
908 void Assembler::cmn(const Register& rn,
910 Register zr = AppropriateZeroRegFor(rn);
[all...] |
| simulator-a64.cc | 843 const Instruction* target = Instruction::Cast(xreg(instr->Rn()));
899 reg(reg_size, instr->Rn(), instr->RnMode()),
907 reg(reg_size, instr->Rn(), instr->RnMode()),
956 reg(reg_size, instr->Rn()),
984 int64_t op1 = reg(reg_size, instr->Rn());
1297 unsigned rn = instr->Rn(); local
1653 int32_t rn = wreg(instr->Rn()); local
1666 int64_t rn = xreg(instr->Rn()); local
1679 uint32_t rn = static_cast<uint32_t>(wreg(instr->Rn())); local
1690 uint64_t rn = static_cast<uint64_t>(xreg(instr->Rn())); local
2165 SimVRegister& rn = vreg(instr->Rn()); local
2213 SimVRegister& rn = vreg(instr->Rn()); local
2437 SimVRegister& rn = vreg(instr->Rn()); local
2571 SimVRegister& rn = vreg(instr->Rn()); local
2695 SimVRegister& rn = vreg(instr->Rn()); local
2761 SimVRegister& rn = vreg(instr->Rn()); local
2799 SimVRegister& rn = vreg(instr->Rn()); local
2905 SimVRegister& rn = vreg(instr->Rn()); local
2941 SimVRegister& rn = vreg(instr->Rn()); local
3404 SimVRegister& rn = vreg(instr->Rn()); local
3474 SimVRegister& rn = vreg(instr->Rn()); local
3491 SimVRegister& rn = vreg(instr->Rn()); local
3566 SimVRegister& rn = vreg(instr->Rn()); local
3612 SimVRegister& rn = vreg(instr->Rn()); local
3630 SimVRegister& rn = vreg(instr->Rn()); local
3646 SimVRegister& rn = vreg(instr->Rn()); local
3698 SimVRegister& rn = vreg(instr->Rn()); local
3827 SimVRegister& rn = vreg(instr->Rn()); local
3853 SimVRegister& rn = vreg(instr->Rn()); local
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 653 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
658 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
661 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
[all...] |
