| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 454 // with an immediate value. Not checking the mask here, since we handle
620 int Mask = 0, ImmValue = 0;
622 Mask, ImmValue);
[all...] |
| HexagonISelDAGToDAG.cpp | 114 // the single bit 32 bit mask represents.
125 // 16 bit mask represents. Used in Clr and Set bit immediate memops.
131 // 8 bit mask represents. Used in Clr and Set bit immediate memops.
776 SDNode *Mask = CurDAG->getMachineNode(Hexagon::C2_mask, dl, MVT::i64, Op0);
790 SDValue(Mask,0), SDValue(OnesReg,0));
797 SDValue(Mask,0), SDValue(OnesReg,0));
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 564 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
566 if (!Mask)
569 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
572 return SDValue(); // Mask+1 is not a power of 2
660 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
661 // where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
686 APInt Mask, InvMask;
688 // If Op0Op0 is an appropriate mask, try to find it's inverse in either
692 if (isVSplat(Op0Op0, Mask, IsLittleEndian))
[all...] |
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 803 uint64_t Mask = 1;
805 if (ErrorInfo & Mask) {
807 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
809 Mask <<= 1;
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineAddSub.cpp | [all...] |
| InstCombineAndOrXor.cpp | 41 /// a three bit mask. It also returns whether it is an ordered predicate by
190 // NOTE: This reduces the number of bits set in the & mask, which
359 /// This is part of an expression (LHS +/- RHS) & Mask, where isSub determines
362 /// ((A & N) +/- B) & Mask -> (A +/- B) & Mask iff N&Mask == Mask
363 /// ((A | N) +/- B) & Mask -> (A +/- B) & Mask iff N&Mask ==
707 unsigned mask = foldLogOpOfMaskedICmpsHelper(A, B, C, D, E, LHS, RHS, local
[all...] |
| InstCombineCalls.cpp | 335 // [3:0] - zero mask for each 32-bit lane
346 // If all zero mask bits are set, this was just a weird way to
358 // If the zero mask is being used with a single input or the zero mask
366 // The zero mask may override the previous insert operation.
453 // Constant Fold - shift Index'th bit to lowest position and mask off
548 APInt Mask = APInt::getLowBitsSet(64, Length).shl(Index);
549 V00 = V00 & ~Mask;
574 /// The shuffle mask for a perm2*128 selects any two halves of two 256-bit
576 /// then ignore that half of the mask and clear that half of the vector
[all...] |
| InstCombineCasts.cpp | 370 APInt Mask = APInt::getHighBitsSet(OrigBitWidth, OrigBitWidth-BitWidth);
371 if (IC.MaskedValueIsZero(I->getOperand(0), Mask, 0, CxtI) &&
372 IC.MaskedValueIsZero(I->getOperand(1), Mask, 0, CxtI)) {
685 // Mask off any bits that are set and won't be shifted away.
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 93 // The lane mask is simply the union of all sub-indices.
97 assert(M && "Missing lane mask, sub-register cycle?");
[all...] |
| /external/pdfium/third_party/lcms2-2.6/src/ |
| cmspack.c | 60 cmsUInt32Number Mask;
67 cmsUInt32Number Mask;
[all...] |
| /external/vixl/src/vixl/a64/ |
| instructions-a64.h | 186 Instr Mask(uint32_t mask) const {
187 return InstructionBits() & mask;
212 return CalcLSDataSize(static_cast<LoadStoreOp>(Mask(LoadStoreMask)));
217 static_cast<LoadStorePairOp>(Mask(LoadStorePairMask)));
230 return Mask(ConditionalBranchFMask) == ConditionalBranchFixed;
234 return Mask(UnconditionalBranchFMask) == UnconditionalBranchFixed;
238 return Mask(CompareBranchFMask) == CompareBranchFixed;
242 return Mask(TestBranchFMask) == TestBranchFixed;
250 return Mask(PCRelAddressingFMask) == PCRelAddressingFixed
[all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_2_7/ |
| BitcodeReader.cpp | [all...] |
| /frameworks/compile/slang/ |
| slang_rs_reflection.cpp | 357 std::string Mask, MaskLiteralType;
359 Mask = "0xff";
362 Mask = "0xffff";
365 Mask = "0xffffffffL";
372 // Cast the mask to the appropriate type.
374 Mask = "(" + DestIntegerType + ") " + Mask;
376 return "((" + DestIntegerType + ") ((" + Value + ") & " + Mask + "))";
[all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/ |
| routprot.h | 159 DWORD Mask;
|
| wincodec.h | 329 BYTE *Mask;
[all...] |
| /external/clang/utils/TableGen/ |
| NeonEmitter.cpp | [all...] |
| /external/llvm/include/llvm/IR/ |
| Instructions.h | [all...] |
| /external/llvm/lib/Analysis/ |
| ValueTracking.cpp | 208 static bool MaskedValueIsZero(Value *V, const APInt &Mask, const DataLayout &DL,
211 bool llvm::MaskedValueIsZero(Value *V, const APInt &Mask, const DataLayout &DL,
214 return ::MaskedValueIsZero(V, Mask, DL, Depth,
390 APInt Mask = APInt::getHighBitsSet(BitWidth, CommonPrefixBits);
391 KnownOne &= Range.getUnsignedMax() & Mask;
392 KnownZero &= ~Range.getUnsignedMax() & Mask;
[all...] |
| /external/llvm/lib/Bitcode/Reader/ |
| BitcodeReader.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 384 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
395 "Mask size mismatches value type size!");
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | [all...] |
