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  /external/llvm/lib/Target/Mips/Disassembler/
MipsDisassembler.cpp 1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
10 // This file is part of the Mips Disassembler.
14 #include "Mips.h"
27 #define DEBUG_TYPE "mips-disassembler"
39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
42 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
43 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
45 return STI.getFeatureBits()[Mips::FeatureMips32r6];
48 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
50 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips];
    [all...]
  /external/llvm/lib/Target/Mips/
MipsConstantIslandPass.cpp 24 #include "Mips.h"
49 #define DEBUG_TYPE "mips-constant-islands"
58 AlignConstantIslands("mips-align-constant-islands", cl::Hidden, cl::init(true),
66 "mips-constant-islands-small-offset",
76 "mips-constant-islands-no-load-relaxation",
83 case Mips::Bimm16:
84 case Mips::BimmX16:
85 case Mips::Bteqz16:
86 case Mips::BteqzX16:
87 case Mips::Btnez16
    [all...]
MipsISelLowering.cpp 1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
44 #define DEBUG_TYPE "mips-lower"
50 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
54 cl::desc("MIPS: Don't trap on integer division by zero."),
58 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
59 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_6
    [all...]
Mips16ISelDAGToDAG.cpp 16 #include "Mips.h"
37 #define DEBUG_TYPE "mips-isel"
55 unsigned Opcode = Mips::Mflo16;
60 unsigned Opcode = Mips::Mfhi16;
78 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
84 BuildMI(MBB, I, DL, TII.get(Mips::GotPrologue16), V0).
89 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
90 BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
109 BuildMI(MBB, I, DL, TII.get(Mips::MoveR3216), Mips16SPAliasReg)
110 .addReg(Mips::SP)
    [all...]
Mips16RegisterInfo.cpp 15 #include "Mips.h"
68 TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true);
69 TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true);
76 return &Mips::CPU16RegsRegClass;
106 FrameReg = Mips::SP;
110 FrameReg = Mips::S0;
116 FrameReg = Mips::SP;
MipsAnalyzeImmediate.cpp 10 #include "Mips.h"
131 ADDiu = Mips::ADDiu;
132 ORi = Mips::ORi;
133 SLL = Mips::SLL;
134 LUi = Mips::LUi;
136 ADDiu = Mips::DADDiu;
137 ORi = Mips::ORi64;
138 SLL = Mips::DSLL;
139 LUi = Mips::LUi64;
Makefile 1 ##===- lib/Target/Mips/Makefile ----------------------------*- Makefile -*-===##
12 TARGET = Mips
MipsDelaySlotFiller.cpp 1 //===-- MipsDelaySlotFiller.cpp - Mips Delay Slot Filler ------------------===//
15 #include "Mips.h"
42 "disable-mips-delay-filler",
48 "disable-mips-df-forward-search",
50 cl::desc("Disallow MIPS delay filler to search forward."),
54 "disable-mips-df-succbb-search",
56 cl::desc("Disallow MIPS delay filler to search successor basic blocks."),
60 "disable-mips-df-backward-search",
62 cl::desc("Disallow MIPS delay filler to search backward."),
174 return "Mips Delay Slot Filler"
    [all...]
MipsMCInstLower.cpp 1 //===-- MipsMCInstLower.cpp - Convert Mips MachineInstr to MCInst ---------===//
10 // This file contains code to lower Mips MachineInstrs to their corresponding
173 OutMI.setOpcode(Mips::LUi);
205 case Mips::LONG_BRANCH_LUi:
208 case Mips::LONG_BRANCH_ADDiu:
209 lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu,
212 case Mips::LONG_BRANCH_DADDiu:
215 lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu,
218 lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu,
MipsFrameLowering.cpp 1 //===-- MipsFrameLowering.cpp - Mips Frame Information --------------------===//
10 // This file contains the Mips implementation of TargetFrameLowering class.
150 unsigned SP = STI.getABI().IsN64() ? Mips::SP_64 : Mips::SP;
154 if (I->getOpcode() == Mips::ADJCALLSTACKDOWN)
MipsSEISelLowering.cpp 27 #define DEBUG_TYPE "mips-isel"
30 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
31 cl::desc("MIPS: Enable tail calls."), cl::init(false));
42 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
45 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
63 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
87 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
88 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
89 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
90 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass)
    [all...]
MipsInstrInfo.cpp 1 //===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
34 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
54 BuildMI(MBB, MI, DL, get(Mips::NOP));
127 "# of Mips branch conditions must be <= 3!");
172 "Invalid Mips branch condition!");
270 case Mips::CONSTPOOL_ENTRY:
MipsOptimizePICCall.cpp 15 #include "Mips.h"
26 #define DEBUG_TYPE "optimize-mips-pic-call"
28 static cl::opt<bool> LoadTargetFromGOT("mips-load-target-from-got",
33 static cl::opt<bool> EraseGPOpnd("mips-erase-gp-opnd",
64 const char *getPassName() const override { return "Mips OptimizePICCall"; }
135 unsigned DstReg = getRegTy(SrcReg, MF) == MVT::i32 ? Mips::T9 : Mips::T9_64;
148 unsigned Reg = Ty == MVT::i32 ? Mips::GP : Mips::GP_64;
  /external/llvm/lib/Target/Mips/MCTargetDesc/
MipsTargetStreamer.cpp 1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
10 // This file provides Mips specific target streamer methods.
458 if (Features[Mips::FeatureMips64r6])
460 else if (Features[Mips::FeatureMips64r2] ||
461 Features[Mips::FeatureMips64r3] ||
462 Features[Mips::FeatureMips64r5])
464 else if (Features[Mips::FeatureMips64])
466 else if (Features[Mips::FeatureMips5])
468 else if (Features[Mips::FeatureMips4])
470 else if (Features[Mips::FeatureMips3]
    [all...]
MipsFixupKinds.h 1 //===-- MipsFixupKinds.h - Mips Specific Fixup Entries ----------*- C++ -*-===//
16 namespace Mips {
22 // MCFixupKindInfo Infos[Mips::NumTargetFixupKinds]
207 } // namespace Mips
MipsAsmBackend.h 1 //===-- MipsAsmBackend.h - Mips Asm Backend ------------------------------===//
48 return Mips::NumTargetFixupKinds;
  /frameworks/compile/mclinker/
Android.mk 31 # MIPS Code Generation Libraries
33 lib/Target/Mips \
34 lib/Target/Mips/TargetInfo
  /external/llvm/device/include/llvm/Config/
Targets.def 29 LLVM_TARGET(Mips)
  /external/llvm/
Android.mk 80 # MIPS Code Generation Libraries
82 lib/Target/Mips \
83 lib/Target/Mips/AsmParser \
84 lib/Target/Mips/InstPrinter \
85 lib/Target/Mips/Disassembler \
86 lib/Target/Mips/MCTargetDesc \
87 lib/Target/Mips/TargetInfo
  /external/llvm/include/llvm/Config/
llvm-platform-config.h 69 #define LLVM_NATIVE_ARCH Mips
  /external/llvm/include/llvm/Support/
MipsABIFlags.h 1 //===--- MipsABIFlags.h - MIPS ABI flags ----------------------------------===//
11 // in the .MIPS.abiflags section.
13 // https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking
21 namespace Mips {
38 AFL_ASE_MIPS3D = 0x00000020, // MIPS-3D ASE
56 AFL_EXT_5900 = 6, // MIPS R5900 instruction
57 AFL_EXT_4650 = 7, // MIPS R4650 instruction
61 AFL_EXT_10000 = 11, // MIPS R10000 instruction
75 // MIPS object attribute tags
  /build/core/clang/
mips.mk 1 # Clang flags for mips arch, target or host.
18 # Temporary workaround for Mips clang++ problem, creates
23 # We don't have any mips flags to substitute yet.
24 define subst-clang-incompatible-mips-flags
mips64.mk 18 # Temporary workaround for Mips clang++ problem creating
  /external/llvm/lib/Target/Mips/InstPrinter/
MipsInstPrinter.h 1 //=== MipsInstPrinter.h - Convert Mips MCInst to assembly syntax -*- C++ -*-==//
10 // This class prints a Mips MCInst to a .s file.
22 namespace Mips {
23 // Mips Branch Codes
32 // Mips Condition Codes
73 const char *MipsFCCToString(Mips::CondCode CC);
74 } // end namespace Mips
  /external/llvm/tools/llvm-readobj/
ELFDumper.cpp     [all...]

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