| /prebuilts/go/darwin-x86/src/regexp/syntax/ |
| regexp.go | 19 Op Op // operator
30 // An Op is a single regular expression operator.
31 type Op uint8
38 OpNoMatch Op = 1 + iota // matches no strings
59 const opPseudo Op = 128 // where pseudo-ops start
66 if x.Op != y.Op {
69 switch x.Op {
116 switch re.Op {
[all...] |
| /prebuilts/go/linux-x86/src/regexp/syntax/ |
| regexp.go | 19 Op Op // operator
30 // An Op is a single regular expression operator.
31 type Op uint8
38 OpNoMatch Op = 1 + iota // matches no strings
59 const opPseudo Op = 128 // where pseudo-ops start
66 if x.Op != y.Op {
69 switch x.Op {
116 switch re.Op {
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 229 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
233 return MI.getOperand(Op).getReg() == ARM::CPSR;
237 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
239 unsigned SoImm = MI.getOperand(Op).getImm();
253 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
255 unsigned SoImm = MI.getOperand(Op).getImm();
271 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
273 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
275 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
278 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 136 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
[all...] |
| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| AMDGPUAsmParser.cpp | 490 auto Op = llvm::make_unique<AMDGPUOperand>(Immediate);
491 Op->Imm.Val = Val;
492 Op->Imm.IsFPImm = IsFPImm;
493 Op->Imm.Type = Type;
494 Op->Imm.Mods = {false, false, false};
495 Op->StartLoc = Loc;
496 Op->EndLoc = Loc;
497 return Op;
515 auto Op = llvm::make_unique<AMDGPUOperand>(Register);
516 Op->Reg.RegNo = RegNo
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 612 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
615 switch (Op.getOpcode()) {
616 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
617 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
618 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
619 case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
621 case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG);
622 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY);
623 case ISD::USUBO: return LowerUADDSUBO(Op, DAG, ISD::SUB, AMDGPUISD::BORROW);
625 case ISD::FSIN: return LowerTrig(Op, DAG)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86AsmPrinter.cpp | 229 unsigned Op, raw_ostream &O,
231 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
232 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
233 const MachineOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
267 printOperand(P, MI, Op+X86::AddrBaseReg, O, Modifier);
271 printOperand(P, MI, Op+X86::AddrIndexReg, O, Modifier);
272 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
281 unsigned Op, raw_ostream &O,
283 assert(isMem(*MI, Op) && "Invalid memory reference!");
284 const MachineOperand &Segment = MI->getOperand(Op+X86::AddrSegmentReg)
[all...] |
| /frameworks/native/libs/vr/libpdx/private/pdx/rpc/ |
| variant.h | 177 template <typename Op>
178 decltype(auto) Visit(std::int32_t target_index, Op&& op) {
180 return std::forward<Op>(op)(get(TypeTag<Type>{}));
182 return std::forward<Op>(op)(get(TypeTag<EmptyVariant>{}));
184 template <typename Op>
185 decltype(auto) Visit(std::int32_t target_index, Op&& op) const
631 Op&& op; member in struct:android::pdx::CallOp
[all...] |
| /external/clang/lib/StaticAnalyzer/Core/ |
| SimpleConstraintManager.cpp | 143 BinaryOperator::Opcode op = SE->getOpcode(); local
144 if (BinaryOperator::isComparisonOp(op)) {
146 op = BinaryOperator::negateComparisonOp(op);
148 return assumeSymRel(state, SE->getLHS(), op, SE->getRHS());
159 BinaryOperator::Opcode Op = SSE->getOpcode();
160 assert(BinaryOperator::isComparisonOp(Op));
170 Op = BinaryOperator::reverseComparisonOp(Op);
172 Op = BinaryOperator::negateComparisonOp(Op)
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/compile/internal/gc/ |
| select.go | 20 if ncase.Op != OXCASE {
21 Fatalf("typecheckselect %v", ncase.Op)
39 switch n.Op {
47 if (n.Right.Op == OCONVNOP || n.Right.Op == OCONVIFACE) && n.Right.Implicit {
51 if n.Right.Op != ORECV {
56 n.Op = OSELRECV
60 if n.Rlist.First().Op != ORECV {
65 n.Op = OSELRECV2
109 // optimization: one-case select: single op
[all...] |
| typecheck.go | 28 // rewrites n->op to be more specific in some cases.
33 if n != nil && n.Op == ONONAME && n.Sym != nil {
36 if r.Op != OIOTA {
104 if n := stack[i]; n.Op == cur.Op {
132 for n.Op == OPAREN {
142 switch n.Op {
156 switch n.Op {
206 switch n.Op {
255 switch n.Op {
[all...] |
| /prebuilts/go/linux-x86/src/cmd/compile/internal/gc/ |
| select.go | 20 if ncase.Op != OXCASE {
21 Fatalf("typecheckselect %v", ncase.Op)
39 switch n.Op {
47 if (n.Right.Op == OCONVNOP || n.Right.Op == OCONVIFACE) && n.Right.Implicit {
51 if n.Right.Op != ORECV {
56 n.Op = OSELRECV
60 if n.Rlist.First().Op != ORECV {
65 n.Op = OSELRECV2
109 // optimization: one-case select: single op
[all...] |
| typecheck.go | 28 // rewrites n->op to be more specific in some cases.
33 if n != nil && n.Op == ONONAME && n.Sym != nil {
36 if r.Op != OIOTA {
104 if n := stack[i]; n.Op == cur.Op {
132 for n.Op == OPAREN {
142 switch n.Op {
156 switch n.Op {
206 switch n.Op {
255 switch n.Op {
[all...] |
| /prebuilts/ndk/r13/sources/third_party/shaderc/third_party/glslang/SPIRV/ |
| SPVRemapper.h | 145 typedef std::function<bool(spv::Op, unsigned start)> instfn_t;
165 bool isConstOp(spv::Op opCode) const;
166 bool isTypeOp(spv::Op opCode) const;
167 bool isStripOp(spv::Op opCode) const;
168 bool isFlowCtrl(spv::Op opCode) const;
169 range_t literalRange(spv::Op opCode) const;
170 range_t typeRange(spv::Op opCode) const;
171 range_t constRange(spv::Op opCode) const;
175 spv::Op asOpCode(unsigned word) const { return opOpCode(spv[word]); }
183 static spv::Op opOpCode(spirword_t data) { return spv::Op(data & spv::OpCodeMask);
[all...] |
| /prebuilts/ndk/r13/sources/third_party/vulkan/glslang/SPIRV/ |
| SPVRemapper.h | 145 typedef std::function<bool(spv::Op, unsigned start)> instfn_t;
165 bool isConstOp(spv::Op opCode) const;
166 bool isTypeOp(spv::Op opCode) const;
167 bool isStripOp(spv::Op opCode) const;
168 bool isFlowCtrl(spv::Op opCode) const;
169 range_t literalRange(spv::Op opCode) const;
170 range_t typeRange(spv::Op opCode) const;
171 range_t constRange(spv::Op opCode) const;
175 spv::Op asOpCode(unsigned word) const { return opOpCode(spv[word]); }
183 static spv::Op opOpCode(spirword_t data) { return spv::Op(data & spv::OpCodeMask);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 738 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
740 switch (Op.getOpcode()) {
[all...] |
| /external/swiftshader/third_party/LLVM/lib/VMCore/ |
| Instructions.cpp | 125 Op<-1>().set(0);
144 if (NumOps < 2) NumOps = 2; // 2 op PHI nodes are VERY common.
261 Op<-1>() = Func;
283 Op<-1>() = Func;
516 Op<-3>() = Fn;
517 Op<-2>() = IfNormal;
518 Op<-1>() = IfException;
593 Op<0>() = RI.Op<0>();
602 Op<0>() = retVal
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 166 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
167 switch (Op.getOpcode())
169 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
170 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
171 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
172 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
173 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
174 case ISD::LOAD: return LowerLOAD(Op, DAG);
175 case ISD::STORE: return LowerSTORE(Op, DAG);
176 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 163 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
165 switch (Op.getOpcode()) {
166 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
167 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
168 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
169 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
170 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
689 SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
690 SDValue Chain = Op.getOperand(0);
691 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get()
[all...] |
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| CodeGenInstruction.cpp | 155 CGIOperandList::ParseOperandName(const std::string &Op, bool AllowWholeOp) {
156 if (Op.empty() || Op[0] != '$')
157 throw TheDef->getName() + ": Illegal operand name: '" + Op + "'";
159 std::string OpName = Op.substr(1);
167 throw TheDef->getName() + ": illegal empty suboperand name in '" +Op +"'";
178 " whole operand part of complex operand '" + Op + "'";
187 throw TheDef->getName() + ": unknown suboperand name in '" + Op + "'";
195 throw TheDef->getName() + ": unknown suboperand name in '" + Op + "'";
209 std::pair<unsigned,unsigned> Op = Ops.ParseOperandName(Name, false)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 175 const RTLIB::Libcall Op;
235 setLibcallName(LC.Op, LC.Name);
237 setCmpLibcallCC(LC.Op, LC.Cond);
259 const RTLIB::Libcall Op;
348 setLibcallName(LC.Op, LC.Name);
349 setLibcallCallingConv(LC.Op, LC.CC);
351 setCmpLibcallCC(LC.Op, LC.Cond);
358 const RTLIB::Libcall Op;
371 setLibcallName(LC.Op, LC.Name);
372 setLibcallCallingConv(LC.Op, LC.CC)
[all...] |
| /external/eigen/Eigen/src/SparseCore/ |
| SparseUtil.h | 21 #define EIGEN_SPARSE_INHERIT_ASSIGNMENT_OPERATOR(Derived, Op) \
23 EIGEN_STRONG_INLINE Derived& operator Op(const Eigen::SparseMatrixBase<OtherDerived>& other) \
25 return Base::operator Op(other.derived()); \
27 EIGEN_STRONG_INLINE Derived& operator Op(const Derived& other) \
29 return Base::operator Op(other); \
32 #define EIGEN_SPARSE_INHERIT_SCALAR_ASSIGNMENT_OPERATOR(Derived, Op) \
34 EIGEN_STRONG_INLINE Derived& operator Op(const Other& scalar) \
36 return Base::operator Op(scalar); \
|
| /external/llvm/include/llvm/MC/ |
| MCWinEH.h | 27 Instruction(unsigned Op, MCSymbol *L, unsigned Reg, unsigned Off)
28 : Label(L), Offset(Off), Register(Reg), Operation(Op) {}
|
| /external/llvm/lib/Bitcode/Writer/ |
| ValueEnumerator.cpp | 63 for (const Value *Op : C->operands())
64 if (!isa<BasicBlock>(Op) && !isa<GlobalValue>(Op))
65 orderValue(Op, OM);
129 for (const Value *Op : I.operands())
130 if ((isa<Constant>(*Op) && !isa<GlobalValue>(*Op)) ||
131 isa<InlineAsm>(*Op))
132 orderValue(Op, OM);
225 for (const Value *Op : C->operands()
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 44 unsigned Op;
46 Op = NVPTX::IMOV1rr;
48 Op = NVPTX::IMOV16rr;
50 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr
53 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr
56 Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr
59 Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr
64 BuildMI(MBB, I, DL, get(Op), DestReg)
|
