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    Searched defs:CPUID (Results 1 - 13 of 13) sorted by null

  /external/swiftshader/src/Common/
CPUID.hpp 28 class CPUID
86 inline bool CPUID::supportsMMX()
91 inline bool CPUID::supportsCMOV()
96 inline bool CPUID::supportsMMX2()
101 inline bool CPUID::supportsSSE()
106 inline bool CPUID::supportsSSE2()
111 inline bool CPUID::supportsSSE3()
116 inline bool CPUID::supportsSSSE3()
121 inline bool CPUID::supportsSSE4_1()
126 inline int CPUID::coreCount(
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  /external/swiftshader/src/Reactor/
SubzeroReactor.cpp 74 class CPUID
81 static void cpuid(int registers[4], int info) function in class:__anon35662::CPUID
87 __asm volatile("cpuid": "=a" (registers[0]), "=b" (registers[1]), "=c" (registers[2]), "=d" (registers[3]): "a" (info));
112 cpuid(registers, 1);
120 const bool CPUID::ARM = CPUID::detectARM();
121 const bool CPUID::SSE4_1 = CPUID::detectSSE4_1();
123 const bool emulateMismatchedBitCast = CPUID::ARM;
245 if(CPUID::ARM
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  /toolchain/binutils/binutils-2.27/include/opcode/
convex.h 64 #define CPUID 20
88 "cpuid",
996 {0,0,lr,CPUID,S,0}, /* mov */
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  /device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
core_cm0.h 336 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
347 /* SCB CPUID Register Definitions */
348 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
349 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
351 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
352 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
354 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
355 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
357 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position *
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core_cm0plus.h 347 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
362 /* SCB CPUID Register Definitions */
363 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
364 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
366 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
367 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
369 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
370 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
372 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position *
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core_sc000.h 342 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
355 /* SCB CPUID Register Definitions */
356 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
357 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
359 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
360 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
362 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
363 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
365 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position *
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core_cm3.h 350 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
373 /* SCB CPUID Register Definitions */
374 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
375 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
377 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
378 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
380 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
381 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
383 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position *
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core_sc300.h 350 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
373 /* SCB CPUID Register Definitions */
374 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
375 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
377 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
378 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
380 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
381 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
383 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position *
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core_cm4.h 397 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
420 /* SCB CPUID Register Definitions */
421 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
422 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
424 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
425 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
427 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
428 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
430 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position *
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core_cm7.h 412 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
464 /* SCB CPUID Register Definitions */
465 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
466 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
468 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
469 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
471 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
472 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
474 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position *
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  /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/x86/x86asm/
tables.go     [all...]
  /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/x86/x86asm/
tables.go     [all...]
  /external/mesa3d/src/mesa/x86/
assyntax.h     [all...]

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