Home | History | Annotate | Download | only in aarch32 
      1 // Copyright 2017, VIXL authors
      2 // All rights reserved.
      3 //
      4 // Redistribution and use in source and binary forms, with or without
      5 // modification, are permitted provided that the following conditions are met:
      6 //
      7 //   * Redistributions of source code must retain the above copyright notice,
      8 //     this list of conditions and the following disclaimer.
      9 //   * Redistributions in binary form must reproduce the above copyright notice,
     10 //     this list of conditions and the following disclaimer in the documentation
     11 //     and/or other materials provided with the distribution.
     12 //   * Neither the name of ARM Limited nor the names of its contributors may be
     13 //     used to endorse or promote products derived from this software without
     14 //     specific prior written permission.
     15 //
     16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
     17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
     20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
     23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     26 
     27 #ifndef VIXL_DISASM_AARCH32_H_
     28 #define VIXL_DISASM_AARCH32_H_
     29 
     30 extern "C" {
     31 #include <stdint.h>
     32 }
     33 
     34 #include <iomanip>
     35 
     36 #include "aarch32/constants-aarch32.h"
     37 #include "aarch32/operands-aarch32.h"
     38 
     39 namespace vixl {
     40 namespace aarch32 {
     41 
     42 class ITBlock {
     43   Condition first_condition_;
     44   Condition condition_;
     45   uint16_t it_mask_;
     46 
     47  public:
     48   ITBlock() : first_condition_(al), condition_(al), it_mask_(0) {}
     49   void Advance() {
     50     condition_ = Condition((condition_.GetCondition() & 0xe) | (it_mask_ >> 3));
     51     it_mask_ = (it_mask_ << 1) & 0xf;
     52   }
     53   bool InITBlock() const { return it_mask_ != 0; }
     54   bool OutsideITBlock() const { return !InITBlock(); }
     55   bool LastInITBlock() const { return it_mask_ == 0x8; }
     56   bool OutsideITBlockOrLast() const {
     57     return OutsideITBlock() || LastInITBlock();
     58   }
     59   void Set(Condition first_condition, uint16_t mask) {
     60     condition_ = first_condition_ = first_condition;
     61     it_mask_ = mask;
     62   }
     63   Condition GetFirstCondition() const { return first_condition_; }
     64   Condition GetCurrentCondition() const { return condition_; }
     65 };
     66 
     67 class Disassembler {
     68  public:
     69   enum LocationType {
     70     kAnyLocation,
     71     kCodeLocation,
     72     kDataLocation,
     73     kCoprocLocation,
     74     kLoadByteLocation,
     75     kLoadHalfWordLocation,
     76     kLoadWordLocation,
     77     kLoadDoubleWordLocation,
     78     kLoadSignedByteLocation,
     79     kLoadSignedHalfWordLocation,
     80     kLoadSinglePrecisionLocation,
     81     kLoadDoublePrecisionLocation,
     82     kStoreByteLocation,
     83     kStoreHalfWordLocation,
     84     kStoreWordLocation,
     85     kStoreDoubleWordLocation,
     86     kStoreSinglePrecisionLocation,
     87     kStoreDoublePrecisionLocation,
     88     kVld1Location,
     89     kVld2Location,
     90     kVld3Location,
     91     kVld4Location,
     92     kVst1Location,
     93     kVst2Location,
     94     kVst3Location,
     95     kVst4Location
     96   };
     97 
     98   class ConditionPrinter {
     99     const ITBlock& it_block_;
    100     Condition cond_;
    101 
    102    public:
    103     ConditionPrinter(const ITBlock& it_block, Condition cond)
    104         : it_block_(it_block), cond_(cond) {}
    105     const ITBlock& GetITBlock() const { return it_block_; }
    106     Condition GetCond() const { return cond_; }
    107     friend std::ostream& operator<<(std::ostream& os, ConditionPrinter cond) {
    108       if (cond.it_block_.InITBlock() && cond.cond_.Is(al) &&
    109           !cond.cond_.IsNone()) {
    110         return os << "al";
    111       }
    112       return os << cond.cond_;
    113     }
    114   };
    115 
    116   class ImmediatePrinter {
    117     uint32_t imm_;
    118 
    119    public:
    120     explicit ImmediatePrinter(uint32_t imm) : imm_(imm) {}
    121     uint32_t GetImm() const { return imm_; }
    122     friend std::ostream& operator<<(std::ostream& os, ImmediatePrinter imm) {
    123       return os << "#" << imm.GetImm();
    124     }
    125   };
    126 
    127   class SignedImmediatePrinter {
    128     int32_t imm_;
    129 
    130    public:
    131     explicit SignedImmediatePrinter(int32_t imm) : imm_(imm) {}
    132     int32_t GetImm() const { return imm_; }
    133     friend std::ostream& operator<<(std::ostream& os,
    134                                     SignedImmediatePrinter imm) {
    135       return os << "#" << imm.GetImm();
    136     }
    137   };
    138 
    139   class RawImmediatePrinter {
    140     uint32_t imm_;
    141 
    142    public:
    143     explicit RawImmediatePrinter(uint32_t imm) : imm_(imm) {}
    144     uint32_t GetImm() const { return imm_; }
    145     friend std::ostream& operator<<(std::ostream& os, RawImmediatePrinter imm) {
    146       return os << imm.GetImm();
    147     }
    148   };
    149 
    150   class DtPrinter {
    151     DataType dt_;
    152     DataType default_dt_;
    153 
    154    public:
    155     DtPrinter(DataType dt, DataType default_dt)
    156         : dt_(dt), default_dt_(default_dt) {}
    157     DataType GetDt() const { return dt_; }
    158     DataType GetDefaultDt() const { return default_dt_; }
    159     friend std::ostream& operator<<(std::ostream& os, DtPrinter dt) {
    160       if (dt.dt_.Is(dt.default_dt_)) return os;
    161       return os << dt.dt_;
    162     }
    163   };
    164 
    165   class IndexedRegisterPrinter {
    166     DRegister reg_;
    167     uint32_t index_;
    168 
    169    public:
    170     IndexedRegisterPrinter(DRegister reg, uint32_t index)
    171         : reg_(reg), index_(index) {}
    172     DRegister GetReg() const { return reg_; }
    173     uint32_t GetIndex() const { return index_; }
    174     friend std::ostream& operator<<(std::ostream& os,
    175                                     IndexedRegisterPrinter reg) {
    176       return os << reg.GetReg() << "[" << reg.GetIndex() << "]";
    177     }
    178   };
    179 
    180   // TODO: Merge this class with PrintLabel below. This Location class
    181   // represents a PC-relative offset, not an address.
    182   class Location {
    183    public:
    184     typedef int32_t Offset;
    185 
    186     Location(Offset immediate, Offset pc_offset)
    187         : immediate_(immediate), pc_offset_(pc_offset) {}
    188     Offset GetImmediate() const { return immediate_; }
    189     Offset GetPCOffset() const { return pc_offset_; }
    190 
    191    private:
    192     Offset immediate_;
    193     Offset pc_offset_;
    194   };
    195 
    196   class PrintLabel {
    197     LocationType location_type_;
    198     Location::Offset immediate_;
    199     Location::Offset location_;
    200 
    201    public:
    202     PrintLabel(LocationType location_type,
    203                Location* offset,
    204                Location::Offset position)
    205         : location_type_(location_type),
    206           immediate_(offset->GetImmediate()),
    207           location_(offset->GetPCOffset() + offset->GetImmediate() + position) {
    208     }
    209 
    210     LocationType GetLocationType() const { return location_type_; }
    211     Location::Offset GetLocation() const { return location_; }
    212     Location::Offset GetImmediate() const { return immediate_; }
    213 
    214     friend inline std::ostream& operator<<(std::ostream& os,
    215                                            const PrintLabel& label) {
    216       os << "0x" << std::hex << std::setw(8) << std::setfill('0')
    217          << label.GetLocation() << std::dec;
    218       return os;
    219     }
    220   };
    221 
    222 
    223   class PrintMemOperand {
    224     LocationType location_type_;
    225     const MemOperand& operand_;
    226 
    227    public:
    228     PrintMemOperand(LocationType location_type, const MemOperand& operand)
    229         : location_type_(location_type), operand_(operand) {}
    230     LocationType GetLocationType() const { return location_type_; }
    231     const MemOperand& GetOperand() const { return operand_; }
    232   };
    233 
    234   class PrintAlignedMemOperand {
    235     LocationType location_type_;
    236     const AlignedMemOperand& operand_;
    237 
    238    public:
    239     PrintAlignedMemOperand(LocationType location_type,
    240                            const AlignedMemOperand& operand)
    241         : location_type_(location_type), operand_(operand) {}
    242     LocationType GetLocationType() const { return location_type_; }
    243     const AlignedMemOperand& GetOperand() const { return operand_; }
    244   };
    245 
    246   class DisassemblerStream {
    247     std::ostream& os_;
    248     InstructionType current_instruction_type_;
    249     InstructionAttribute current_instruction_attributes_;
    250 
    251    public:
    252     explicit DisassemblerStream(std::ostream& os)  // NOLINT(runtime/references)
    253         : os_(os),
    254           current_instruction_type_(kUndefInstructionType),
    255           current_instruction_attributes_(kNoAttribute) {}
    256     virtual ~DisassemblerStream() {}
    257     std::ostream& os() const { return os_; }
    258     void SetCurrentInstruction(
    259         InstructionType current_instruction_type,
    260         InstructionAttribute current_instruction_attributes) {
    261       current_instruction_type_ = current_instruction_type;
    262       current_instruction_attributes_ = current_instruction_attributes;
    263     }
    264     InstructionType GetCurrentInstructionType() const {
    265       return current_instruction_type_;
    266     }
    267     InstructionAttribute GetCurrentInstructionAttributes() const {
    268       return current_instruction_attributes_;
    269     }
    270     bool Has(InstructionAttribute attributes) const {
    271       return (current_instruction_attributes_ & attributes) == attributes;
    272     }
    273     template <typename T>
    274     DisassemblerStream& operator<<(T value) {
    275       os_ << value;
    276       return *this;
    277     }
    278     virtual DisassemblerStream& operator<<(const char* string) {
    279       os_ << string;
    280       return *this;
    281     }
    282     virtual DisassemblerStream& operator<<(const ConditionPrinter& cond) {
    283       os_ << cond;
    284       return *this;
    285     }
    286     virtual DisassemblerStream& operator<<(Condition cond) {
    287       os_ << cond;
    288       return *this;
    289     }
    290     virtual DisassemblerStream& operator<<(const EncodingSize& size) {
    291       os_ << size;
    292       return *this;
    293     }
    294     virtual DisassemblerStream& operator<<(const ImmediatePrinter& imm) {
    295       os_ << imm;
    296       return *this;
    297     }
    298     virtual DisassemblerStream& operator<<(const SignedImmediatePrinter& imm) {
    299       os_ << imm;
    300       return *this;
    301     }
    302     virtual DisassemblerStream& operator<<(const RawImmediatePrinter& imm) {
    303       os_ << imm;
    304       return *this;
    305     }
    306     virtual DisassemblerStream& operator<<(const DtPrinter& dt) {
    307       os_ << dt;
    308       return *this;
    309     }
    310     virtual DisassemblerStream& operator<<(const DataType& type) {
    311       os_ << type;
    312       return *this;
    313     }
    314     virtual DisassemblerStream& operator<<(Shift shift) {
    315       os_ << shift;
    316       return *this;
    317     }
    318     virtual DisassemblerStream& operator<<(Sign sign) {
    319       os_ << sign;
    320       return *this;
    321     }
    322     virtual DisassemblerStream& operator<<(Alignment alignment) {
    323       os_ << alignment;
    324       return *this;
    325     }
    326     virtual DisassemblerStream& operator<<(const PrintLabel& label) {
    327       os_ << label;
    328       return *this;
    329     }
    330     virtual DisassemblerStream& operator<<(const WriteBack& write_back) {
    331       os_ << write_back;
    332       return *this;
    333     }
    334     virtual DisassemblerStream& operator<<(const NeonImmediate& immediate) {
    335       os_ << immediate;
    336       return *this;
    337     }
    338     virtual DisassemblerStream& operator<<(Register reg) {
    339       os_ << reg;
    340       return *this;
    341     }
    342     virtual DisassemblerStream& operator<<(SRegister reg) {
    343       os_ << reg;
    344       return *this;
    345     }
    346     virtual DisassemblerStream& operator<<(DRegister reg) {
    347       os_ << reg;
    348       return *this;
    349     }
    350     virtual DisassemblerStream& operator<<(QRegister reg) {
    351       os_ << reg;
    352       return *this;
    353     }
    354     virtual DisassemblerStream& operator<<(const RegisterOrAPSR_nzcv reg) {
    355       os_ << reg;
    356       return *this;
    357     }
    358     virtual DisassemblerStream& operator<<(SpecialRegister reg) {
    359       os_ << reg;
    360       return *this;
    361     }
    362     virtual DisassemblerStream& operator<<(MaskedSpecialRegister reg) {
    363       os_ << reg;
    364       return *this;
    365     }
    366     virtual DisassemblerStream& operator<<(SpecialFPRegister reg) {
    367       os_ << reg;
    368       return *this;
    369     }
    370     virtual DisassemblerStream& operator<<(BankedRegister reg) {
    371       os_ << reg;
    372       return *this;
    373     }
    374     virtual DisassemblerStream& operator<<(const RegisterList& list) {
    375       os_ << list;
    376       return *this;
    377     }
    378     virtual DisassemblerStream& operator<<(const SRegisterList& list) {
    379       os_ << list;
    380       return *this;
    381     }
    382     virtual DisassemblerStream& operator<<(const DRegisterList& list) {
    383       os_ << list;
    384       return *this;
    385     }
    386     virtual DisassemblerStream& operator<<(const NeonRegisterList& list) {
    387       os_ << list;
    388       return *this;
    389     }
    390     virtual DisassemblerStream& operator<<(const DRegisterLane& reg) {
    391       os_ << reg;
    392       return *this;
    393     }
    394     virtual DisassemblerStream& operator<<(const IndexedRegisterPrinter& reg) {
    395       os_ << reg;
    396       return *this;
    397     }
    398     virtual DisassemblerStream& operator<<(Coprocessor coproc) {
    399       os_ << coproc;
    400       return *this;
    401     }
    402     virtual DisassemblerStream& operator<<(CRegister reg) {
    403       os_ << reg;
    404       return *this;
    405     }
    406     virtual DisassemblerStream& operator<<(Endianness endian_specifier) {
    407       os_ << endian_specifier;
    408       return *this;
    409     }
    410     virtual DisassemblerStream& operator<<(MemoryBarrier option) {
    411       os_ << option;
    412       return *this;
    413     }
    414     virtual DisassemblerStream& operator<<(InterruptFlags iflags) {
    415       os_ << iflags;
    416       return *this;
    417     }
    418     virtual DisassemblerStream& operator<<(const Operand& operand) {
    419       if (operand.IsImmediate()) {
    420         if (Has(kBitwise)) {
    421           return *this << "#0x" << std::hex << operand.GetImmediate()
    422                        << std::dec;
    423         }
    424         return *this << "#" << operand.GetImmediate();
    425       }
    426       if (operand.IsImmediateShiftedRegister()) {
    427         if ((operand.GetShift().IsLSL() || operand.GetShift().IsROR()) &&
    428             (operand.GetShiftAmount() == 0)) {
    429           return *this << operand.GetBaseRegister();
    430         }
    431         if (operand.GetShift().IsRRX()) {
    432           return *this << operand.GetBaseRegister() << ", rrx";
    433         }
    434         return *this << operand.GetBaseRegister() << ", " << operand.GetShift()
    435                      << " #" << operand.GetShiftAmount();
    436       }
    437       if (operand.IsRegisterShiftedRegister()) {
    438         return *this << operand.GetBaseRegister() << ", " << operand.GetShift()
    439                      << " " << operand.GetShiftRegister();
    440       }
    441       VIXL_UNREACHABLE();
    442       return *this;
    443     }
    444     virtual DisassemblerStream& operator<<(const SOperand& operand) {
    445       if (operand.IsImmediate()) {
    446         return *this << operand.GetNeonImmediate();
    447       }
    448       return *this << operand.GetRegister();
    449     }
    450     virtual DisassemblerStream& operator<<(const DOperand& operand) {
    451       if (operand.IsImmediate()) {
    452         return *this << operand.GetNeonImmediate();
    453       }
    454       return *this << operand.GetRegister();
    455     }
    456     virtual DisassemblerStream& operator<<(const QOperand& operand) {
    457       if (operand.IsImmediate()) {
    458         return *this << operand.GetNeonImmediate();
    459       }
    460       return *this << operand.GetRegister();
    461     }
    462     virtual DisassemblerStream& operator<<(const MemOperand& operand) {
    463       *this << "[" << operand.GetBaseRegister();
    464       if (operand.GetAddrMode() == PostIndex) {
    465         *this << "]";
    466         if (operand.IsRegisterOnly()) return *this << "!";
    467       }
    468       if (operand.IsImmediate()) {
    469         if ((operand.GetOffsetImmediate() != 0) ||
    470             operand.GetSign().IsMinus() ||
    471             ((operand.GetAddrMode() != Offset) && !operand.IsRegisterOnly())) {
    472           if (operand.GetOffsetImmediate() == 0) {
    473             *this << ", #" << operand.GetSign() << operand.GetOffsetImmediate();
    474           } else {
    475             *this << ", #" << operand.GetOffsetImmediate();
    476           }
    477         }
    478       } else if (operand.IsPlainRegister()) {
    479         *this << ", " << operand.GetSign() << operand.GetOffsetRegister();
    480       } else if (operand.IsShiftedRegister()) {
    481         *this << ", " << operand.GetSign() << operand.GetOffsetRegister()
    482               << ImmediateShiftOperand(operand.GetShift(),
    483                                        operand.GetShiftAmount());
    484       } else {
    485         VIXL_UNREACHABLE();
    486         return *this;
    487       }
    488       if (operand.GetAddrMode() == Offset) {
    489         *this << "]";
    490       } else if (operand.GetAddrMode() == PreIndex) {
    491         *this << "]!";
    492       }
    493       return *this;
    494     }
    495     virtual DisassemblerStream& operator<<(const PrintMemOperand& operand) {
    496       return *this << operand.GetOperand();
    497     }
    498     virtual DisassemblerStream& operator<<(const AlignedMemOperand& operand) {
    499       *this << "[" << operand.GetBaseRegister() << operand.GetAlignment()
    500             << "]";
    501       if (operand.GetAddrMode() == PostIndex) {
    502         if (operand.IsPlainRegister()) {
    503           *this << ", " << operand.GetOffsetRegister();
    504         } else {
    505           *this << "!";
    506         }
    507       }
    508       return *this;
    509     }
    510     virtual DisassemblerStream& operator<<(
    511         const PrintAlignedMemOperand& operand) {
    512       return *this << operand.GetOperand();
    513     }
    514   };
    515 
    516  private:
    517   class ITBlockScope {
    518     ITBlock* const it_block_;
    519     bool inside_;
    520 
    521    public:
    522     explicit ITBlockScope(ITBlock* it_block)
    523         : it_block_(it_block), inside_(it_block->InITBlock()) {}
    524     ~ITBlockScope() {
    525       if (inside_) it_block_->Advance();
    526     }
    527   };
    528 
    529   ITBlock it_block_;
    530   DisassemblerStream* os_;
    531   bool owns_os_;
    532   uint32_t code_address_;
    533   // True if the disassembler always output instructions with all the
    534   // registers (even if two registers are identical and only one could be
    535   // output).
    536   bool use_short_hand_form_;
    537 
    538  public:
    539   explicit Disassembler(std::ostream& os,  // NOLINT(runtime/references)
    540                         uint32_t code_address = 0)
    541       : os_(new DisassemblerStream(os)),
    542         owns_os_(true),
    543         code_address_(code_address),
    544         use_short_hand_form_(true) {}
    545   explicit Disassembler(DisassemblerStream* os, uint32_t code_address = 0)
    546       : os_(os),
    547         owns_os_(false),
    548         code_address_(code_address),
    549         use_short_hand_form_(true) {}
    550   virtual ~Disassembler() {
    551     if (owns_os_) {
    552       delete os_;
    553     }
    554   }
    555   DisassemblerStream& os() const { return *os_; }
    556   void SetIT(Condition first_condition, uint16_t it_mask) {
    557     it_block_.Set(first_condition, it_mask);
    558   }
    559   const ITBlock& GetITBlock() const { return it_block_; }
    560   bool InITBlock() const { return it_block_.InITBlock(); }
    561   bool OutsideITBlock() const { return it_block_.OutsideITBlock(); }
    562   bool OutsideITBlockOrLast() const { return it_block_.OutsideITBlockOrLast(); }
    563   void CheckNotIT() const { VIXL_ASSERT(it_block_.OutsideITBlock()); }
    564   // Return the current condition depending on the IT state for T32.
    565   Condition CurrentCond() const {
    566     if (it_block_.OutsideITBlock()) return al;
    567     return it_block_.GetCurrentCondition();
    568   }
    569   bool UseShortHandForm() const { return use_short_hand_form_; }
    570   void SetUseShortHandForm(bool use_short_hand_form) {
    571     use_short_hand_form_ = use_short_hand_form;
    572   }
    573 
    574   virtual void UnallocatedT32(uint32_t instruction) {
    575     if (T32Size(instruction) == 2) {
    576       os() << "unallocated " << std::hex << std::setw(4) << std::setfill('0')
    577            << (instruction >> 16) << std::dec;
    578     } else {
    579       os() << "unallocated " << std::hex << std::setw(8) << std::setfill('0')
    580            << instruction << std::dec;
    581     }
    582   }
    583   virtual void UnallocatedA32(uint32_t instruction) {
    584     os() << "unallocated " << std::hex << std::setw(8) << std::setfill('0')
    585          << instruction << std::dec;
    586   }
    587   virtual void UnimplementedT32_16(const char* name, uint32_t instruction) {
    588     os() << "unimplemented " << name << " T32:" << std::hex << std::setw(4)
    589          << std::setfill('0') << (instruction >> 16) << std::dec;
    590   }
    591   virtual void UnimplementedT32_32(const char* name, uint32_t instruction) {
    592     os() << "unimplemented " << name << " T32:" << std::hex << std::setw(8)
    593          << std::setfill('0') << instruction << std::dec;
    594   }
    595   virtual void UnimplementedA32(const char* name, uint32_t instruction) {
    596     os() << "unimplemented " << name << " ARM:" << std::hex << std::setw(8)
    597          << std::setfill('0') << instruction << std::dec;
    598   }
    599   virtual void Unpredictable() { os() << " ; unpredictable"; }
    600   virtual void UnpredictableT32(uint32_t /*instr*/) { return Unpredictable(); }
    601   virtual void UnpredictableA32(uint32_t /*instr*/) { return Unpredictable(); }
    602 
    603   static bool Is16BitEncoding(uint32_t instr) { return instr < 0xe8000000; }
    604   uint32_t GetCodeAddress() const { return code_address_; }
    605   void SetCodeAddress(uint32_t code_address) { code_address_ = code_address; }
    606 
    607   // Start of generated code.
    608 
    609   void adc(Condition cond,
    610            EncodingSize size,
    611            Register rd,
    612            Register rn,
    613            const Operand& operand);
    614 
    615   void adcs(Condition cond,
    616             EncodingSize size,
    617             Register rd,
    618             Register rn,
    619             const Operand& operand);
    620 
    621   void add(Condition cond,
    622            EncodingSize size,
    623            Register rd,
    624            Register rn,
    625            const Operand& operand);
    626 
    627   void add(Condition cond, Register rd, const Operand& operand);
    628 
    629   void adds(Condition cond,
    630             EncodingSize size,
    631             Register rd,
    632             Register rn,
    633             const Operand& operand);
    634 
    635   void adds(Register rd, const Operand& operand);
    636 
    637   void addw(Condition cond, Register rd, Register rn, const Operand& operand);
    638 
    639   void adr(Condition cond, EncodingSize size, Register rd, Location* location);
    640 
    641   void and_(Condition cond,
    642             EncodingSize size,
    643             Register rd,
    644             Register rn,
    645             const Operand& operand);
    646 
    647   void ands(Condition cond,
    648             EncodingSize size,
    649             Register rd,
    650             Register rn,
    651             const Operand& operand);
    652 
    653   void asr(Condition cond,
    654            EncodingSize size,
    655            Register rd,
    656            Register rm,
    657            const Operand& operand);
    658 
    659   void asrs(Condition cond,
    660             EncodingSize size,
    661             Register rd,
    662             Register rm,
    663             const Operand& operand);
    664 
    665   void b(Condition cond, EncodingSize size, Location* location);
    666 
    667   void bfc(Condition cond, Register rd, uint32_t lsb, uint32_t width);
    668 
    669   void bfi(
    670       Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width);
    671 
    672   void bic(Condition cond,
    673            EncodingSize size,
    674            Register rd,
    675            Register rn,
    676            const Operand& operand);
    677 
    678   void bics(Condition cond,
    679             EncodingSize size,
    680             Register rd,
    681             Register rn,
    682             const Operand& operand);
    683 
    684   void bkpt(Condition cond, uint32_t imm);
    685 
    686   void bl(Condition cond, Location* location);
    687 
    688   void blx(Condition cond, Location* location);
    689 
    690   void blx(Condition cond, Register rm);
    691 
    692   void bx(Condition cond, Register rm);
    693 
    694   void bxj(Condition cond, Register rm);
    695 
    696   void cbnz(Register rn, Location* location);
    697 
    698   void cbz(Register rn, Location* location);
    699 
    700   void clrex(Condition cond);
    701 
    702   void clz(Condition cond, Register rd, Register rm);
    703 
    704   void cmn(Condition cond,
    705            EncodingSize size,
    706            Register rn,
    707            const Operand& operand);
    708 
    709   void cmp(Condition cond,
    710            EncodingSize size,
    711            Register rn,
    712            const Operand& operand);
    713 
    714   void crc32b(Condition cond, Register rd, Register rn, Register rm);
    715 
    716   void crc32cb(Condition cond, Register rd, Register rn, Register rm);
    717 
    718   void crc32ch(Condition cond, Register rd, Register rn, Register rm);
    719 
    720   void crc32cw(Condition cond, Register rd, Register rn, Register rm);
    721 
    722   void crc32h(Condition cond, Register rd, Register rn, Register rm);
    723 
    724   void crc32w(Condition cond, Register rd, Register rn, Register rm);
    725 
    726   void dmb(Condition cond, MemoryBarrier option);
    727 
    728   void dsb(Condition cond, MemoryBarrier option);
    729 
    730   void eor(Condition cond,
    731            EncodingSize size,
    732            Register rd,
    733            Register rn,
    734            const Operand& operand);
    735 
    736   void eors(Condition cond,
    737             EncodingSize size,
    738             Register rd,
    739             Register rn,
    740             const Operand& operand);
    741 
    742   void fldmdbx(Condition cond,
    743                Register rn,
    744                WriteBack write_back,
    745                DRegisterList dreglist);
    746 
    747   void fldmiax(Condition cond,
    748                Register rn,
    749                WriteBack write_back,
    750                DRegisterList dreglist);
    751 
    752   void fstmdbx(Condition cond,
    753                Register rn,
    754                WriteBack write_back,
    755                DRegisterList dreglist);
    756 
    757   void fstmiax(Condition cond,
    758                Register rn,
    759                WriteBack write_back,
    760                DRegisterList dreglist);
    761 
    762   void hlt(Condition cond, uint32_t imm);
    763 
    764   void hvc(Condition cond, uint32_t imm);
    765 
    766   void isb(Condition cond, MemoryBarrier option);
    767 
    768   void it(Condition cond, uint16_t mask);
    769 
    770   void lda(Condition cond, Register rt, const MemOperand& operand);
    771 
    772   void ldab(Condition cond, Register rt, const MemOperand& operand);
    773 
    774   void ldaex(Condition cond, Register rt, const MemOperand& operand);
    775 
    776   void ldaexb(Condition cond, Register rt, const MemOperand& operand);
    777 
    778   void ldaexd(Condition cond,
    779               Register rt,
    780               Register rt2,
    781               const MemOperand& operand);
    782 
    783   void ldaexh(Condition cond, Register rt, const MemOperand& operand);
    784 
    785   void ldah(Condition cond, Register rt, const MemOperand& operand);
    786 
    787   void ldm(Condition cond,
    788            EncodingSize size,
    789            Register rn,
    790            WriteBack write_back,
    791            RegisterList registers);
    792 
    793   void ldmda(Condition cond,
    794              Register rn,
    795              WriteBack write_back,
    796              RegisterList registers);
    797 
    798   void ldmdb(Condition cond,
    799              Register rn,
    800              WriteBack write_back,
    801              RegisterList registers);
    802 
    803   void ldmea(Condition cond,
    804              Register rn,
    805              WriteBack write_back,
    806              RegisterList registers);
    807 
    808   void ldmed(Condition cond,
    809              Register rn,
    810              WriteBack write_back,
    811              RegisterList registers);
    812 
    813   void ldmfa(Condition cond,
    814              Register rn,
    815              WriteBack write_back,
    816              RegisterList registers);
    817 
    818   void ldmfd(Condition cond,
    819              EncodingSize size,
    820              Register rn,
    821              WriteBack write_back,
    822              RegisterList registers);
    823 
    824   void ldmib(Condition cond,
    825              Register rn,
    826              WriteBack write_back,
    827              RegisterList registers);
    828 
    829   void ldr(Condition cond,
    830            EncodingSize size,
    831            Register rt,
    832            const MemOperand& operand);
    833 
    834   void ldr(Condition cond, EncodingSize size, Register rt, Location* location);
    835 
    836   void ldrb(Condition cond,
    837             EncodingSize size,
    838             Register rt,
    839             const MemOperand& operand);
    840 
    841   void ldrb(Condition cond, Register rt, Location* location);
    842 
    843   void ldrd(Condition cond,
    844             Register rt,
    845             Register rt2,
    846             const MemOperand& operand);
    847 
    848   void ldrd(Condition cond, Register rt, Register rt2, Location* location);
    849 
    850   void ldrex(Condition cond, Register rt, const MemOperand& operand);
    851 
    852   void ldrexb(Condition cond, Register rt, const MemOperand& operand);
    853 
    854   void ldrexd(Condition cond,
    855               Register rt,
    856               Register rt2,
    857               const MemOperand& operand);
    858 
    859   void ldrexh(Condition cond, Register rt, const MemOperand& operand);
    860 
    861   void ldrh(Condition cond,
    862             EncodingSize size,
    863             Register rt,
    864             const MemOperand& operand);
    865 
    866   void ldrh(Condition cond, Register rt, Location* location);
    867 
    868   void ldrsb(Condition cond,
    869              EncodingSize size,
    870              Register rt,
    871              const MemOperand& operand);
    872 
    873   void ldrsb(Condition cond, Register rt, Location* location);
    874 
    875   void ldrsh(Condition cond,
    876              EncodingSize size,
    877              Register rt,
    878              const MemOperand& operand);
    879 
    880   void ldrsh(Condition cond, Register rt, Location* location);
    881 
    882   void lsl(Condition cond,
    883            EncodingSize size,
    884            Register rd,
    885            Register rm,
    886            const Operand& operand);
    887 
    888   void lsls(Condition cond,
    889             EncodingSize size,
    890             Register rd,
    891             Register rm,
    892             const Operand& operand);
    893 
    894   void lsr(Condition cond,
    895            EncodingSize size,
    896            Register rd,
    897            Register rm,
    898            const Operand& operand);
    899 
    900   void lsrs(Condition cond,
    901             EncodingSize size,
    902             Register rd,
    903             Register rm,
    904             const Operand& operand);
    905 
    906   void mla(Condition cond, Register rd, Register rn, Register rm, Register ra);
    907 
    908   void mlas(Condition cond, Register rd, Register rn, Register rm, Register ra);
    909 
    910   void mls(Condition cond, Register rd, Register rn, Register rm, Register ra);
    911 
    912   void mov(Condition cond,
    913            EncodingSize size,
    914            Register rd,
    915            const Operand& operand);
    916 
    917   void movs(Condition cond,
    918             EncodingSize size,
    919             Register rd,
    920             const Operand& operand);
    921 
    922   void movt(Condition cond, Register rd, const Operand& operand);
    923 
    924   void movw(Condition cond, Register rd, const Operand& operand);
    925 
    926   void mrs(Condition cond, Register rd, SpecialRegister spec_reg);
    927 
    928   void msr(Condition cond,
    929            MaskedSpecialRegister spec_reg,
    930            const Operand& operand);
    931 
    932   void mul(
    933       Condition cond, EncodingSize size, Register rd, Register rn, Register rm);
    934 
    935   void muls(Condition cond, Register rd, Register rn, Register rm);
    936 
    937   void mvn(Condition cond,
    938            EncodingSize size,
    939            Register rd,
    940            const Operand& operand);
    941 
    942   void mvns(Condition cond,
    943             EncodingSize size,
    944             Register rd,
    945             const Operand& operand);
    946 
    947   void nop(Condition cond, EncodingSize size);
    948 
    949   void orn(Condition cond, Register rd, Register rn, const Operand& operand);
    950 
    951   void orns(Condition cond, Register rd, Register rn, const Operand& operand);
    952 
    953   void orr(Condition cond,
    954            EncodingSize size,
    955            Register rd,
    956            Register rn,
    957            const Operand& operand);
    958 
    959   void orrs(Condition cond,
    960             EncodingSize size,
    961             Register rd,
    962             Register rn,
    963             const Operand& operand);
    964 
    965   void pkhbt(Condition cond, Register rd, Register rn, const Operand& operand);
    966 
    967   void pkhtb(Condition cond, Register rd, Register rn, const Operand& operand);
    968 
    969   void pld(Condition cond, Location* location);
    970 
    971   void pld(Condition cond, const MemOperand& operand);
    972 
    973   void pldw(Condition cond, const MemOperand& operand);
    974 
    975   void pli(Condition cond, const MemOperand& operand);
    976 
    977   void pli(Condition cond, Location* location);
    978 
    979   void pop(Condition cond, EncodingSize size, RegisterList registers);
    980 
    981   void pop(Condition cond, EncodingSize size, Register rt);
    982 
    983   void push(Condition cond, EncodingSize size, RegisterList registers);
    984 
    985   void push(Condition cond, EncodingSize size, Register rt);
    986 
    987   void qadd(Condition cond, Register rd, Register rm, Register rn);
    988 
    989   void qadd16(Condition cond, Register rd, Register rn, Register rm);
    990 
    991   void qadd8(Condition cond, Register rd, Register rn, Register rm);
    992 
    993   void qasx(Condition cond, Register rd, Register rn, Register rm);
    994 
    995   void qdadd(Condition cond, Register rd, Register rm, Register rn);
    996 
    997   void qdsub(Condition cond, Register rd, Register rm, Register rn);
    998 
    999   void qsax(Condition cond, Register rd, Register rn, Register rm);
   1000 
   1001   void qsub(Condition cond, Register rd, Register rm, Register rn);
   1002 
   1003   void qsub16(Condition cond, Register rd, Register rn, Register rm);
   1004 
   1005   void qsub8(Condition cond, Register rd, Register rn, Register rm);
   1006 
   1007   void rbit(Condition cond, Register rd, Register rm);
   1008 
   1009   void rev(Condition cond, EncodingSize size, Register rd, Register rm);
   1010 
   1011   void rev16(Condition cond, EncodingSize size, Register rd, Register rm);
   1012 
   1013   void revsh(Condition cond, EncodingSize size, Register rd, Register rm);
   1014 
   1015   void ror(Condition cond,
   1016            EncodingSize size,
   1017            Register rd,
   1018            Register rm,
   1019            const Operand& operand);
   1020 
   1021   void rors(Condition cond,
   1022             EncodingSize size,
   1023             Register rd,
   1024             Register rm,
   1025             const Operand& operand);
   1026 
   1027   void rrx(Condition cond, Register rd, Register rm);
   1028 
   1029   void rrxs(Condition cond, Register rd, Register rm);
   1030 
   1031   void rsb(Condition cond,
   1032            EncodingSize size,
   1033            Register rd,
   1034            Register rn,
   1035            const Operand& operand);
   1036 
   1037   void rsbs(Condition cond,
   1038             EncodingSize size,
   1039             Register rd,
   1040             Register rn,
   1041             const Operand& operand);
   1042 
   1043   void rsc(Condition cond, Register rd, Register rn, const Operand& operand);
   1044 
   1045   void rscs(Condition cond, Register rd, Register rn, const Operand& operand);
   1046 
   1047   void sadd16(Condition cond, Register rd, Register rn, Register rm);
   1048 
   1049   void sadd8(Condition cond, Register rd, Register rn, Register rm);
   1050 
   1051   void sasx(Condition cond, Register rd, Register rn, Register rm);
   1052 
   1053   void sbc(Condition cond,
   1054            EncodingSize size,
   1055            Register rd,
   1056            Register rn,
   1057            const Operand& operand);
   1058 
   1059   void sbcs(Condition cond,
   1060             EncodingSize size,
   1061             Register rd,
   1062             Register rn,
   1063             const Operand& operand);
   1064 
   1065   void sbfx(
   1066       Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width);
   1067 
   1068   void sdiv(Condition cond, Register rd, Register rn, Register rm);
   1069 
   1070   void sel(Condition cond, Register rd, Register rn, Register rm);
   1071 
   1072   void shadd16(Condition cond, Register rd, Register rn, Register rm);
   1073 
   1074   void shadd8(Condition cond, Register rd, Register rn, Register rm);
   1075 
   1076   void shasx(Condition cond, Register rd, Register rn, Register rm);
   1077 
   1078   void shsax(Condition cond, Register rd, Register rn, Register rm);
   1079 
   1080   void shsub16(Condition cond, Register rd, Register rn, Register rm);
   1081 
   1082   void shsub8(Condition cond, Register rd, Register rn, Register rm);
   1083 
   1084   void smlabb(
   1085       Condition cond, Register rd, Register rn, Register rm, Register ra);
   1086 
   1087   void smlabt(
   1088       Condition cond, Register rd, Register rn, Register rm, Register ra);
   1089 
   1090   void smlad(
   1091       Condition cond, Register rd, Register rn, Register rm, Register ra);
   1092 
   1093   void smladx(
   1094       Condition cond, Register rd, Register rn, Register rm, Register ra);
   1095 
   1096   void smlal(
   1097       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
   1098 
   1099   void smlalbb(
   1100       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
   1101 
   1102   void smlalbt(
   1103       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
   1104 
   1105   void smlald(
   1106       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
   1107 
   1108   void smlaldx(
   1109       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
   1110 
   1111   void smlals(
   1112       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
   1113 
   1114   void smlaltb(
   1115       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
   1116 
   1117   void smlaltt(
   1118       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
   1119 
   1120   void smlatb(
   1121       Condition cond, Register rd, Register rn, Register rm, Register ra);
   1122 
   1123   void smlatt(
   1124       Condition cond, Register rd, Register rn, Register rm, Register ra);
   1125 
   1126   void smlawb(
   1127       Condition cond, Register rd, Register rn, Register rm, Register ra);
   1128 
   1129   void smlawt(
   1130       Condition cond, Register rd, Register rn, Register rm, Register ra);
   1131 
   1132   void smlsd(
   1133       Condition cond, Register rd, Register rn, Register rm, Register ra);
   1134 
   1135   void smlsdx(
   1136       Condition cond, Register rd, Register rn, Register rm, Register ra);
   1137 
   1138   void smlsld(
   1139       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
   1140 
   1141   void smlsldx(
   1142       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
   1143 
   1144   void smmla(
   1145       Condition cond, Register rd, Register rn, Register rm, Register ra);
   1146 
   1147   void smmlar(
   1148       Condition cond, Register rd, Register rn, Register rm, Register ra);
   1149 
   1150   void smmls(
   1151       Condition cond, Register rd, Register rn, Register rm, Register ra);
   1152 
   1153   void smmlsr(
   1154       Condition cond, Register rd, Register rn, Register rm, Register ra);
   1155 
   1156   void smmul(Condition cond, Register rd, Register rn, Register rm);
   1157 
   1158   void smmulr(Condition cond, Register rd, Register rn, Register rm);
   1159 
   1160   void smuad(Condition cond, Register rd, Register rn, Register rm);
   1161 
   1162   void smuadx(Condition cond, Register rd, Register rn, Register rm);
   1163 
   1164   void smulbb(Condition cond, Register rd, Register rn, Register rm);
   1165 
   1166   void smulbt(Condition cond, Register rd, Register rn, Register rm);
   1167 
   1168   void smull(
   1169       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
   1170 
   1171   void smulls(
   1172       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
   1173 
   1174   void smultb(Condition cond, Register rd, Register rn, Register rm);
   1175 
   1176   void smultt(Condition cond, Register rd, Register rn, Register rm);
   1177 
   1178   void smulwb(Condition cond, Register rd, Register rn, Register rm);
   1179 
   1180   void smulwt(Condition cond, Register rd, Register rn, Register rm);
   1181 
   1182   void smusd(Condition cond, Register rd, Register rn, Register rm);
   1183 
   1184   void smusdx(Condition cond, Register rd, Register rn, Register rm);
   1185 
   1186   void ssat(Condition cond, Register rd, uint32_t imm, const Operand& operand);
   1187 
   1188   void ssat16(Condition cond, Register rd, uint32_t imm, Register rn);
   1189 
   1190   void ssax(Condition cond, Register rd, Register rn, Register rm);
   1191 
   1192   void ssub16(Condition cond, Register rd, Register rn, Register rm);
   1193 
   1194   void ssub8(Condition cond, Register rd, Register rn, Register rm);
   1195 
   1196   void stl(Condition cond, Register rt, const MemOperand& operand);
   1197 
   1198   void stlb(Condition cond, Register rt, const MemOperand& operand);
   1199 
   1200   void stlex(Condition cond,
   1201              Register rd,
   1202              Register rt,
   1203              const MemOperand& operand);
   1204 
   1205   void stlexb(Condition cond,
   1206               Register rd,
   1207               Register rt,
   1208               const MemOperand& operand);
   1209 
   1210   void stlexd(Condition cond,
   1211               Register rd,
   1212               Register rt,
   1213               Register rt2,
   1214               const MemOperand& operand);
   1215 
   1216   void stlexh(Condition cond,
   1217               Register rd,
   1218               Register rt,
   1219               const MemOperand& operand);
   1220 
   1221   void stlh(Condition cond, Register rt, const MemOperand& operand);
   1222 
   1223   void stm(Condition cond,
   1224            EncodingSize size,
   1225            Register rn,
   1226            WriteBack write_back,
   1227            RegisterList registers);
   1228 
   1229   void stmda(Condition cond,
   1230              Register rn,
   1231              WriteBack write_back,
   1232              RegisterList registers);
   1233 
   1234   void stmdb(Condition cond,
   1235              EncodingSize size,
   1236              Register rn,
   1237              WriteBack write_back,
   1238              RegisterList registers);
   1239 
   1240   void stmea(Condition cond,
   1241              EncodingSize size,
   1242              Register rn,
   1243              WriteBack write_back,
   1244              RegisterList registers);
   1245 
   1246   void stmed(Condition cond,
   1247              Register rn,
   1248              WriteBack write_back,
   1249              RegisterList registers);
   1250 
   1251   void stmfa(Condition cond,
   1252              Register rn,
   1253              WriteBack write_back,
   1254              RegisterList registers);
   1255 
   1256   void stmfd(Condition cond,
   1257              Register rn,
   1258              WriteBack write_back,
   1259              RegisterList registers);
   1260 
   1261   void stmib(Condition cond,
   1262              Register rn,
   1263              WriteBack write_back,
   1264              RegisterList registers);
   1265 
   1266   void str(Condition cond,
   1267            EncodingSize size,
   1268            Register rt,
   1269            const MemOperand& operand);
   1270 
   1271   void strb(Condition cond,
   1272             EncodingSize size,
   1273             Register rt,
   1274             const MemOperand& operand);
   1275 
   1276   void strd(Condition cond,
   1277             Register rt,
   1278             Register rt2,
   1279             const MemOperand& operand);
   1280 
   1281   void strex(Condition cond,
   1282              Register rd,
   1283              Register rt,
   1284              const MemOperand& operand);
   1285 
   1286   void strexb(Condition cond,
   1287               Register rd,
   1288               Register rt,
   1289               const MemOperand& operand);
   1290 
   1291   void strexd(Condition cond,
   1292               Register rd,
   1293               Register rt,
   1294               Register rt2,
   1295               const MemOperand& operand);
   1296 
   1297   void strexh(Condition cond,
   1298               Register rd,
   1299               Register rt,
   1300               const MemOperand& operand);
   1301 
   1302   void strh(Condition cond,
   1303             EncodingSize size,
   1304             Register rt,
   1305             const MemOperand& operand);
   1306 
   1307   void sub(Condition cond,
   1308            EncodingSize size,
   1309            Register rd,
   1310            Register rn,
   1311            const Operand& operand);
   1312 
   1313   void sub(Condition cond, Register rd, const Operand& operand);
   1314 
   1315   void subs(Condition cond,
   1316             EncodingSize size,
   1317             Register rd,
   1318             Register rn,
   1319             const Operand& operand);
   1320 
   1321   void subs(Register rd, const Operand& operand);
   1322 
   1323   void subw(Condition cond, Register rd, Register rn, const Operand& operand);
   1324 
   1325   void svc(Condition cond, uint32_t imm);
   1326 
   1327   void sxtab(Condition cond, Register rd, Register rn, const Operand& operand);
   1328 
   1329   void sxtab16(Condition cond,
   1330                Register rd,
   1331                Register rn,
   1332                const Operand& operand);
   1333 
   1334   void sxtah(Condition cond, Register rd, Register rn, const Operand& operand);
   1335 
   1336   void sxtb(Condition cond,
   1337             EncodingSize size,
   1338             Register rd,
   1339             const Operand& operand);
   1340 
   1341   void sxtb16(Condition cond, Register rd, const Operand& operand);
   1342 
   1343   void sxth(Condition cond,
   1344             EncodingSize size,
   1345             Register rd,
   1346             const Operand& operand);
   1347 
   1348   void tbb(Condition cond, Register rn, Register rm);
   1349 
   1350   void tbh(Condition cond, Register rn, Register rm);
   1351 
   1352   void teq(Condition cond, Register rn, const Operand& operand);
   1353 
   1354   void tst(Condition cond,
   1355            EncodingSize size,
   1356            Register rn,
   1357            const Operand& operand);
   1358 
   1359   void uadd16(Condition cond, Register rd, Register rn, Register rm);
   1360 
   1361   void uadd8(Condition cond, Register rd, Register rn, Register rm);
   1362 
   1363   void uasx(Condition cond, Register rd, Register rn, Register rm);
   1364 
   1365   void ubfx(
   1366       Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width);
   1367 
   1368   void udf(Condition cond, EncodingSize size, uint32_t imm);
   1369 
   1370   void udiv(Condition cond, Register rd, Register rn, Register rm);
   1371 
   1372   void uhadd16(Condition cond, Register rd, Register rn, Register rm);
   1373 
   1374   void uhadd8(Condition cond, Register rd, Register rn, Register rm);
   1375 
   1376   void uhasx(Condition cond, Register rd, Register rn, Register rm);
   1377 
   1378   void uhsax(Condition cond, Register rd, Register rn, Register rm);
   1379 
   1380   void uhsub16(Condition cond, Register rd, Register rn, Register rm);
   1381 
   1382   void uhsub8(Condition cond, Register rd, Register rn, Register rm);
   1383 
   1384   void umaal(
   1385       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
   1386 
   1387   void umlal(
   1388       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
   1389 
   1390   void umlals(
   1391       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
   1392 
   1393   void umull(
   1394       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
   1395 
   1396   void umulls(
   1397       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
   1398 
   1399   void uqadd16(Condition cond, Register rd, Register rn, Register rm);
   1400 
   1401   void uqadd8(Condition cond, Register rd, Register rn, Register rm);
   1402 
   1403   void uqasx(Condition cond, Register rd, Register rn, Register rm);
   1404 
   1405   void uqsax(Condition cond, Register rd, Register rn, Register rm);
   1406 
   1407   void uqsub16(Condition cond, Register rd, Register rn, Register rm);
   1408 
   1409   void uqsub8(Condition cond, Register rd, Register rn, Register rm);
   1410 
   1411   void usad8(Condition cond, Register rd, Register rn, Register rm);
   1412 
   1413   void usada8(
   1414       Condition cond, Register rd, Register rn, Register rm, Register ra);
   1415 
   1416   void usat(Condition cond, Register rd, uint32_t imm, const Operand& operand);
   1417 
   1418   void usat16(Condition cond, Register rd, uint32_t imm, Register rn);
   1419 
   1420   void usax(Condition cond, Register rd, Register rn, Register rm);
   1421 
   1422   void usub16(Condition cond, Register rd, Register rn, Register rm);
   1423 
   1424   void usub8(Condition cond, Register rd, Register rn, Register rm);
   1425 
   1426   void uxtab(Condition cond, Register rd, Register rn, const Operand& operand);
   1427 
   1428   void uxtab16(Condition cond,
   1429                Register rd,
   1430                Register rn,
   1431                const Operand& operand);
   1432 
   1433   void uxtah(Condition cond, Register rd, Register rn, const Operand& operand);
   1434 
   1435   void uxtb(Condition cond,
   1436             EncodingSize size,
   1437             Register rd,
   1438             const Operand& operand);
   1439 
   1440   void uxtb16(Condition cond, Register rd, const Operand& operand);
   1441 
   1442   void uxth(Condition cond,
   1443             EncodingSize size,
   1444             Register rd,
   1445             const Operand& operand);
   1446 
   1447   void vaba(
   1448       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1449 
   1450   void vaba(
   1451       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1452 
   1453   void vabal(
   1454       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
   1455 
   1456   void vabd(
   1457       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1458 
   1459   void vabd(
   1460       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1461 
   1462   void vabdl(
   1463       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
   1464 
   1465   void vabs(Condition cond, DataType dt, DRegister rd, DRegister rm);
   1466 
   1467   void vabs(Condition cond, DataType dt, QRegister rd, QRegister rm);
   1468 
   1469   void vabs(Condition cond, DataType dt, SRegister rd, SRegister rm);
   1470 
   1471   void vacge(
   1472       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1473 
   1474   void vacge(
   1475       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1476 
   1477   void vacgt(
   1478       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1479 
   1480   void vacgt(
   1481       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1482 
   1483   void vacle(
   1484       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1485 
   1486   void vacle(
   1487       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1488 
   1489   void vaclt(
   1490       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1491 
   1492   void vaclt(
   1493       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1494 
   1495   void vadd(
   1496       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1497 
   1498   void vadd(
   1499       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1500 
   1501   void vadd(
   1502       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
   1503 
   1504   void vaddhn(
   1505       Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm);
   1506 
   1507   void vaddl(
   1508       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
   1509 
   1510   void vaddw(
   1511       Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm);
   1512 
   1513   void vand(Condition cond,
   1514             DataType dt,
   1515             DRegister rd,
   1516             DRegister rn,
   1517             const DOperand& operand);
   1518 
   1519   void vand(Condition cond,
   1520             DataType dt,
   1521             QRegister rd,
   1522             QRegister rn,
   1523             const QOperand& operand);
   1524 
   1525   void vbic(Condition cond,
   1526             DataType dt,
   1527             DRegister rd,
   1528             DRegister rn,
   1529             const DOperand& operand);
   1530 
   1531   void vbic(Condition cond,
   1532             DataType dt,
   1533             QRegister rd,
   1534             QRegister rn,
   1535             const QOperand& operand);
   1536 
   1537   void vbif(
   1538       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1539 
   1540   void vbif(
   1541       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1542 
   1543   void vbit(
   1544       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1545 
   1546   void vbit(
   1547       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1548 
   1549   void vbsl(
   1550       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1551 
   1552   void vbsl(
   1553       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1554 
   1555   void vceq(Condition cond,
   1556             DataType dt,
   1557             DRegister rd,
   1558             DRegister rm,
   1559             const DOperand& operand);
   1560 
   1561   void vceq(Condition cond,
   1562             DataType dt,
   1563             QRegister rd,
   1564             QRegister rm,
   1565             const QOperand& operand);
   1566 
   1567   void vceq(
   1568       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1569 
   1570   void vceq(
   1571       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1572 
   1573   void vcge(Condition cond,
   1574             DataType dt,
   1575             DRegister rd,
   1576             DRegister rm,
   1577             const DOperand& operand);
   1578 
   1579   void vcge(Condition cond,
   1580             DataType dt,
   1581             QRegister rd,
   1582             QRegister rm,
   1583             const QOperand& operand);
   1584 
   1585   void vcge(
   1586       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1587 
   1588   void vcge(
   1589       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1590 
   1591   void vcgt(Condition cond,
   1592             DataType dt,
   1593             DRegister rd,
   1594             DRegister rm,
   1595             const DOperand& operand);
   1596 
   1597   void vcgt(Condition cond,
   1598             DataType dt,
   1599             QRegister rd,
   1600             QRegister rm,
   1601             const QOperand& operand);
   1602 
   1603   void vcgt(
   1604       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1605 
   1606   void vcgt(
   1607       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1608 
   1609   void vcle(Condition cond,
   1610             DataType dt,
   1611             DRegister rd,
   1612             DRegister rm,
   1613             const DOperand& operand);
   1614 
   1615   void vcle(Condition cond,
   1616             DataType dt,
   1617             QRegister rd,
   1618             QRegister rm,
   1619             const QOperand& operand);
   1620 
   1621   void vcle(
   1622       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1623 
   1624   void vcle(
   1625       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1626 
   1627   void vcls(Condition cond, DataType dt, DRegister rd, DRegister rm);
   1628 
   1629   void vcls(Condition cond, DataType dt, QRegister rd, QRegister rm);
   1630 
   1631   void vclt(Condition cond,
   1632             DataType dt,
   1633             DRegister rd,
   1634             DRegister rm,
   1635             const DOperand& operand);
   1636 
   1637   void vclt(Condition cond,
   1638             DataType dt,
   1639             QRegister rd,
   1640             QRegister rm,
   1641             const QOperand& operand);
   1642 
   1643   void vclt(
   1644       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1645 
   1646   void vclt(
   1647       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1648 
   1649   void vclz(Condition cond, DataType dt, DRegister rd, DRegister rm);
   1650 
   1651   void vclz(Condition cond, DataType dt, QRegister rd, QRegister rm);
   1652 
   1653   void vcmp(Condition cond, DataType dt, SRegister rd, const SOperand& operand);
   1654 
   1655   void vcmp(Condition cond, DataType dt, DRegister rd, const DOperand& operand);
   1656 
   1657   void vcmpe(Condition cond,
   1658              DataType dt,
   1659              SRegister rd,
   1660              const SOperand& operand);
   1661 
   1662   void vcmpe(Condition cond,
   1663              DataType dt,
   1664              DRegister rd,
   1665              const DOperand& operand);
   1666 
   1667   void vcnt(Condition cond, DataType dt, DRegister rd, DRegister rm);
   1668 
   1669   void vcnt(Condition cond, DataType dt, QRegister rd, QRegister rm);
   1670 
   1671   void vcvt(
   1672       Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm);
   1673 
   1674   void vcvt(
   1675       Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm);
   1676 
   1677   void vcvt(Condition cond,
   1678             DataType dt1,
   1679             DataType dt2,
   1680             DRegister rd,
   1681             DRegister rm,
   1682             int32_t fbits);
   1683 
   1684   void vcvt(Condition cond,
   1685             DataType dt1,
   1686             DataType dt2,
   1687             QRegister rd,
   1688             QRegister rm,
   1689             int32_t fbits);
   1690 
   1691   void vcvt(Condition cond,
   1692             DataType dt1,
   1693             DataType dt2,
   1694             SRegister rd,
   1695             SRegister rm,
   1696             int32_t fbits);
   1697 
   1698   void vcvt(
   1699       Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm);
   1700 
   1701   void vcvt(
   1702       Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm);
   1703 
   1704   void vcvt(
   1705       Condition cond, DataType dt1, DataType dt2, DRegister rd, QRegister rm);
   1706 
   1707   void vcvt(
   1708       Condition cond, DataType dt1, DataType dt2, QRegister rd, DRegister rm);
   1709 
   1710   void vcvt(
   1711       Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm);
   1712 
   1713   void vcvta(DataType dt1, DataType dt2, DRegister rd, DRegister rm);
   1714 
   1715   void vcvta(DataType dt1, DataType dt2, QRegister rd, QRegister rm);
   1716 
   1717   void vcvta(DataType dt1, DataType dt2, SRegister rd, SRegister rm);
   1718 
   1719   void vcvta(DataType dt1, DataType dt2, SRegister rd, DRegister rm);
   1720 
   1721   void vcvtb(
   1722       Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm);
   1723 
   1724   void vcvtb(
   1725       Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm);
   1726 
   1727   void vcvtb(
   1728       Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm);
   1729 
   1730   void vcvtm(DataType dt1, DataType dt2, DRegister rd, DRegister rm);
   1731 
   1732   void vcvtm(DataType dt1, DataType dt2, QRegister rd, QRegister rm);
   1733 
   1734   void vcvtm(DataType dt1, DataType dt2, SRegister rd, SRegister rm);
   1735 
   1736   void vcvtm(DataType dt1, DataType dt2, SRegister rd, DRegister rm);
   1737 
   1738   void vcvtn(DataType dt1, DataType dt2, DRegister rd, DRegister rm);
   1739 
   1740   void vcvtn(DataType dt1, DataType dt2, QRegister rd, QRegister rm);
   1741 
   1742   void vcvtn(DataType dt1, DataType dt2, SRegister rd, SRegister rm);
   1743 
   1744   void vcvtn(DataType dt1, DataType dt2, SRegister rd, DRegister rm);
   1745 
   1746   void vcvtp(DataType dt1, DataType dt2, DRegister rd, DRegister rm);
   1747 
   1748   void vcvtp(DataType dt1, DataType dt2, QRegister rd, QRegister rm);
   1749 
   1750   void vcvtp(DataType dt1, DataType dt2, SRegister rd, SRegister rm);
   1751 
   1752   void vcvtp(DataType dt1, DataType dt2, SRegister rd, DRegister rm);
   1753 
   1754   void vcvtr(
   1755       Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm);
   1756 
   1757   void vcvtr(
   1758       Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm);
   1759 
   1760   void vcvtt(
   1761       Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm);
   1762 
   1763   void vcvtt(
   1764       Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm);
   1765 
   1766   void vcvtt(
   1767       Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm);
   1768 
   1769   void vdiv(
   1770       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
   1771 
   1772   void vdiv(
   1773       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1774 
   1775   void vdup(Condition cond, DataType dt, QRegister rd, Register rt);
   1776 
   1777   void vdup(Condition cond, DataType dt, DRegister rd, Register rt);
   1778 
   1779   void vdup(Condition cond, DataType dt, DRegister rd, DRegisterLane rm);
   1780 
   1781   void vdup(Condition cond, DataType dt, QRegister rd, DRegisterLane rm);
   1782 
   1783   void veor(
   1784       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1785 
   1786   void veor(
   1787       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1788 
   1789   void vext(Condition cond,
   1790             DataType dt,
   1791             DRegister rd,
   1792             DRegister rn,
   1793             DRegister rm,
   1794             const DOperand& operand);
   1795 
   1796   void vext(Condition cond,
   1797             DataType dt,
   1798             QRegister rd,
   1799             QRegister rn,
   1800             QRegister rm,
   1801             const QOperand& operand);
   1802 
   1803   void vfma(
   1804       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1805 
   1806   void vfma(
   1807       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1808 
   1809   void vfma(
   1810       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
   1811 
   1812   void vfms(
   1813       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1814 
   1815   void vfms(
   1816       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1817 
   1818   void vfms(
   1819       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
   1820 
   1821   void vfnma(
   1822       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
   1823 
   1824   void vfnma(
   1825       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1826 
   1827   void vfnms(
   1828       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
   1829 
   1830   void vfnms(
   1831       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1832 
   1833   void vhadd(
   1834       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1835 
   1836   void vhadd(
   1837       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1838 
   1839   void vhsub(
   1840       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1841 
   1842   void vhsub(
   1843       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1844 
   1845   void vld1(Condition cond,
   1846             DataType dt,
   1847             const NeonRegisterList& nreglist,
   1848             const AlignedMemOperand& operand);
   1849 
   1850   void vld2(Condition cond,
   1851             DataType dt,
   1852             const NeonRegisterList& nreglist,
   1853             const AlignedMemOperand& operand);
   1854 
   1855   void vld3(Condition cond,
   1856             DataType dt,
   1857             const NeonRegisterList& nreglist,
   1858             const AlignedMemOperand& operand);
   1859 
   1860   void vld3(Condition cond,
   1861             DataType dt,
   1862             const NeonRegisterList& nreglist,
   1863             const MemOperand& operand);
   1864 
   1865   void vld4(Condition cond,
   1866             DataType dt,
   1867             const NeonRegisterList& nreglist,
   1868             const AlignedMemOperand& operand);
   1869 
   1870   void vldm(Condition cond,
   1871             DataType dt,
   1872             Register rn,
   1873             WriteBack write_back,
   1874             DRegisterList dreglist);
   1875 
   1876   void vldm(Condition cond,
   1877             DataType dt,
   1878             Register rn,
   1879             WriteBack write_back,
   1880             SRegisterList sreglist);
   1881 
   1882   void vldmdb(Condition cond,
   1883               DataType dt,
   1884               Register rn,
   1885               WriteBack write_back,
   1886               DRegisterList dreglist);
   1887 
   1888   void vldmdb(Condition cond,
   1889               DataType dt,
   1890               Register rn,
   1891               WriteBack write_back,
   1892               SRegisterList sreglist);
   1893 
   1894   void vldmia(Condition cond,
   1895               DataType dt,
   1896               Register rn,
   1897               WriteBack write_back,
   1898               DRegisterList dreglist);
   1899 
   1900   void vldmia(Condition cond,
   1901               DataType dt,
   1902               Register rn,
   1903               WriteBack write_back,
   1904               SRegisterList sreglist);
   1905 
   1906   void vldr(Condition cond, DataType dt, DRegister rd, Location* location);
   1907 
   1908   void vldr(Condition cond,
   1909             DataType dt,
   1910             DRegister rd,
   1911             const MemOperand& operand);
   1912 
   1913   void vldr(Condition cond, DataType dt, SRegister rd, Location* location);
   1914 
   1915   void vldr(Condition cond,
   1916             DataType dt,
   1917             SRegister rd,
   1918             const MemOperand& operand);
   1919 
   1920   void vmax(
   1921       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1922 
   1923   void vmax(
   1924       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1925 
   1926   void vmaxnm(DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1927 
   1928   void vmaxnm(DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1929 
   1930   void vmaxnm(DataType dt, SRegister rd, SRegister rn, SRegister rm);
   1931 
   1932   void vmin(
   1933       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1934 
   1935   void vmin(
   1936       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1937 
   1938   void vminnm(DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1939 
   1940   void vminnm(DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1941 
   1942   void vminnm(DataType dt, SRegister rd, SRegister rn, SRegister rm);
   1943 
   1944   void vmla(Condition cond,
   1945             DataType dt,
   1946             DRegister rd,
   1947             DRegister rn,
   1948             DRegisterLane rm);
   1949 
   1950   void vmla(Condition cond,
   1951             DataType dt,
   1952             QRegister rd,
   1953             QRegister rn,
   1954             DRegisterLane rm);
   1955 
   1956   void vmla(
   1957       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1958 
   1959   void vmla(
   1960       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1961 
   1962   void vmla(
   1963       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
   1964 
   1965   void vmlal(Condition cond,
   1966              DataType dt,
   1967              QRegister rd,
   1968              DRegister rn,
   1969              DRegisterLane rm);
   1970 
   1971   void vmlal(
   1972       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
   1973 
   1974   void vmls(Condition cond,
   1975             DataType dt,
   1976             DRegister rd,
   1977             DRegister rn,
   1978             DRegisterLane rm);
   1979 
   1980   void vmls(Condition cond,
   1981             DataType dt,
   1982             QRegister rd,
   1983             QRegister rn,
   1984             DRegisterLane rm);
   1985 
   1986   void vmls(
   1987       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   1988 
   1989   void vmls(
   1990       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   1991 
   1992   void vmls(
   1993       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
   1994 
   1995   void vmlsl(Condition cond,
   1996              DataType dt,
   1997              QRegister rd,
   1998              DRegister rn,
   1999              DRegisterLane rm);
   2000 
   2001   void vmlsl(
   2002       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
   2003 
   2004   void vmov(Condition cond, Register rt, SRegister rn);
   2005 
   2006   void vmov(Condition cond, SRegister rn, Register rt);
   2007 
   2008   void vmov(Condition cond, Register rt, Register rt2, DRegister rm);
   2009 
   2010   void vmov(Condition cond, DRegister rm, Register rt, Register rt2);
   2011 
   2012   void vmov(
   2013       Condition cond, Register rt, Register rt2, SRegister rm, SRegister rm1);
   2014 
   2015   void vmov(
   2016       Condition cond, SRegister rm, SRegister rm1, Register rt, Register rt2);
   2017 
   2018   void vmov(Condition cond, DataType dt, DRegisterLane rd, Register rt);
   2019 
   2020   void vmov(Condition cond, DataType dt, DRegister rd, const DOperand& operand);
   2021 
   2022   void vmov(Condition cond, DataType dt, QRegister rd, const QOperand& operand);
   2023 
   2024   void vmov(Condition cond, DataType dt, SRegister rd, const SOperand& operand);
   2025 
   2026   void vmov(Condition cond, DataType dt, Register rt, DRegisterLane rn);
   2027 
   2028   void vmovl(Condition cond, DataType dt, QRegister rd, DRegister rm);
   2029 
   2030   void vmovn(Condition cond, DataType dt, DRegister rd, QRegister rm);
   2031 
   2032   void vmrs(Condition cond, RegisterOrAPSR_nzcv rt, SpecialFPRegister spec_reg);
   2033 
   2034   void vmsr(Condition cond, SpecialFPRegister spec_reg, Register rt);
   2035 
   2036   void vmul(Condition cond,
   2037             DataType dt,
   2038             DRegister rd,
   2039             DRegister rn,
   2040             DRegister dm,
   2041             unsigned index);
   2042 
   2043   void vmul(Condition cond,
   2044             DataType dt,
   2045             QRegister rd,
   2046             QRegister rn,
   2047             DRegister dm,
   2048             unsigned index);
   2049 
   2050   void vmul(
   2051       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   2052 
   2053   void vmul(
   2054       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   2055 
   2056   void vmul(
   2057       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
   2058 
   2059   void vmull(Condition cond,
   2060              DataType dt,
   2061              QRegister rd,
   2062              DRegister rn,
   2063              DRegister dm,
   2064              unsigned index);
   2065 
   2066   void vmull(
   2067       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
   2068 
   2069   void vmvn(Condition cond, DataType dt, DRegister rd, const DOperand& operand);
   2070 
   2071   void vmvn(Condition cond, DataType dt, QRegister rd, const QOperand& operand);
   2072 
   2073   void vneg(Condition cond, DataType dt, DRegister rd, DRegister rm);
   2074 
   2075   void vneg(Condition cond, DataType dt, QRegister rd, QRegister rm);
   2076 
   2077   void vneg(Condition cond, DataType dt, SRegister rd, SRegister rm);
   2078 
   2079   void vnmla(
   2080       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
   2081 
   2082   void vnmla(
   2083       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   2084 
   2085   void vnmls(
   2086       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
   2087 
   2088   void vnmls(
   2089       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   2090 
   2091   void vnmul(
   2092       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
   2093 
   2094   void vnmul(
   2095       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   2096 
   2097   void vorn(Condition cond,
   2098             DataType dt,
   2099             DRegister rd,
   2100             DRegister rn,
   2101             const DOperand& operand);
   2102 
   2103   void vorn(Condition cond,
   2104             DataType dt,
   2105             QRegister rd,
   2106             QRegister rn,
   2107             const QOperand& operand);
   2108 
   2109   void vorr(Condition cond,
   2110             DataType dt,
   2111             DRegister rd,
   2112             DRegister rn,
   2113             const DOperand& operand);
   2114 
   2115   void vorr(Condition cond,
   2116             DataType dt,
   2117             QRegister rd,
   2118             QRegister rn,
   2119             const QOperand& operand);
   2120 
   2121   void vpadal(Condition cond, DataType dt, DRegister rd, DRegister rm);
   2122 
   2123   void vpadal(Condition cond, DataType dt, QRegister rd, QRegister rm);
   2124 
   2125   void vpadd(
   2126       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   2127 
   2128   void vpaddl(Condition cond, DataType dt, DRegister rd, DRegister rm);
   2129 
   2130   void vpaddl(Condition cond, DataType dt, QRegister rd, QRegister rm);
   2131 
   2132   void vpmax(
   2133       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   2134 
   2135   void vpmin(
   2136       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   2137 
   2138   void vpop(Condition cond, DataType dt, DRegisterList dreglist);
   2139 
   2140   void vpop(Condition cond, DataType dt, SRegisterList sreglist);
   2141 
   2142   void vpush(Condition cond, DataType dt, DRegisterList dreglist);
   2143 
   2144   void vpush(Condition cond, DataType dt, SRegisterList sreglist);
   2145 
   2146   void vqabs(Condition cond, DataType dt, DRegister rd, DRegister rm);
   2147 
   2148   void vqabs(Condition cond, DataType dt, QRegister rd, QRegister rm);
   2149 
   2150   void vqadd(
   2151       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   2152 
   2153   void vqadd(
   2154       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   2155 
   2156   void vqdmlal(
   2157       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
   2158 
   2159   void vqdmlal(Condition cond,
   2160                DataType dt,
   2161                QRegister rd,
   2162                DRegister rn,
   2163                DRegister dm,
   2164                unsigned index);
   2165 
   2166   void vqdmlsl(
   2167       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
   2168 
   2169   void vqdmlsl(Condition cond,
   2170                DataType dt,
   2171                QRegister rd,
   2172                DRegister rn,
   2173                DRegister dm,
   2174                unsigned index);
   2175 
   2176   void vqdmulh(
   2177       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   2178 
   2179   void vqdmulh(
   2180       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   2181 
   2182   void vqdmulh(Condition cond,
   2183                DataType dt,
   2184                DRegister rd,
   2185                DRegister rn,
   2186                DRegisterLane rm);
   2187 
   2188   void vqdmulh(Condition cond,
   2189                DataType dt,
   2190                QRegister rd,
   2191                QRegister rn,
   2192                DRegisterLane rm);
   2193 
   2194   void vqdmull(
   2195       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
   2196 
   2197   void vqdmull(Condition cond,
   2198                DataType dt,
   2199                QRegister rd,
   2200                DRegister rn,
   2201                DRegisterLane rm);
   2202 
   2203   void vqmovn(Condition cond, DataType dt, DRegister rd, QRegister rm);
   2204 
   2205   void vqmovun(Condition cond, DataType dt, DRegister rd, QRegister rm);
   2206 
   2207   void vqneg(Condition cond, DataType dt, DRegister rd, DRegister rm);
   2208 
   2209   void vqneg(Condition cond, DataType dt, QRegister rd, QRegister rm);
   2210 
   2211   void vqrdmulh(
   2212       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   2213 
   2214   void vqrdmulh(
   2215       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   2216 
   2217   void vqrdmulh(Condition cond,
   2218                 DataType dt,
   2219                 DRegister rd,
   2220                 DRegister rn,
   2221                 DRegisterLane rm);
   2222 
   2223   void vqrdmulh(Condition cond,
   2224                 DataType dt,
   2225                 QRegister rd,
   2226                 QRegister rn,
   2227                 DRegisterLane rm);
   2228 
   2229   void vqrshl(
   2230       Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn);
   2231 
   2232   void vqrshl(
   2233       Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn);
   2234 
   2235   void vqrshrn(Condition cond,
   2236                DataType dt,
   2237                DRegister rd,
   2238                QRegister rm,
   2239                const QOperand& operand);
   2240 
   2241   void vqrshrun(Condition cond,
   2242                 DataType dt,
   2243                 DRegister rd,
   2244                 QRegister rm,
   2245                 const QOperand& operand);
   2246 
   2247   void vqshl(Condition cond,
   2248              DataType dt,
   2249              DRegister rd,
   2250              DRegister rm,
   2251              const DOperand& operand);
   2252 
   2253   void vqshl(Condition cond,
   2254              DataType dt,
   2255              QRegister rd,
   2256              QRegister rm,
   2257              const QOperand& operand);
   2258 
   2259   void vqshlu(Condition cond,
   2260               DataType dt,
   2261               DRegister rd,
   2262               DRegister rm,
   2263               const DOperand& operand);
   2264 
   2265   void vqshlu(Condition cond,
   2266               DataType dt,
   2267               QRegister rd,
   2268               QRegister rm,
   2269               const QOperand& operand);
   2270 
   2271   void vqshrn(Condition cond,
   2272               DataType dt,
   2273               DRegister rd,
   2274               QRegister rm,
   2275               const QOperand& operand);
   2276 
   2277   void vqshrun(Condition cond,
   2278                DataType dt,
   2279                DRegister rd,
   2280                QRegister rm,
   2281                const QOperand& operand);
   2282 
   2283   void vqsub(
   2284       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   2285 
   2286   void vqsub(
   2287       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   2288 
   2289   void vraddhn(
   2290       Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm);
   2291 
   2292   void vrecpe(Condition cond, DataType dt, DRegister rd, DRegister rm);
   2293 
   2294   void vrecpe(Condition cond, DataType dt, QRegister rd, QRegister rm);
   2295 
   2296   void vrecps(
   2297       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   2298 
   2299   void vrecps(
   2300       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   2301 
   2302   void vrev16(Condition cond, DataType dt, DRegister rd, DRegister rm);
   2303 
   2304   void vrev16(Condition cond, DataType dt, QRegister rd, QRegister rm);
   2305 
   2306   void vrev32(Condition cond, DataType dt, DRegister rd, DRegister rm);
   2307 
   2308   void vrev32(Condition cond, DataType dt, QRegister rd, QRegister rm);
   2309 
   2310   void vrev64(Condition cond, DataType dt, DRegister rd, DRegister rm);
   2311 
   2312   void vrev64(Condition cond, DataType dt, QRegister rd, QRegister rm);
   2313 
   2314   void vrhadd(
   2315       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   2316 
   2317   void vrhadd(
   2318       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   2319 
   2320   void vrinta(DataType dt1, DataType dt2, DRegister rd, DRegister rm);
   2321 
   2322   void vrinta(DataType dt1, DataType dt2, QRegister rd, QRegister rm);
   2323 
   2324   void vrinta(DataType dt1, DataType dt2, SRegister rd, SRegister rm);
   2325 
   2326   void vrintm(DataType dt1, DataType dt2, DRegister rd, DRegister rm);
   2327 
   2328   void vrintm(DataType dt1, DataType dt2, QRegister rd, QRegister rm);
   2329 
   2330   void vrintm(DataType dt1, DataType dt2, SRegister rd, SRegister rm);
   2331 
   2332   void vrintn(DataType dt1, DataType dt2, DRegister rd, DRegister rm);
   2333 
   2334   void vrintn(DataType dt1, DataType dt2, QRegister rd, QRegister rm);
   2335 
   2336   void vrintn(DataType dt1, DataType dt2, SRegister rd, SRegister rm);
   2337 
   2338   void vrintp(DataType dt1, DataType dt2, DRegister rd, DRegister rm);
   2339 
   2340   void vrintp(DataType dt1, DataType dt2, QRegister rd, QRegister rm);
   2341 
   2342   void vrintp(DataType dt1, DataType dt2, SRegister rd, SRegister rm);
   2343 
   2344   void vrintr(
   2345       Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm);
   2346 
   2347   void vrintr(
   2348       Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm);
   2349 
   2350   void vrintx(
   2351       Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm);
   2352 
   2353   void vrintx(DataType dt1, DataType dt2, QRegister rd, QRegister rm);
   2354 
   2355   void vrintx(
   2356       Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm);
   2357 
   2358   void vrintz(
   2359       Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm);
   2360 
   2361   void vrintz(DataType dt1, DataType dt2, QRegister rd, QRegister rm);
   2362 
   2363   void vrintz(
   2364       Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm);
   2365 
   2366   void vrshl(
   2367       Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn);
   2368 
   2369   void vrshl(
   2370       Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn);
   2371 
   2372   void vrshr(Condition cond,
   2373              DataType dt,
   2374              DRegister rd,
   2375              DRegister rm,
   2376              const DOperand& operand);
   2377 
   2378   void vrshr(Condition cond,
   2379              DataType dt,
   2380              QRegister rd,
   2381              QRegister rm,
   2382              const QOperand& operand);
   2383 
   2384   void vrshrn(Condition cond,
   2385               DataType dt,
   2386               DRegister rd,
   2387               QRegister rm,
   2388               const QOperand& operand);
   2389 
   2390   void vrsqrte(Condition cond, DataType dt, DRegister rd, DRegister rm);
   2391 
   2392   void vrsqrte(Condition cond, DataType dt, QRegister rd, QRegister rm);
   2393 
   2394   void vrsqrts(
   2395       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   2396 
   2397   void vrsqrts(
   2398       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   2399 
   2400   void vrsra(Condition cond,
   2401              DataType dt,
   2402              DRegister rd,
   2403              DRegister rm,
   2404              const DOperand& operand);
   2405 
   2406   void vrsra(Condition cond,
   2407              DataType dt,
   2408              QRegister rd,
   2409              QRegister rm,
   2410              const QOperand& operand);
   2411 
   2412   void vrsubhn(
   2413       Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm);
   2414 
   2415   void vseleq(DataType dt, DRegister rd, DRegister rn, DRegister rm);
   2416 
   2417   void vseleq(DataType dt, SRegister rd, SRegister rn, SRegister rm);
   2418 
   2419   void vselge(DataType dt, DRegister rd, DRegister rn, DRegister rm);
   2420 
   2421   void vselge(DataType dt, SRegister rd, SRegister rn, SRegister rm);
   2422 
   2423   void vselgt(DataType dt, DRegister rd, DRegister rn, DRegister rm);
   2424 
   2425   void vselgt(DataType dt, SRegister rd, SRegister rn, SRegister rm);
   2426 
   2427   void vselvs(DataType dt, DRegister rd, DRegister rn, DRegister rm);
   2428 
   2429   void vselvs(DataType dt, SRegister rd, SRegister rn, SRegister rm);
   2430 
   2431   void vshl(Condition cond,
   2432             DataType dt,
   2433             DRegister rd,
   2434             DRegister rm,
   2435             const DOperand& operand);
   2436 
   2437   void vshl(Condition cond,
   2438             DataType dt,
   2439             QRegister rd,
   2440             QRegister rm,
   2441             const QOperand& operand);
   2442 
   2443   void vshll(Condition cond,
   2444              DataType dt,
   2445              QRegister rd,
   2446              DRegister rm,
   2447              const DOperand& operand);
   2448 
   2449   void vshr(Condition cond,
   2450             DataType dt,
   2451             DRegister rd,
   2452             DRegister rm,
   2453             const DOperand& operand);
   2454 
   2455   void vshr(Condition cond,
   2456             DataType dt,
   2457             QRegister rd,
   2458             QRegister rm,
   2459             const QOperand& operand);
   2460 
   2461   void vshrn(Condition cond,
   2462              DataType dt,
   2463              DRegister rd,
   2464              QRegister rm,
   2465              const QOperand& operand);
   2466 
   2467   void vsli(Condition cond,
   2468             DataType dt,
   2469             DRegister rd,
   2470             DRegister rm,
   2471             const DOperand& operand);
   2472 
   2473   void vsli(Condition cond,
   2474             DataType dt,
   2475             QRegister rd,
   2476             QRegister rm,
   2477             const QOperand& operand);
   2478 
   2479   void vsqrt(Condition cond, DataType dt, SRegister rd, SRegister rm);
   2480 
   2481   void vsqrt(Condition cond, DataType dt, DRegister rd, DRegister rm);
   2482 
   2483   void vsra(Condition cond,
   2484             DataType dt,
   2485             DRegister rd,
   2486             DRegister rm,
   2487             const DOperand& operand);
   2488 
   2489   void vsra(Condition cond,
   2490             DataType dt,
   2491             QRegister rd,
   2492             QRegister rm,
   2493             const QOperand& operand);
   2494 
   2495   void vsri(Condition cond,
   2496             DataType dt,
   2497             DRegister rd,
   2498             DRegister rm,
   2499             const DOperand& operand);
   2500 
   2501   void vsri(Condition cond,
   2502             DataType dt,
   2503             QRegister rd,
   2504             QRegister rm,
   2505             const QOperand& operand);
   2506 
   2507   void vst1(Condition cond,
   2508             DataType dt,
   2509             const NeonRegisterList& nreglist,
   2510             const AlignedMemOperand& operand);
   2511 
   2512   void vst2(Condition cond,
   2513             DataType dt,
   2514             const NeonRegisterList& nreglist,
   2515             const AlignedMemOperand& operand);
   2516 
   2517   void vst3(Condition cond,
   2518             DataType dt,
   2519             const NeonRegisterList& nreglist,
   2520             const AlignedMemOperand& operand);
   2521 
   2522   void vst3(Condition cond,
   2523             DataType dt,
   2524             const NeonRegisterList& nreglist,
   2525             const MemOperand& operand);
   2526 
   2527   void vst4(Condition cond,
   2528             DataType dt,
   2529             const NeonRegisterList& nreglist,
   2530             const AlignedMemOperand& operand);
   2531 
   2532   void vstm(Condition cond,
   2533             DataType dt,
   2534             Register rn,
   2535             WriteBack write_back,
   2536             DRegisterList dreglist);
   2537 
   2538   void vstm(Condition cond,
   2539             DataType dt,
   2540             Register rn,
   2541             WriteBack write_back,
   2542             SRegisterList sreglist);
   2543 
   2544   void vstmdb(Condition cond,
   2545               DataType dt,
   2546               Register rn,
   2547               WriteBack write_back,
   2548               DRegisterList dreglist);
   2549 
   2550   void vstmdb(Condition cond,
   2551               DataType dt,
   2552               Register rn,
   2553               WriteBack write_back,
   2554               SRegisterList sreglist);
   2555 
   2556   void vstmia(Condition cond,
   2557               DataType dt,
   2558               Register rn,
   2559               WriteBack write_back,
   2560               DRegisterList dreglist);
   2561 
   2562   void vstmia(Condition cond,
   2563               DataType dt,
   2564               Register rn,
   2565               WriteBack write_back,
   2566               SRegisterList sreglist);
   2567 
   2568   void vstr(Condition cond,
   2569             DataType dt,
   2570             DRegister rd,
   2571             const MemOperand& operand);
   2572 
   2573   void vstr(Condition cond,
   2574             DataType dt,
   2575             SRegister rd,
   2576             const MemOperand& operand);
   2577 
   2578   void vsub(
   2579       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   2580 
   2581   void vsub(
   2582       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   2583 
   2584   void vsub(
   2585       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
   2586 
   2587   void vsubhn(
   2588       Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm);
   2589 
   2590   void vsubl(
   2591       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
   2592 
   2593   void vsubw(
   2594       Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm);
   2595 
   2596   void vswp(Condition cond, DataType dt, DRegister rd, DRegister rm);
   2597 
   2598   void vswp(Condition cond, DataType dt, QRegister rd, QRegister rm);
   2599 
   2600   void vtbl(Condition cond,
   2601             DataType dt,
   2602             DRegister rd,
   2603             const NeonRegisterList& nreglist,
   2604             DRegister rm);
   2605 
   2606   void vtbx(Condition cond,
   2607             DataType dt,
   2608             DRegister rd,
   2609             const NeonRegisterList& nreglist,
   2610             DRegister rm);
   2611 
   2612   void vtrn(Condition cond, DataType dt, DRegister rd, DRegister rm);
   2613 
   2614   void vtrn(Condition cond, DataType dt, QRegister rd, QRegister rm);
   2615 
   2616   void vtst(
   2617       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
   2618 
   2619   void vtst(
   2620       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
   2621 
   2622   void vuzp(Condition cond, DataType dt, DRegister rd, DRegister rm);
   2623 
   2624   void vuzp(Condition cond, DataType dt, QRegister rd, QRegister rm);
   2625 
   2626   void vzip(Condition cond, DataType dt, DRegister rd, DRegister rm);
   2627 
   2628   void vzip(Condition cond, DataType dt, QRegister rd, QRegister rm);
   2629 
   2630   void yield(Condition cond, EncodingSize size);
   2631 
   2632   int T32Size(uint32_t instr);
   2633   void DecodeT32(uint32_t instr);
   2634   void DecodeA32(uint32_t instr);
   2635 };
   2636 
   2637 DataTypeValue Dt_L_imm6_1_Decode(uint32_t value, uint32_t type_value);
   2638 DataTypeValue Dt_L_imm6_2_Decode(uint32_t value, uint32_t type_value);
   2639 DataTypeValue Dt_L_imm6_3_Decode(uint32_t value);
   2640 DataTypeValue Dt_L_imm6_4_Decode(uint32_t value);
   2641 DataTypeValue Dt_imm6_1_Decode(uint32_t value, uint32_t type_value);
   2642 DataTypeValue Dt_imm6_2_Decode(uint32_t value, uint32_t type_value);
   2643 DataTypeValue Dt_imm6_3_Decode(uint32_t value);
   2644 DataTypeValue Dt_imm6_4_Decode(uint32_t value, uint32_t type_value);
   2645 DataTypeValue Dt_op_U_size_1_Decode(uint32_t value);
   2646 DataTypeValue Dt_op_size_1_Decode(uint32_t value);
   2647 DataTypeValue Dt_op_size_2_Decode(uint32_t value);
   2648 DataTypeValue Dt_op_size_3_Decode(uint32_t value);
   2649 DataTypeValue Dt_U_imm3H_1_Decode(uint32_t value);
   2650 DataTypeValue Dt_U_opc1_opc2_1_Decode(uint32_t value, unsigned* lane);
   2651 DataTypeValue Dt_opc1_opc2_1_Decode(uint32_t value, unsigned* lane);
   2652 DataTypeValue Dt_imm4_1_Decode(uint32_t value, unsigned* lane);
   2653 DataTypeValue Dt_B_E_1_Decode(uint32_t value);
   2654 DataTypeValue Dt_op_1_Decode1(uint32_t value);
   2655 DataTypeValue Dt_op_1_Decode2(uint32_t value);
   2656 DataTypeValue Dt_op_2_Decode(uint32_t value);
   2657 DataTypeValue Dt_op_3_Decode(uint32_t value);
   2658 DataTypeValue Dt_U_sx_1_Decode(uint32_t value);
   2659 DataTypeValue Dt_op_U_1_Decode1(uint32_t value);
   2660 DataTypeValue Dt_op_U_1_Decode2(uint32_t value);
   2661 DataTypeValue Dt_sz_1_Decode(uint32_t value);
   2662 DataTypeValue Dt_F_size_1_Decode(uint32_t value);
   2663 DataTypeValue Dt_F_size_2_Decode(uint32_t value);
   2664 DataTypeValue Dt_F_size_3_Decode(uint32_t value);
   2665 DataTypeValue Dt_F_size_4_Decode(uint32_t value);
   2666 DataTypeValue Dt_U_size_1_Decode(uint32_t value);
   2667 DataTypeValue Dt_U_size_2_Decode(uint32_t value);
   2668 DataTypeValue Dt_U_size_3_Decode(uint32_t value);
   2669 DataTypeValue Dt_size_1_Decode(uint32_t value);
   2670 DataTypeValue Dt_size_2_Decode(uint32_t value);
   2671 DataTypeValue Dt_size_3_Decode(uint32_t value);
   2672 DataTypeValue Dt_size_4_Decode(uint32_t value);
   2673 DataTypeValue Dt_size_5_Decode(uint32_t value);
   2674 DataTypeValue Dt_size_6_Decode(uint32_t value);
   2675 DataTypeValue Dt_size_7_Decode(uint32_t value);
   2676 DataTypeValue Dt_size_8_Decode(uint32_t value);
   2677 DataTypeValue Dt_size_9_Decode(uint32_t value, uint32_t type_value);
   2678 DataTypeValue Dt_size_10_Decode(uint32_t value);
   2679 DataTypeValue Dt_size_11_Decode(uint32_t value, uint32_t type_value);
   2680 DataTypeValue Dt_size_12_Decode(uint32_t value, uint32_t type_value);
   2681 DataTypeValue Dt_size_13_Decode(uint32_t value);
   2682 DataTypeValue Dt_size_14_Decode(uint32_t value);
   2683 DataTypeValue Dt_size_15_Decode(uint32_t value);
   2684 DataTypeValue Dt_size_16_Decode(uint32_t value);
   2685 // End of generated code.
   2686 
   2687 class PrintDisassembler : public Disassembler {
   2688  public:
   2689   explicit PrintDisassembler(std::ostream& os,  // NOLINT(runtime/references)
   2690                              uint32_t code_address = 0)
   2691       : Disassembler(os, code_address) {}
   2692   explicit PrintDisassembler(DisassemblerStream* os, uint32_t code_address = 0)
   2693       : Disassembler(os, code_address) {}
   2694 
   2695   virtual void PrintCodeAddress(uint32_t code_address) {
   2696     os() << "0x" << std::hex << std::setw(8) << std::setfill('0')
   2697          << code_address << "\t";
   2698   }
   2699 
   2700   virtual void PrintOpcode16(uint32_t opcode) {
   2701     os() << std::hex << std::setw(4) << std::setfill('0') << opcode << "    "
   2702          << std::dec << "\t";
   2703   }
   2704 
   2705   virtual void PrintOpcode32(uint32_t opcode) {
   2706     os() << std::hex << std::setw(8) << std::setfill('0') << opcode << std::dec
   2707          << "\t";
   2708   }
   2709 
   2710   const uint32_t* DecodeA32At(const uint32_t* instruction_address) {
   2711     DecodeA32(*instruction_address);
   2712     return instruction_address + 1;
   2713   }
   2714 
   2715   // Returns the address of the next instruction.
   2716   const uint16_t* DecodeT32At(const uint16_t* instruction_address,
   2717                               const uint16_t* buffer_end);
   2718   void DecodeT32(uint32_t instruction);
   2719   void DecodeA32(uint32_t instruction);
   2720   void DisassembleA32Buffer(const uint32_t* buffer, size_t size_in_bytes);
   2721   void DisassembleT32Buffer(const uint16_t* buffer, size_t size_in_bytes);
   2722 };
   2723 
   2724 }  // namespace aarch32
   2725 }  // namespace vixl
   2726 
   2727 #endif  // VIXL_DISASM_AARCH32_H_
   2728