| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| gen8_sol_state.c | 83 OUT_RELOC64(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, start);
85 OUT_RELOC64(brw_obj->offset_bo,
|
| gen8_hs_state.c | 56 OUT_RELOC64(stage_state->scratch_bo,
|
| gen8_vs_state.c | 61 OUT_RELOC64(stage_state->scratch_bo,
|
| gen6_constant_state.c | 73 OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_RENDER, 0,
|
| gen8_ds_state.c | 55 OUT_RELOC64(stage_state->scratch_bo,
|
| gen8_gs_state.c | 62 OUT_RELOC64(stage_state->scratch_bo,
|
| intel_batchbuffer.c | 510 OUT_RELOC64(bo, read_domains, write_domain, offset + i * 4);
557 OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
586 OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
590 OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
684 OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
707 OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
|
| gen8_depth_state.c | 72 OUT_RELOC64(depth_mt->bo,
97 OUT_RELOC64(depth_mt->hiz_buf->aux_base.bo,
130 OUT_RELOC64(stencil_mt->bo,
|
| brw_pipe_control.c | 190 OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
|
| gen8_ps_state.c | 268 OUT_RELOC64(stage_state->scratch_bo,
|
| intel_batchbuffer.h | 172 #define OUT_RELOC64(buf, read_domains, write_domain, delta) do { \
|
| gen7_cs_state.c | 72 OUT_RELOC64(stage_state->scratch_bo,
|
| gen8_draw_upload.c | 379 OUT_RELOC64(brw->ib.bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
|
| intel_blit.c | 736 OUT_RELOC64(dst_buffer,
747 OUT_RELOC64(src_buffer,
821 OUT_RELOC64(dst_buffer,
[all...] |
| brw_binding_tables.c | 414 OUT_RELOC64(brw->hw_bt_pool.bo, I915_GEM_DOMAIN_SAMPLER, 0, dw1);
|
| hsw_queryobj.c | 341 OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION,
|
| brw_misc_state.c | [all...] |
| brw_draw_upload.c | 837 OUT_RELOC64(bo, I915_GEM_DOMAIN_VERTEX, 0, start_offset);
[all...] |
