| /device/linaro/bootloader/arm-trusted-firmware/lib/cpus/aarch32/ |
| aem_generic.S | 15 ldcopr r0, SCTLR
31 ldcopr r0, SCTLR
|
| cortex_a32.S | 56 ldcopr r0, SCTLR
87 ldcopr r0, SCTLR
|
| cortex_a53.S | 178 ldcopr r0, SCTLR
208 ldcopr r0, SCTLR
|
| cortex_a72.S | 124 ldcopr r0, SCTLR
171 ldcopr r0, SCTLR
|
| cortex_a57.S | 410 ldcopr r0, SCTLR
452 ldcopr r0, SCTLR
|
| /device/linaro/bootloader/arm-trusted-firmware/lib/psci/aarch32/ |
| psci_helpers.S | 89 ldcopr r0, SCTLR
91 stcopr r0, SCTLR
109 ldcopr r1, SCTLR
111 stcopr r1, SCTLR
|
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/Arm/ |
| ArmV7Support.asm | 74 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
75 orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU
76 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
82 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
83 bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
84 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
103 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
108 ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
109 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
110 orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled
[all...] |
| ArmV7Support.S | 165 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
167 mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
172 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
174 mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
251 # Ensure the SCTLR.V bit is clear
252 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
254 mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
|
| ArmLibSupport.S | 153 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
|
| /device/linaro/bootloader/arm-trusted-firmware/bl2/aarch32/ |
| bl2_entrypoint.S | 48 ldcopr r0, SCTLR
50 stcopr r0, SCTLR
|
| /device/linaro/bootloader/arm-trusted-firmware/bl2u/aarch32/ |
| bl2u_entrypoint.S | 49 ldcopr r0, SCTLR
51 stcopr r0, SCTLR
|
| /device/linaro/bootloader/arm-trusted-firmware/include/common/aarch32/ |
| el3_common_macros.S | 19 * SCTLR has already been initialised - read current value before
22 * SCTLR.I: Enable the instruction cache.
24 * SCTLR.A: Enable Alignment fault checking. All instructions that load
31 ldcopr r0, SCTLR
33 stcopr r0, SCTLR
133 * Whether the macro needs to initialise the SCTLR register including
174 * This is the initialisation of SCTLR and so must ensure that
178 * SCTLR.TE: Set to zero so that exceptions to an Exception
181 * SCTLR.EE: Set the CPU endianness before doing anything that
185 * SCTLR.V: Set to zero to select the normal exception vector
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/bl1/aarch32/ |
| bl1_exceptions.S | 117 ldcopr r9, SCTLR
119 stcopr r9, SCTLR
|
| /device/linaro/bootloader/arm-trusted-firmware/lib/aarch32/ |
| misc_helpers.S | 174 ldcopr r0, SCTLR
176 stcopr r0, SCTLR
|
| /device/linaro/bootloader/arm-trusted-firmware/bl32/sp_min/aarch32/ |
| entrypoint.S | 64 * SCTLR, including the CPU endianness, and has initialised the memory.
248 * programming the reset address do we need to initialied the SCTLR.
292 ldcopr r0, SCTLR
294 stcopr r0, SCTLR
|
| /device/linaro/bootloader/arm-trusted-firmware/include/lib/aarch32/ |
| arch_helpers.h | 237 DEFINE_COPROCR_RW_FUNCS(sctlr, SCTLR)
|
| arch.h | 89 /* SCTLR definitions */
387 #define SCTLR p15, 0, c1, c0, 0
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/include/drivers/ |
| smmu.h | 674 make_smmu_cb_cfg(SCTLR, n), \
|
