1 //==-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ ---===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines an instruction selector for the SystemZ target. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "SystemZ.h" 15 #include "SystemZTargetMachine.h" 16 #include "llvm/DerivedTypes.h" 17 #include "llvm/Function.h" 18 #include "llvm/Intrinsics.h" 19 #include "llvm/CallingConv.h" 20 #include "llvm/Constants.h" 21 #include "llvm/CodeGen/MachineFrameInfo.h" 22 #include "llvm/CodeGen/MachineFunction.h" 23 #include "llvm/CodeGen/MachineInstrBuilder.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/CodeGen/SelectionDAG.h" 26 #include "llvm/CodeGen/SelectionDAGISel.h" 27 #include "llvm/Target/TargetLowering.h" 28 #include "llvm/Support/Compiler.h" 29 #include "llvm/Support/Debug.h" 30 #include "llvm/Support/raw_ostream.h" 31 using namespace llvm; 32 33 namespace { 34 /// SystemZRRIAddressMode - This corresponds to rriaddr, but uses SDValue's 35 /// instead of register numbers for the leaves of the matched tree. 36 struct SystemZRRIAddressMode { 37 enum { 38 RegBase, 39 FrameIndexBase 40 } BaseType; 41 42 struct { // This is really a union, discriminated by BaseType! 43 SDValue Reg; 44 int FrameIndex; 45 } Base; 46 47 SDValue IndexReg; 48 int64_t Disp; 49 bool isRI; 50 51 SystemZRRIAddressMode(bool RI = false) 52 : BaseType(RegBase), IndexReg(), Disp(0), isRI(RI) { 53 } 54 55 void dump() { 56 errs() << "SystemZRRIAddressMode " << this << '\n'; 57 if (BaseType == RegBase) { 58 errs() << "Base.Reg "; 59 if (Base.Reg.getNode() != 0) 60 Base.Reg.getNode()->dump(); 61 else 62 errs() << "nul"; 63 errs() << '\n'; 64 } else { 65 errs() << " Base.FrameIndex " << Base.FrameIndex << '\n'; 66 } 67 if (!isRI) { 68 errs() << "IndexReg "; 69 if (IndexReg.getNode() != 0) IndexReg.getNode()->dump(); 70 else errs() << "nul"; 71 } 72 errs() << " Disp " << Disp << '\n'; 73 } 74 }; 75 } 76 77 /// SystemZDAGToDAGISel - SystemZ specific code to select SystemZ machine 78 /// instructions for SelectionDAG operations. 79 /// 80 namespace { 81 class SystemZDAGToDAGISel : public SelectionDAGISel { 82 const SystemZTargetLowering &Lowering; 83 const SystemZSubtarget &Subtarget; 84 85 void getAddressOperandsRI(const SystemZRRIAddressMode &AM, 86 SDValue &Base, SDValue &Disp); 87 void getAddressOperands(const SystemZRRIAddressMode &AM, 88 SDValue &Base, SDValue &Disp, 89 SDValue &Index); 90 91 public: 92 SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel) 93 : SelectionDAGISel(TM, OptLevel), 94 Lowering(*TM.getTargetLowering()), 95 Subtarget(*TM.getSubtargetImpl()) { } 96 97 virtual const char *getPassName() const { 98 return "SystemZ DAG->DAG Pattern Instruction Selection"; 99 } 100 101 /// getI8Imm - Return a target constant with the specified value, of type 102 /// i8. 103 inline SDValue getI8Imm(uint64_t Imm) { 104 return CurDAG->getTargetConstant(Imm, MVT::i8); 105 } 106 107 /// getI16Imm - Return a target constant with the specified value, of type 108 /// i16. 109 inline SDValue getI16Imm(uint64_t Imm) { 110 return CurDAG->getTargetConstant(Imm, MVT::i16); 111 } 112 113 /// getI32Imm - Return a target constant with the specified value, of type 114 /// i32. 115 inline SDValue getI32Imm(uint64_t Imm) { 116 return CurDAG->getTargetConstant(Imm, MVT::i32); 117 } 118 119 // Include the pieces autogenerated from the target description. 120 #include "SystemZGenDAGISel.inc" 121 122 private: 123 bool SelectAddrRI12Only(SDValue& Addr, 124 SDValue &Base, SDValue &Disp); 125 bool SelectAddrRI12(SDValue& Addr, 126 SDValue &Base, SDValue &Disp, 127 bool is12BitOnly = false); 128 bool SelectAddrRI(SDValue& Addr, SDValue &Base, SDValue &Disp); 129 bool SelectAddrRRI12(SDValue Addr, 130 SDValue &Base, SDValue &Disp, SDValue &Index); 131 bool SelectAddrRRI20(SDValue Addr, 132 SDValue &Base, SDValue &Disp, SDValue &Index); 133 bool SelectLAAddr(SDValue Addr, 134 SDValue &Base, SDValue &Disp, SDValue &Index); 135 136 SDNode *Select(SDNode *Node); 137 138 bool TryFoldLoad(SDNode *P, SDValue N, 139 SDValue &Base, SDValue &Disp, SDValue &Index); 140 141 bool MatchAddress(SDValue N, SystemZRRIAddressMode &AM, 142 bool is12Bit, unsigned Depth = 0); 143 bool MatchAddressBase(SDValue N, SystemZRRIAddressMode &AM); 144 }; 145 } // end anonymous namespace 146 147 /// createSystemZISelDag - This pass converts a legalized DAG into a 148 /// SystemZ-specific DAG, ready for instruction scheduling. 149 /// 150 FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM, 151 CodeGenOpt::Level OptLevel) { 152 return new SystemZDAGToDAGISel(TM, OptLevel); 153 } 154 155 /// isImmSExt20 - This method tests to see if the node is either a 32-bit 156 /// or 64-bit immediate, and if the value can be accurately represented as a 157 /// sign extension from a 20-bit value. If so, this returns true and the 158 /// immediate. 159 static bool isImmSExt20(int64_t Val, int64_t &Imm) { 160 if (Val >= -524288 && Val <= 524287) { 161 Imm = Val; 162 return true; 163 } 164 return false; 165 } 166 167 /// isImmZExt12 - This method tests to see if the node is either a 32-bit 168 /// or 64-bit immediate, and if the value can be accurately represented as a 169 /// zero extension from a 12-bit value. If so, this returns true and the 170 /// immediate. 171 static bool isImmZExt12(int64_t Val, int64_t &Imm) { 172 if (Val >= 0 && Val <= 0xFFF) { 173 Imm = Val; 174 return true; 175 } 176 return false; 177 } 178 179 /// MatchAddress - Add the specified node to the specified addressing mode, 180 /// returning true if it cannot be done. This just pattern matches for the 181 /// addressing mode. 182 bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM, 183 bool is12Bit, unsigned Depth) { 184 DebugLoc dl = N.getDebugLoc(); 185 DEBUG(errs() << "MatchAddress: "; AM.dump()); 186 // Limit recursion. 187 if (Depth > 5) 188 return MatchAddressBase(N, AM); 189 190 // FIXME: We can perform better here. If we have something like 191 // (shift (add A, imm), N), we can try to reassociate stuff and fold shift of 192 // imm into addressing mode. 193 switch (N.getOpcode()) { 194 default: break; 195 case ISD::Constant: { 196 int64_t Val = cast<ConstantSDNode>(N)->getSExtValue(); 197 int64_t Imm = 0; 198 bool Match = (is12Bit ? 199 isImmZExt12(AM.Disp + Val, Imm) : 200 isImmSExt20(AM.Disp + Val, Imm)); 201 if (Match) { 202 AM.Disp = Imm; 203 return false; 204 } 205 break; 206 } 207 208 case ISD::FrameIndex: 209 if (AM.BaseType == SystemZRRIAddressMode::RegBase && 210 AM.Base.Reg.getNode() == 0) { 211 AM.BaseType = SystemZRRIAddressMode::FrameIndexBase; 212 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex(); 213 return false; 214 } 215 break; 216 217 case ISD::SUB: { 218 // Given A-B, if A can be completely folded into the address and 219 // the index field with the index field unused, use -B as the index. 220 // This is a win if a has multiple parts that can be folded into 221 // the address. Also, this saves a mov if the base register has 222 // other uses, since it avoids a two-address sub instruction, however 223 // it costs an additional mov if the index register has other uses. 224 225 // Test if the LHS of the sub can be folded. 226 SystemZRRIAddressMode Backup = AM; 227 if (MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1)) { 228 AM = Backup; 229 break; 230 } 231 // Test if the index field is free for use. 232 if (AM.IndexReg.getNode() || AM.isRI) { 233 AM = Backup; 234 break; 235 } 236 237 // If the base is a register with multiple uses, this transformation may 238 // save a mov. Otherwise it's probably better not to do it. 239 if (AM.BaseType == SystemZRRIAddressMode::RegBase && 240 (!AM.Base.Reg.getNode() || AM.Base.Reg.getNode()->hasOneUse())) { 241 AM = Backup; 242 break; 243 } 244 245 // Ok, the transformation is legal and appears profitable. Go for it. 246 SDValue RHS = N.getNode()->getOperand(1); 247 SDValue Zero = CurDAG->getConstant(0, N.getValueType()); 248 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS); 249 AM.IndexReg = Neg; 250 251 // Insert the new nodes into the topological ordering. 252 if (Zero.getNode()->getNodeId() == -1 || 253 Zero.getNode()->getNodeId() > N.getNode()->getNodeId()) { 254 CurDAG->RepositionNode(N.getNode(), Zero.getNode()); 255 Zero.getNode()->setNodeId(N.getNode()->getNodeId()); 256 } 257 if (Neg.getNode()->getNodeId() == -1 || 258 Neg.getNode()->getNodeId() > N.getNode()->getNodeId()) { 259 CurDAG->RepositionNode(N.getNode(), Neg.getNode()); 260 Neg.getNode()->setNodeId(N.getNode()->getNodeId()); 261 } 262 return false; 263 } 264 265 case ISD::ADD: { 266 SystemZRRIAddressMode Backup = AM; 267 if (!MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1) && 268 !MatchAddress(N.getNode()->getOperand(1), AM, is12Bit, Depth+1)) 269 return false; 270 AM = Backup; 271 if (!MatchAddress(N.getNode()->getOperand(1), AM, is12Bit, Depth+1) && 272 !MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1)) 273 return false; 274 AM = Backup; 275 276 // If we couldn't fold both operands into the address at the same time, 277 // see if we can just put each operand into a register and fold at least 278 // the add. 279 if (!AM.isRI && 280 AM.BaseType == SystemZRRIAddressMode::RegBase && 281 !AM.Base.Reg.getNode() && !AM.IndexReg.getNode()) { 282 AM.Base.Reg = N.getNode()->getOperand(0); 283 AM.IndexReg = N.getNode()->getOperand(1); 284 return false; 285 } 286 break; 287 } 288 289 case ISD::OR: 290 // Handle "X | C" as "X + C" iff X is known to have C bits clear. 291 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 292 SystemZRRIAddressMode Backup = AM; 293 int64_t Offset = CN->getSExtValue(); 294 int64_t Imm = 0; 295 bool MatchOffset = (is12Bit ? 296 isImmZExt12(AM.Disp + Offset, Imm) : 297 isImmSExt20(AM.Disp + Offset, Imm)); 298 // The resultant disp must fit in 12 or 20-bits. 299 if (MatchOffset && 300 // LHS should be an addr mode. 301 !MatchAddress(N.getOperand(0), AM, is12Bit, Depth+1) && 302 // Check to see if the LHS & C is zero. 303 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) { 304 AM.Disp = Imm; 305 return false; 306 } 307 AM = Backup; 308 } 309 break; 310 } 311 312 return MatchAddressBase(N, AM); 313 } 314 315 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the 316 /// specified addressing mode without any further recursion. 317 bool SystemZDAGToDAGISel::MatchAddressBase(SDValue N, 318 SystemZRRIAddressMode &AM) { 319 // Is the base register already occupied? 320 if (AM.BaseType != SystemZRRIAddressMode::RegBase || AM.Base.Reg.getNode()) { 321 // If so, check to see if the index register is set. 322 if (AM.IndexReg.getNode() == 0 && !AM.isRI) { 323 AM.IndexReg = N; 324 return false; 325 } 326 327 // Otherwise, we cannot select it. 328 return true; 329 } 330 331 // Default, generate it as a register. 332 AM.BaseType = SystemZRRIAddressMode::RegBase; 333 AM.Base.Reg = N; 334 return false; 335 } 336 337 void SystemZDAGToDAGISel::getAddressOperandsRI(const SystemZRRIAddressMode &AM, 338 SDValue &Base, SDValue &Disp) { 339 if (AM.BaseType == SystemZRRIAddressMode::RegBase) 340 Base = AM.Base.Reg; 341 else 342 Base = CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()); 343 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i64); 344 } 345 346 void SystemZDAGToDAGISel::getAddressOperands(const SystemZRRIAddressMode &AM, 347 SDValue &Base, SDValue &Disp, 348 SDValue &Index) { 349 getAddressOperandsRI(AM, Base, Disp); 350 Index = AM.IndexReg; 351 } 352 353 /// Returns true if the address can be represented by a base register plus 354 /// an unsigned 12-bit displacement [r+imm]. 355 bool SystemZDAGToDAGISel::SelectAddrRI12Only(SDValue &Addr, 356 SDValue &Base, SDValue &Disp) { 357 return SelectAddrRI12(Addr, Base, Disp, /*is12BitOnly*/true); 358 } 359 360 bool SystemZDAGToDAGISel::SelectAddrRI12(SDValue &Addr, 361 SDValue &Base, SDValue &Disp, 362 bool is12BitOnly) { 363 SystemZRRIAddressMode AM20(/*isRI*/true), AM12(/*isRI*/true); 364 bool Done = false; 365 366 if (!Addr.hasOneUse()) { 367 unsigned Opcode = Addr.getOpcode(); 368 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) { 369 // If we are able to fold N into addressing mode, then we'll allow it even 370 // if N has multiple uses. In general, addressing computation is used as 371 // addresses by all of its uses. But watch out for CopyToReg uses, that 372 // means the address computation is liveout. It will be computed by a LA 373 // so we want to avoid computing the address twice. 374 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), 375 UE = Addr.getNode()->use_end(); UI != UE; ++UI) { 376 if (UI->getOpcode() == ISD::CopyToReg) { 377 MatchAddressBase(Addr, AM12); 378 Done = true; 379 break; 380 } 381 } 382 } 383 } 384 if (!Done && MatchAddress(Addr, AM12, /* is12Bit */ true)) 385 return false; 386 387 // Check, whether we can match stuff using 20-bit displacements 388 if (!Done && !is12BitOnly && 389 !MatchAddress(Addr, AM20, /* is12Bit */ false)) 390 if (AM12.Disp == 0 && AM20.Disp != 0) 391 return false; 392 393 DEBUG(errs() << "MatchAddress (final): "; AM12.dump()); 394 395 EVT VT = Addr.getValueType(); 396 if (AM12.BaseType == SystemZRRIAddressMode::RegBase) { 397 if (!AM12.Base.Reg.getNode()) 398 AM12.Base.Reg = CurDAG->getRegister(0, VT); 399 } 400 401 assert(AM12.IndexReg.getNode() == 0 && "Invalid reg-imm address mode!"); 402 403 getAddressOperandsRI(AM12, Base, Disp); 404 405 return true; 406 } 407 408 /// Returns true if the address can be represented by a base register plus 409 /// a signed 20-bit displacement [r+imm]. 410 bool SystemZDAGToDAGISel::SelectAddrRI(SDValue& Addr, 411 SDValue &Base, SDValue &Disp) { 412 SystemZRRIAddressMode AM(/*isRI*/true); 413 bool Done = false; 414 415 if (!Addr.hasOneUse()) { 416 unsigned Opcode = Addr.getOpcode(); 417 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) { 418 // If we are able to fold N into addressing mode, then we'll allow it even 419 // if N has multiple uses. In general, addressing computation is used as 420 // addresses by all of its uses. But watch out for CopyToReg uses, that 421 // means the address computation is liveout. It will be computed by a LA 422 // so we want to avoid computing the address twice. 423 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), 424 UE = Addr.getNode()->use_end(); UI != UE; ++UI) { 425 if (UI->getOpcode() == ISD::CopyToReg) { 426 MatchAddressBase(Addr, AM); 427 Done = true; 428 break; 429 } 430 } 431 } 432 } 433 if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false)) 434 return false; 435 436 DEBUG(errs() << "MatchAddress (final): "; AM.dump()); 437 438 EVT VT = Addr.getValueType(); 439 if (AM.BaseType == SystemZRRIAddressMode::RegBase) { 440 if (!AM.Base.Reg.getNode()) 441 AM.Base.Reg = CurDAG->getRegister(0, VT); 442 } 443 444 assert(AM.IndexReg.getNode() == 0 && "Invalid reg-imm address mode!"); 445 446 getAddressOperandsRI(AM, Base, Disp); 447 448 return true; 449 } 450 451 /// Returns true if the address can be represented by a base register plus 452 /// index register plus an unsigned 12-bit displacement [base + idx + imm]. 453 bool SystemZDAGToDAGISel::SelectAddrRRI12(SDValue Addr, 454 SDValue &Base, SDValue &Disp, SDValue &Index) { 455 SystemZRRIAddressMode AM20, AM12; 456 bool Done = false; 457 458 if (!Addr.hasOneUse()) { 459 unsigned Opcode = Addr.getOpcode(); 460 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) { 461 // If we are able to fold N into addressing mode, then we'll allow it even 462 // if N has multiple uses. In general, addressing computation is used as 463 // addresses by all of its uses. But watch out for CopyToReg uses, that 464 // means the address computation is liveout. It will be computed by a LA 465 // so we want to avoid computing the address twice. 466 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), 467 UE = Addr.getNode()->use_end(); UI != UE; ++UI) { 468 if (UI->getOpcode() == ISD::CopyToReg) { 469 MatchAddressBase(Addr, AM12); 470 Done = true; 471 break; 472 } 473 } 474 } 475 } 476 if (!Done && MatchAddress(Addr, AM12, /* is12Bit */ true)) 477 return false; 478 479 // Check, whether we can match stuff using 20-bit displacements 480 if (!Done && !MatchAddress(Addr, AM20, /* is12Bit */ false)) 481 if (AM12.Disp == 0 && AM20.Disp != 0) 482 return false; 483 484 DEBUG(errs() << "MatchAddress (final): "; AM12.dump()); 485 486 EVT VT = Addr.getValueType(); 487 if (AM12.BaseType == SystemZRRIAddressMode::RegBase) { 488 if (!AM12.Base.Reg.getNode()) 489 AM12.Base.Reg = CurDAG->getRegister(0, VT); 490 } 491 492 if (!AM12.IndexReg.getNode()) 493 AM12.IndexReg = CurDAG->getRegister(0, VT); 494 495 getAddressOperands(AM12, Base, Disp, Index); 496 497 return true; 498 } 499 500 /// Returns true if the address can be represented by a base register plus 501 /// index register plus a signed 20-bit displacement [base + idx + imm]. 502 bool SystemZDAGToDAGISel::SelectAddrRRI20(SDValue Addr, 503 SDValue &Base, SDValue &Disp, SDValue &Index) { 504 SystemZRRIAddressMode AM; 505 bool Done = false; 506 507 if (!Addr.hasOneUse()) { 508 unsigned Opcode = Addr.getOpcode(); 509 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) { 510 // If we are able to fold N into addressing mode, then we'll allow it even 511 // if N has multiple uses. In general, addressing computation is used as 512 // addresses by all of its uses. But watch out for CopyToReg uses, that 513 // means the address computation is liveout. It will be computed by a LA 514 // so we want to avoid computing the address twice. 515 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), 516 UE = Addr.getNode()->use_end(); UI != UE; ++UI) { 517 if (UI->getOpcode() == ISD::CopyToReg) { 518 MatchAddressBase(Addr, AM); 519 Done = true; 520 break; 521 } 522 } 523 } 524 } 525 if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false)) 526 return false; 527 528 DEBUG(errs() << "MatchAddress (final): "; AM.dump()); 529 530 EVT VT = Addr.getValueType(); 531 if (AM.BaseType == SystemZRRIAddressMode::RegBase) { 532 if (!AM.Base.Reg.getNode()) 533 AM.Base.Reg = CurDAG->getRegister(0, VT); 534 } 535 536 if (!AM.IndexReg.getNode()) 537 AM.IndexReg = CurDAG->getRegister(0, VT); 538 539 getAddressOperands(AM, Base, Disp, Index); 540 541 return true; 542 } 543 544 /// SelectLAAddr - it calls SelectAddr and determines if the maximal addressing 545 /// mode it matches can be cost effectively emitted as an LA/LAY instruction. 546 bool SystemZDAGToDAGISel::SelectLAAddr(SDValue Addr, 547 SDValue &Base, SDValue &Disp, SDValue &Index) { 548 SystemZRRIAddressMode AM; 549 550 if (MatchAddress(Addr, AM, false)) 551 return false; 552 553 EVT VT = Addr.getValueType(); 554 unsigned Complexity = 0; 555 if (AM.BaseType == SystemZRRIAddressMode::RegBase) 556 if (AM.Base.Reg.getNode()) 557 Complexity = 1; 558 else 559 AM.Base.Reg = CurDAG->getRegister(0, VT); 560 else if (AM.BaseType == SystemZRRIAddressMode::FrameIndexBase) 561 Complexity = 4; 562 563 if (AM.IndexReg.getNode()) 564 Complexity += 1; 565 else 566 AM.IndexReg = CurDAG->getRegister(0, VT); 567 568 if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode())) 569 Complexity += 1; 570 571 if (Complexity > 2) { 572 getAddressOperands(AM, Base, Disp, Index); 573 return true; 574 } 575 576 return false; 577 } 578 579 bool SystemZDAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N, 580 SDValue &Base, SDValue &Disp, SDValue &Index) { 581 if (ISD::isNON_EXTLoad(N.getNode()) && 582 IsLegalToFold(N, P, P, OptLevel)) 583 return SelectAddrRRI20(N.getOperand(1), Base, Disp, Index); 584 return false; 585 } 586 587 SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) { 588 EVT NVT = Node->getValueType(0); 589 DebugLoc dl = Node->getDebugLoc(); 590 unsigned Opcode = Node->getOpcode(); 591 592 // Dump information about the Node being selected 593 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n"); 594 595 // If we have a custom node, we already have selected! 596 if (Node->isMachineOpcode()) { 597 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); 598 return NULL; // Already selected. 599 } 600 601 switch (Opcode) { 602 default: break; 603 case ISD::SDIVREM: { 604 unsigned Opc, MOpc; 605 SDValue N0 = Node->getOperand(0); 606 SDValue N1 = Node->getOperand(1); 607 608 EVT ResVT; 609 bool is32Bit = false; 610 switch (NVT.getSimpleVT().SimpleTy) { 611 default: assert(0 && "Unsupported VT!"); 612 case MVT::i32: 613 Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m; 614 ResVT = MVT::v2i64; 615 is32Bit = true; 616 break; 617 case MVT::i64: 618 Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m; 619 ResVT = MVT::v2i64; 620 break; 621 } 622 623 SDValue Tmp0, Tmp1, Tmp2; 624 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2); 625 626 // Prepare the dividend 627 SDNode *Dividend; 628 if (is32Bit) 629 Dividend = CurDAG->getMachineNode(SystemZ::MOVSX64rr32, dl, MVT::i64, N0); 630 else 631 Dividend = N0.getNode(); 632 633 // Insert prepared dividend into suitable 'subreg' 634 SDNode *Tmp = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, 635 dl, ResVT); 636 Dividend = 637 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, ResVT, 638 SDValue(Tmp, 0), SDValue(Dividend, 0), 639 CurDAG->getTargetConstant(SystemZ::subreg_odd, MVT::i32)); 640 641 SDNode *Result; 642 SDValue DivVal = SDValue(Dividend, 0); 643 if (foldedLoad) { 644 SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) }; 645 Result = CurDAG->getMachineNode(MOpc, dl, ResVT, MVT::Other, 646 Ops, array_lengthof(Ops)); 647 // Update the chain. 648 ReplaceUses(N1.getValue(1), SDValue(Result, 1)); 649 } else { 650 Result = CurDAG->getMachineNode(Opc, dl, ResVT, SDValue(Dividend, 0), N1); 651 } 652 653 // Copy the division (odd subreg) result, if it is needed. 654 if (!SDValue(Node, 0).use_empty()) { 655 unsigned SubRegIdx = (is32Bit ? 656 SystemZ::subreg_odd32 : SystemZ::subreg_odd); 657 SDNode *Div = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, 658 dl, NVT, 659 SDValue(Result, 0), 660 CurDAG->getTargetConstant(SubRegIdx, 661 MVT::i32)); 662 663 ReplaceUses(SDValue(Node, 0), SDValue(Div, 0)); 664 DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n"); 665 } 666 667 // Copy the remainder (even subreg) result, if it is needed. 668 if (!SDValue(Node, 1).use_empty()) { 669 unsigned SubRegIdx = (is32Bit ? 670 SystemZ::subreg_32bit : SystemZ::subreg_even); 671 SDNode *Rem = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, 672 dl, NVT, 673 SDValue(Result, 0), 674 CurDAG->getTargetConstant(SubRegIdx, 675 MVT::i32)); 676 677 ReplaceUses(SDValue(Node, 1), SDValue(Rem, 0)); 678 DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n"); 679 } 680 681 return NULL; 682 } 683 case ISD::UDIVREM: { 684 unsigned Opc, MOpc, ClrOpc; 685 SDValue N0 = Node->getOperand(0); 686 SDValue N1 = Node->getOperand(1); 687 EVT ResVT; 688 689 bool is32Bit = false; 690 switch (NVT.getSimpleVT().SimpleTy) { 691 default: assert(0 && "Unsupported VT!"); 692 case MVT::i32: 693 Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m; 694 ClrOpc = SystemZ::MOV64Pr0_even; 695 ResVT = MVT::v2i32; 696 is32Bit = true; 697 break; 698 case MVT::i64: 699 Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m; 700 ClrOpc = SystemZ::MOV128r0_even; 701 ResVT = MVT::v2i64; 702 break; 703 } 704 705 SDValue Tmp0, Tmp1, Tmp2; 706 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2); 707 708 // Prepare the dividend 709 SDNode *Dividend = N0.getNode(); 710 711 // Insert prepared dividend into suitable 'subreg' 712 SDNode *Tmp = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, 713 dl, ResVT); 714 { 715 unsigned SubRegIdx = (is32Bit ? 716 SystemZ::subreg_odd32 : SystemZ::subreg_odd); 717 Dividend = 718 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, ResVT, 719 SDValue(Tmp, 0), SDValue(Dividend, 0), 720 CurDAG->getTargetConstant(SubRegIdx, MVT::i32)); 721 } 722 723 // Zero out even subreg 724 Dividend = CurDAG->getMachineNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0)); 725 726 SDValue DivVal = SDValue(Dividend, 0); 727 SDNode *Result; 728 if (foldedLoad) { 729 SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) }; 730 Result = CurDAG->getMachineNode(MOpc, dl, ResVT, MVT::Other, 731 Ops, array_lengthof(Ops)); 732 // Update the chain. 733 ReplaceUses(N1.getValue(1), SDValue(Result, 1)); 734 } else { 735 Result = CurDAG->getMachineNode(Opc, dl, ResVT, DivVal, N1); 736 } 737 738 // Copy the division (odd subreg) result, if it is needed. 739 if (!SDValue(Node, 0).use_empty()) { 740 unsigned SubRegIdx = (is32Bit ? 741 SystemZ::subreg_odd32 : SystemZ::subreg_odd); 742 SDNode *Div = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, 743 dl, NVT, 744 SDValue(Result, 0), 745 CurDAG->getTargetConstant(SubRegIdx, 746 MVT::i32)); 747 ReplaceUses(SDValue(Node, 0), SDValue(Div, 0)); 748 DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n"); 749 } 750 751 // Copy the remainder (even subreg) result, if it is needed. 752 if (!SDValue(Node, 1).use_empty()) { 753 unsigned SubRegIdx = (is32Bit ? 754 SystemZ::subreg_32bit : SystemZ::subreg_even); 755 SDNode *Rem = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, 756 dl, NVT, 757 SDValue(Result, 0), 758 CurDAG->getTargetConstant(SubRegIdx, 759 MVT::i32)); 760 ReplaceUses(SDValue(Node, 1), SDValue(Rem, 0)); 761 DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n"); 762 } 763 764 return NULL; 765 } 766 } 767 768 // Select the default instruction 769 SDNode *ResNode = SelectCode(Node); 770 771 DEBUG(errs() << "=> "; 772 if (ResNode == NULL || ResNode == Node) 773 Node->dump(CurDAG); 774 else 775 ResNode->dump(CurDAG); 776 errs() << "\n"; 777 ); 778 return ResNode; 779 } 780
