| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineLoadStoreAlloca.cpp | 583 auto EltSize = DL.getTypeAllocSize(ET);
604 Offset += EltSize;
[all...] |
| InstructionCombining.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| Analysis.cpp | 103 uint64_t EltSize = DL.getTypeAllocSize(EltTy);
106 StartingOffset + i * EltSize);
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 612 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
614 (EltSize == 1 || EltSize == 2 || EltSize == 4));
626 for (unsigned i = 1; i != EltSize; ++i)
630 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
632 for (unsigned j = 0; j != EltSize; ++j)
657 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
659 assert(isSplatShuffleMask(SVOp, EltSize));
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIInstrInfo.cpp | 238 unsigned EltSize;
240 EltSize = getOpRegClass(LdSt, 0)->getSize() / 2;
244 EltSize = getOpRegClass(LdSt, Data0Idx)->getSize();
248 EltSize *= 64;
253 Offset = EltSize * Offset0;
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| PPCISelDAGToDAG.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypes.cpp | [all...] |
| LegalizeDAG.cpp | 344 unsigned EltSize = EltVT.getSizeInBits()/8;
346 DAG.getConstant(EltSize, dl, IdxVT));
[all...] |
| SelectionDAG.cpp | 137 unsigned EltSize = N->getValueType(0).getVectorElementType().getSizeInBits();
139 if (CN->getAPIntValue().countTrailingOnes() < EltSize)
142 if (CFPN->getValueAPF().bitcastToAPInt().countTrailingOnes() < EltSize)
176 unsigned EltSize = N->getValueType(0).getVectorElementType().getSizeInBits();
178 if (CN->getAPIntValue().countTrailingZeros() < EltSize)
181 if (CFPN->getValueAPF().bitcastToAPInt().countTrailingZeros() < EltSize)
[all...] |
| /external/clang/lib/CodeGen/ |
| CGExprScalar.cpp | [all...] |
| TargetInfo.cpp | [all...] |
| CodeGenFunction.cpp | [all...] |
| CGExpr.cpp | [all...] |
| /toolchain/binutils/binutils-2.27/bfd/ |
| bfd-in2.h | 492 #define bfd_read(BUF, ELTSIZE, NITEMS, ABFD) \
494 bfd_bread ((BUF), (ELTSIZE) * (NITEMS), (ABFD)))
495 #define bfd_write(BUF, ELTSIZE, NITEMS, ABFD) \
497 bfd_bwrite ((BUF), (ELTSIZE) * (NITEMS), (ABFD)))
499 #define bfd_read(BUF, ELTSIZE, NITEMS, ABFD) \
501 bfd_bread ((BUF), (ELTSIZE) * (NITEMS), (ABFD)))
502 #define bfd_write(BUF, ELTSIZE, NITEMS, ABFD) \
504 bfd_bwrite ((BUF), (ELTSIZE) * (NITEMS), (ABFD)))
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Transforms/InstCombine/ |
| InstructionCombining.cpp | 775 uint64_t EltSize = TD->getTypeAllocSize(AT->getElementType());
776 assert(EltSize && "Cannot index into a zero-sized array");
777 NewIndices.push_back(ConstantInt::get(IntPtrTy,Offset/EltSize));
778 Offset %= EltSize;
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | 667 unsigned EltSize = EltVT.getSizeInBits()/8;
668 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
[all...] |
| LegalizeTypes.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 855 unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
863 EltSize, !Subtarget.isLittle()) ||
864 (SplatBitSize != EltSize) ||
865 (SplatValue.getZExtValue() >= EltSize))
[all...] |
| /external/clang/lib/AST/ |
| ExprConstant.cpp | [all...] |
| /prebuilts/go/darwin-x86/src/reflect/ |
| value.go | [all...] |
| /prebuilts/go/linux-x86/src/reflect/ |
| value.go | [all...] |
| /external/llvm/lib/IR/ |
| Constants.cpp | [all...] |
