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  /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
MBlazeISelLowering.cpp 75 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Expand);
98 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
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  /art/compiler/jni/
jni_compiler_test.cc 1971 jint i16 = bit_cast<jint, jfloat>(f6); local
2041 jint i16 = bit_cast<jint, jfloat>(f6); local
2110 jint i16 = bit_cast<jint, jfloat>(f6); local
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  /external/icu/icu4c/source/test/cintltst/
creststn.c 2879 int32_t length16, length8, i16, i8; local
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  /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
PPCISelLowering.cpp 85 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
94 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
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  /external/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 436 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
443 setIndexedLoadAction(im, MVT::i16, Legal);
450 setIndexedStoreAction(im, MVT::i16, Legal);
563 // i8 and i16 vector elements also need promotion to i32 for v8i8 or v8i16
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AArch64ISelDAGToDAG.cpp 378 else if (!IsLoadStore && SrcVT == MVT::i16)
390 else if (!IsLoadStore && SrcVT == MVT::i16)
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  /external/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 526 if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16))
763 DAG.getValueType(MVT::i16));
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  /external/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 88 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
99 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
106 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
320 setOperationAction(ISD::VAARG, MVT::i16, Promote);
321 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
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  /prebuilts/devtools/tools/lib/
commons-compress-1.0.jar 
  /prebuilts/tools/common/commons-compress/
commons-compress-1.0.jar 
  /prebuilts/tools/common/m2/repository/org/apache/commons/commons-compress/1.0/
commons-compress-1.0.jar 
  /external/flatbuffers/tests/
monster_test_generated.js 2013 MyGame.Example.TypeAliases.prototype.i16 = function() { method in class:MyGame.Example.TypeAliases
    [all...]
test.cpp     [all...]
  /external/libmtp/src/
libmtp.c     [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonISelDAGToDAG.cpp 262 case MVT::i16:
553 case MVT::i16:
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  /external/llvm/lib/Target/Lanai/
LanaiISelLowering.cpp 118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
363 // Promote i8/i16 args to i32
364 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
    [all...]
  /prebuilts/tools/common/m2/repository/com/fasterxml/jackson/dataformat/jackson-dataformat-cbor/2.6.6/
jackson-dataformat-cbor-2.6.6.jar 
  /external/llvm/lib/Target/ARM/
ARMISelLowering.cpp     [all...]
  /external/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 107 for (auto T : {MVT::i1, MVT::i8, MVT::i16, MVT::i32})
  /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
TargetLowering.cpp 373 if (RetVT == MVT::i16)
384 if (RetVT == MVT::i16)
416 if (RetVT == MVT::i16)
427 if (RetVT == MVT::i16)
693 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
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  /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
SystemZISelDAGToDAG.cpp 108 /// i16.
110 return CurDAG->getTargetConstant(Imm, MVT::i16);
  /external/swiftshader/third_party/LLVM/lib/Target/ARM/
ARMISelLowering.cpp 538 setIndexedLoadAction(im, MVT::i16, Legal);
542 setIndexedStoreAction(im, MVT::i16, Legal);
662 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
    [all...]
  /external/libhevc/common/arm/
ihevc_inter_pred_filters_luma_vert.s 474 vadd.i16 q0,q0,q1 @mul_res1 = vaddq_u16(mul_res1, mul_res2)@
    [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
FastISel.cpp 182 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
    [all...]
  /prebuilts/ndk/r16/sources/third_party/shaderc/third_party/glslang/glslang/MachineIndependent/
Intermediate.cpp     [all...]

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