| /external/llvm/lib/Target/AArch64/ |
| AArch64SystemOperands.td | 100 def : DC<"CIVAC", 0b01, 0b011, 0b0111, 0b1110, 0b001>;
101 def : DC<"CISW", 0b01, 0b000, 0b0111, 0b1110, 0b010>;
316 def : ROSysReg<"DBGAUTHSTATUS_EL1", 0b10, 0b000, 0b0111, 0b1110, 0b110>;
361 def : ROSysReg<"CNTPCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b001>;
362 def : ROSysReg<"CNTVCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b010>;
380 def : ROSysReg<"TRCIDR6", 0b10, 0b001, 0b0000, 0b1110, 0b111>;
387 def : ROSysReg<"TRCAUTHSTATUS", 0b10, 0b001, 0b0111, 0b1110, 0b110>;
401 def : ROSysReg<"TRCCIDR2", 0b10, 0b001, 0b0111, 0b1110, 0b111>;
477 def : RWSysReg<"DBGBVR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b100>;
493 def : RWSysReg<"DBGBCR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b101>
[all...] |
| /external/libvpx/libvpx/vp9/common/ |
| vp9_common_data.c | 232 { 15, 14 }, // 4X8 - {0b1111, 0b1110}
233 { 14, 15 }, // 8X4 - {0b1110, 0b1111}
234 { 14, 14 }, // 8X8 - {0b1110, 0b1110}
235 { 14, 12 }, // 8X16 - {0b1110, 0b1100}
236 { 12, 14 }, // 16X8 - {0b1100, 0b1110}
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrAliases.td | 281 defm : int_cond_alias<"pos", 0b1110>;
308 defm : fp_cond_alias<"ule", 0b1110>;
331 defm : cp_cond_alias<"013", 0b1110>;
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfoV5.td | 161 let IClass = 0b1110;
227 let IClass = 0b1110;
705 let IClass = 0b1110;
738 let IClass = 0b1110;
[all...] |
| HexagonInstrInfoV3.td | 207 let IClass = 0b1110;
237 let IClass = 0b1110;
|
| HexagonIsetDx.td | 228 let Inst{12-9} = 0b1110;
674 let Inst{12-9} = 0b1110;
|
| HexagonInstrInfo.td | 612 let Inst{27-24} = 0b1110;
[all...] |
| HexagonInstrEnc.td | [all...] |
| HexagonInstrInfoV4.td | 437 def L4_loadrd_ap : T_LD_abs_set <"memd", DoubleRegs, 0b1110>;
495 def L4_loadrd_ur : T_LoadAbsReg<"memd", "LDrid", DoubleRegs, 0b1110>;
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMInstrNEON.td | [all...] |
| ARMInstrThumb2.td | [all...] |
| ARMInstrVFP.td | [all...] |
| ARMInstrInfo.td | [all...] |
| ARMInstrThumb.td | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMInstrNEON.td | [all...] |
| ARMInstrVFP.td | 799 def VTOSHS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 0,
817 def VTOSLS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 1,
835 def VTOSHD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 0,
845 def VTOSLD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 1,
[all...] |
| ARMInstrThumb2.td | [all...] |
| ARMInstrInfo.td | [all...] |
| /external/llvm/lib/Target/Lanai/ |
| LanaiInstrFormats.td | 334 let Opcode = 0b1110;
362 let Opcode = 0b1110;
397 let Opcode = 0b1110;
|
| /external/llvm/lib/Target/Mips/ |
| MipsMSAInstrFormats.td | 36 let Inst{22-19} = 0b1110;
|
| MicroMips64r6InstrInfo.td | 65 class LWU_MM64R6_ENC : POOL32C_2R_OFFSET12_FM_MMR6<"lwu", 0b1110>;
|
| MipsMSAInstrInfo.td | 711 class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>
[all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCCodeEmitter.cpp | 260 // 0b1110 =0xE bits are masked off and down shifted by 1 bit.
|
| /toolchain/binutils/binutils-2.27/include/opcode/ |
| spu-insns.h | 59 since 0x700 -> 11'b11100000000, this means opcode is 4'b1110, and other 7bits are defined as 7'b0000000.
|
| /external/valgrind/none/tests/ppc64/ |
| ppc64_helpers.h | [all...] |
