1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <dram.h> 8 #include <plat_private.h> 9 #include <rk3399_def.h> 10 #include <secure.h> 11 #include <soc.h> 12 13 __pmusramdata struct rk3399_sdram_params sdram_config; 14 15 void dram_init(void) 16 { 17 uint32_t os_reg2_val, i; 18 19 os_reg2_val = mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)); 20 sdram_config.dramtype = SYS_REG_DEC_DDRTYPE(os_reg2_val); 21 sdram_config.num_channels = SYS_REG_DEC_NUM_CH(os_reg2_val); 22 sdram_config.stride = (mmio_read_32(SGRF_BASE + SGRF_SOC_CON3_7(4)) >> 23 10) & 0x1f; 24 25 for (i = 0; i < 2; i++) { 26 struct rk3399_sdram_channel *ch = &sdram_config.ch[i]; 27 struct rk3399_msch_timings *noc = &ch->noc_timings; 28 29 if (!(SYS_REG_DEC_CHINFO(os_reg2_val, i))) 30 continue; 31 32 ch->rank = SYS_REG_DEC_RANK(os_reg2_val, i); 33 ch->col = SYS_REG_DEC_COL(os_reg2_val, i); 34 ch->bk = SYS_REG_DEC_BK(os_reg2_val, i); 35 ch->bw = SYS_REG_DEC_BW(os_reg2_val, i); 36 ch->dbw = SYS_REG_DEC_DBW(os_reg2_val, i); 37 ch->row_3_4 = SYS_REG_DEC_ROW_3_4(os_reg2_val, i); 38 ch->cs0_row = SYS_REG_DEC_CS0_ROW(os_reg2_val, i); 39 ch->cs1_row = SYS_REG_DEC_CS1_ROW(os_reg2_val, i); 40 ch->ddrconfig = mmio_read_32(MSCH_BASE(i) + MSCH_DEVICECONF); 41 42 noc->ddrtiminga0.d32 = mmio_read_32(MSCH_BASE(i) + 43 MSCH_DDRTIMINGA0); 44 noc->ddrtimingb0.d32 = mmio_read_32(MSCH_BASE(i) + 45 MSCH_DDRTIMINGB0); 46 noc->ddrtimingc0.d32 = mmio_read_32(MSCH_BASE(i) + 47 MSCH_DDRTIMINGC0); 48 noc->devtodev0.d32 = mmio_read_32(MSCH_BASE(i) + 49 MSCH_DEVTODEV0); 50 noc->ddrmode.d32 = mmio_read_32(MSCH_BASE(i) + MSCH_DDRMODE); 51 noc->agingx0 = mmio_read_32(MSCH_BASE(i) + MSCH_AGINGX0); 52 } 53 } 54
