1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief SI DAG Lowering interface definition 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 16 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 17 18 #include "AMDGPUISelLowering.h" 19 #include "SIInstrInfo.h" 20 21 namespace llvm { 22 23 class SITargetLowering final : public AMDGPUTargetLowering { 24 SDValue LowerParameterPtr(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, 25 unsigned Offset) const; 26 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, 27 SDValue Chain, unsigned Offset, bool Signed) const; 28 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 29 SelectionDAG &DAG) const override; 30 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op, 31 MVT VT, unsigned Offset) const; 32 33 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 34 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 35 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 36 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const; 37 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 38 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 39 SDValue LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const; 40 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const; 41 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const; 42 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const; 43 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const; 44 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 45 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const; 46 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 47 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 48 49 SDValue getSegmentAperture(unsigned AS, SelectionDAG &DAG) const; 50 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const; 51 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const; 52 53 void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; 54 55 SDValue performUCharToFloatCombine(SDNode *N, 56 DAGCombinerInfo &DCI) const; 57 SDValue performSHLPtrCombine(SDNode *N, 58 unsigned AS, 59 DAGCombinerInfo &DCI) const; 60 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const; 61 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const; 62 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const; 63 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const; 64 65 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const; 66 67 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; 68 69 bool isLegalFlatAddressingMode(const AddrMode &AM) const; 70 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const; 71 72 bool isCFIntrinsic(const SDNode *Intr) const; 73 74 void createDebuggerPrologueStackObjects(MachineFunction &MF) const; 75 public: 76 SITargetLowering(const TargetMachine &tm, const SISubtarget &STI); 77 78 const SISubtarget *getSubtarget() const; 79 80 bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 81 unsigned IntrinsicID) const override; 82 83 bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/, 84 EVT /*VT*/) const override; 85 86 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 87 unsigned AS) const override; 88 89 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, 90 unsigned Align, 91 bool *IsFast) const override; 92 93 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 94 unsigned SrcAlign, bool IsMemset, 95 bool ZeroMemset, 96 bool MemcpyStrSrc, 97 MachineFunction &MF) const override; 98 99 bool isMemOpUniform(const SDNode *N) const; 100 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 101 102 TargetLoweringBase::LegalizeTypeAction 103 getPreferredVectorAction(EVT VT) const override; 104 105 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 106 Type *Ty) const override; 107 108 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override; 109 110 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 111 112 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 113 bool isVarArg, 114 const SmallVectorImpl<ISD::InputArg> &Ins, 115 const SDLoc &DL, SelectionDAG &DAG, 116 SmallVectorImpl<SDValue> &InVals) const override; 117 118 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 119 const SmallVectorImpl<ISD::OutputArg> &Outs, 120 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 121 SelectionDAG &DAG) const override; 122 123 unsigned getRegisterByName(const char* RegName, EVT VT, 124 SelectionDAG &DAG) const override; 125 126 MachineBasicBlock *splitKillBlock(MachineInstr &MI, 127 MachineBasicBlock *BB) const; 128 129 MachineBasicBlock * 130 EmitInstrWithCustomInserter(MachineInstr &MI, 131 MachineBasicBlock *BB) const override; 132 bool enableAggressiveFMAFusion(EVT VT) const override; 133 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 134 EVT VT) const override; 135 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override; 136 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 137 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 138 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 139 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override; 140 void AdjustInstrPostInstrSelection(MachineInstr &MI, 141 SDNode *Node) const override; 142 143 int32_t analyzeImmediate(const SDNode *N) const; 144 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, 145 unsigned Reg, EVT VT) const override; 146 void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const; 147 148 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, 149 SDValue Ptr) const; 150 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, 151 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const; 152 std::pair<unsigned, const TargetRegisterClass *> 153 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 154 StringRef Constraint, MVT VT) const override; 155 ConstraintType getConstraintType(StringRef Constraint) const override; 156 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, 157 SDValue V) const; 158 }; 159 160 } // End namespace llvm 161 162 #endif 163
