1 //===-- LanaiISelLowering.h - Lanai DAG Lowering Interface -....-*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Lanai uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H 16 #define LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H 17 18 #include "Lanai.h" 19 #include "LanaiRegisterInfo.h" 20 #include "llvm/CodeGen/SelectionDAG.h" 21 #include "llvm/Target/TargetLowering.h" 22 23 namespace llvm { 24 namespace LanaiISD { 25 enum { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 28 ADJDYNALLOC, 29 30 // Return with a flag operand. Operand 0 is the chain operand. 31 RET_FLAG, 32 33 // CALL - These operations represent an abstract call instruction, which 34 // includes a bunch of information. 35 CALL, 36 37 // SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 38 // is condition code and operand 4 is flag operand. 39 SELECT_CC, 40 41 // SETCC - Store the conditional code to a register. 42 SETCC, 43 44 // SET_FLAG - Set flag compare. 45 SET_FLAG, 46 47 // SUBBF - Subtract with borrow that sets flags. 48 SUBBF, 49 50 // BR_CC - Used to glue together a conditional branch and comparison 51 BR_CC, 52 53 // Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, 54 // and TargetGlobalAddress. 55 Wrapper, 56 57 // Get the Higher/Lower 16 bits from a 32-bit immediate. 58 HI, 59 LO, 60 61 // Small 21-bit immediate in global memory. 62 SMALL 63 }; 64 } // namespace LanaiISD 65 66 class LanaiSubtarget; 67 68 class LanaiTargetLowering : public TargetLowering { 69 public: 70 LanaiTargetLowering(const TargetMachine &TM, const LanaiSubtarget &STI); 71 72 // LowerOperation - Provide custom lowering hooks for some operations. 73 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 74 75 // getTargetNodeName - This method returns the name of a target specific 76 // DAG node. 77 const char *getTargetNodeName(unsigned Opcode) const override; 78 79 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 80 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 81 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 82 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 83 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 84 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 85 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 86 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 87 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 88 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 89 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 90 SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) const; 91 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; 92 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 93 94 unsigned getRegisterByName(const char *RegName, EVT VT, 95 SelectionDAG &DAG) const override; 96 std::pair<unsigned, const TargetRegisterClass *> 97 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 98 StringRef Constraint, MVT VT) const override; 99 ConstraintWeight 100 getSingleConstraintMatchWeight(AsmOperandInfo &Info, 101 const char *Constraint) const override; 102 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 103 std::vector<SDValue> &Ops, 104 SelectionDAG &DAG) const override; 105 106 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 107 108 private: 109 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee, 110 CallingConv::ID CallConv, bool IsVarArg, 111 bool IsTailCall, 112 const SmallVectorImpl<ISD::OutputArg> &Outs, 113 const SmallVectorImpl<SDValue> &OutVals, 114 const SmallVectorImpl<ISD::InputArg> &Ins, 115 const SDLoc &dl, SelectionDAG &DAG, 116 SmallVectorImpl<SDValue> &InVals) const; 117 118 SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, 119 bool IsVarArg, 120 const SmallVectorImpl<ISD::InputArg> &Ins, 121 const SDLoc &DL, SelectionDAG &DAG, 122 SmallVectorImpl<SDValue> &InVals) const; 123 124 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 125 CallingConv::ID CallConv, bool IsVarArg, 126 const SmallVectorImpl<ISD::InputArg> &Ins, 127 const SDLoc &DL, SelectionDAG &DAG, 128 SmallVectorImpl<SDValue> &InVals) const; 129 130 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 131 SmallVectorImpl<SDValue> &InVals) const override; 132 133 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 134 bool IsVarArg, 135 const SmallVectorImpl<ISD::InputArg> &Ins, 136 const SDLoc &DL, SelectionDAG &DAG, 137 SmallVectorImpl<SDValue> &InVals) const override; 138 139 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 140 const SmallVectorImpl<ISD::OutputArg> &Outs, 141 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 142 SelectionDAG &DAG) const override; 143 144 const LanaiRegisterInfo *TRI; 145 }; 146 } // namespace llvm 147 148 #endif // LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H 149
