1 //===- LanaiInstrInfo.h - Lanai Instruction Information ---------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Lanai implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H 15 #define LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H 16 17 #include "LanaiRegisterInfo.h" 18 #include "llvm/Target/TargetInstrInfo.h" 19 20 #define GET_INSTRINFO_HEADER 21 #include "LanaiGenInstrInfo.inc" 22 23 namespace llvm { 24 25 class LanaiInstrInfo : public LanaiGenInstrInfo { 26 const LanaiRegisterInfo RegisterInfo; 27 28 public: 29 LanaiInstrInfo(); 30 31 // getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 32 // such, whenever a client has an instance of instruction info, it should 33 // always be able to get register info as well (through this method). 34 virtual const LanaiRegisterInfo &getRegisterInfo() const { 35 return RegisterInfo; 36 } 37 38 bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, 39 AliasAnalysis *AA) const override; 40 41 unsigned isLoadFromStackSlot(const MachineInstr &MI, 42 int &FrameIndex) const override; 43 44 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, 45 int &FrameIndex) const override; 46 47 unsigned isStoreToStackSlot(const MachineInstr &MI, 48 int &FrameIndex) const override; 49 50 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, 51 const DebugLoc &DL, unsigned DestinationRegister, 52 unsigned SourceRegister, bool KillSource) const override; 53 54 void 55 storeRegToStackSlot(MachineBasicBlock &MBB, 56 MachineBasicBlock::iterator Position, 57 unsigned SourceRegister, bool IsKill, int FrameIndex, 58 const TargetRegisterClass *RegisterClass, 59 const TargetRegisterInfo *RegisterInfo) const override; 60 61 void 62 loadRegFromStackSlot(MachineBasicBlock &MBB, 63 MachineBasicBlock::iterator Position, 64 unsigned DestinationRegister, int FrameIndex, 65 const TargetRegisterClass *RegisterClass, 66 const TargetRegisterInfo *RegisterInfo) const override; 67 68 bool expandPostRAPseudo(MachineInstr &MI) const override; 69 70 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, 71 int64_t &Offset, 72 const TargetRegisterInfo *TRI) const override; 73 74 bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg, 75 int64_t &Offset, unsigned &Width, 76 const TargetRegisterInfo *TRI) const; 77 78 std::pair<unsigned, unsigned> 79 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 80 81 ArrayRef<std::pair<unsigned, const char *>> 82 getSerializableDirectMachineOperandTargetFlags() const override; 83 84 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock, 85 MachineBasicBlock *&FalseBlock, 86 SmallVectorImpl<MachineOperand> &Condition, 87 bool AllowModify) const override; 88 89 unsigned RemoveBranch(MachineBasicBlock &MBB) const override; 90 91 // For a comparison instruction, return the source registers in SrcReg and 92 // SrcReg2 if having two register operands, and the value it compares against 93 // in CmpValue. Return true if the comparison instruction can be analyzed. 94 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, 95 unsigned &SrcReg2, int &CmpMask, 96 int &CmpValue) const override; 97 98 // See if the comparison instruction can be converted into something more 99 // efficient. E.g., on Lanai register-register instructions can set the flag 100 // register, obviating the need for a separate compare. 101 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, 102 unsigned SrcReg2, int CmpMask, int CmpValue, 103 const MachineRegisterInfo *MRI) const override; 104 105 // Analyze the given select instruction, returning true if it cannot be 106 // understood. It is assumed that MI->isSelect() is true. 107 // 108 // When successful, return the controlling condition and the operands that 109 // determine the true and false result values. 110 // 111 // Result = SELECT Cond, TrueOp, FalseOp 112 // 113 // Lanai can optimize certain select instructions, for example by predicating 114 // the instruction defining one of the operands and sets Optimizable to true. 115 bool analyzeSelect(const MachineInstr &MI, 116 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp, 117 unsigned &FalseOp, bool &Optimizable) const override; 118 119 // Given a select instruction that was understood by analyzeSelect and 120 // returned Optimizable = true, attempt to optimize MI by merging it with one 121 // of its operands. Returns NULL on failure. 122 // 123 // When successful, returns the new select instruction. The client is 124 // responsible for deleting MI. 125 // 126 // If both sides of the select can be optimized, the TrueOp is modifed. 127 // PreferFalse is not used. 128 MachineInstr *optimizeSelect(MachineInstr &MI, 129 SmallPtrSetImpl<MachineInstr *> &SeenMIs, 130 bool PreferFalse) const override; 131 132 bool ReverseBranchCondition( 133 SmallVectorImpl<MachineOperand> &Condition) const override; 134 135 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock, 136 MachineBasicBlock *FalseBlock, 137 ArrayRef<MachineOperand> Condition, 138 const DebugLoc &DL) const override; 139 }; 140 141 static inline bool isSPLSOpcode(unsigned Opcode) { 142 switch (Opcode) { 143 case Lanai::LDBs_RI: 144 case Lanai::LDBz_RI: 145 case Lanai::LDHs_RI: 146 case Lanai::LDHz_RI: 147 case Lanai::STB_RI: 148 case Lanai::STH_RI: 149 return true; 150 default: 151 return false; 152 } 153 } 154 155 static inline bool isRMOpcode(unsigned Opcode) { 156 switch (Opcode) { 157 case Lanai::LDW_RI: 158 case Lanai::SW_RI: 159 return true; 160 default: 161 return false; 162 } 163 } 164 165 static inline bool isRRMOpcode(unsigned Opcode) { 166 switch (Opcode) { 167 case Lanai::LDBs_RR: 168 case Lanai::LDBz_RR: 169 case Lanai::LDHs_RR: 170 case Lanai::LDHz_RR: 171 case Lanai::LDWz_RR: 172 case Lanai::LDW_RR: 173 case Lanai::STB_RR: 174 case Lanai::STH_RR: 175 case Lanai::SW_RR: 176 return true; 177 default: 178 return false; 179 } 180 } 181 182 } // namespace llvm 183 184 #endif // LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H 185
