1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains small standalone helper functions and enum definitions for 11 // the X86 target useful for the compiler back-end and the MC libraries. 12 // As such, it deliberately does not include references to LLVM core 13 // code gen types, passes, etc.. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H 18 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H 19 20 #include "X86MCTargetDesc.h" 21 #include "llvm/MC/MCInstrDesc.h" 22 #include "llvm/Support/DataTypes.h" 23 #include "llvm/Support/ErrorHandling.h" 24 25 namespace llvm { 26 27 namespace X86 { 28 // Enums for memory operand decoding. Each memory operand is represented with 29 // a 5 operand sequence in the form: 30 // [BaseReg, ScaleAmt, IndexReg, Disp, Segment] 31 // These enums help decode this. 32 enum { 33 AddrBaseReg = 0, 34 AddrScaleAmt = 1, 35 AddrIndexReg = 2, 36 AddrDisp = 3, 37 38 /// AddrSegmentReg - The operand # of the segment in the memory operand. 39 AddrSegmentReg = 4, 40 41 /// AddrNumOperands - Total number of operands in a memory reference. 42 AddrNumOperands = 5 43 }; 44 45 /// AVX512 static rounding constants. These need to match the values in 46 /// avx512fintrin.h. 47 enum STATIC_ROUNDING { 48 TO_NEAREST_INT = 0, 49 TO_NEG_INF = 1, 50 TO_POS_INF = 2, 51 TO_ZERO = 3, 52 CUR_DIRECTION = 4 53 }; 54 } // end namespace X86; 55 56 /// X86II - This namespace holds all of the target specific flags that 57 /// instruction info tracks. 58 /// 59 namespace X86II { 60 /// Target Operand Flag enum. 61 enum TOF { 62 //===------------------------------------------------------------------===// 63 // X86 Specific MachineOperand flags. 64 65 MO_NO_FLAG, 66 67 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 68 /// relocation of: 69 /// SYMBOL_LABEL + [. - PICBASELABEL] 70 MO_GOT_ABSOLUTE_ADDRESS, 71 72 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 73 /// immediate should get the value of the symbol minus the PIC base label: 74 /// SYMBOL_LABEL - PICBASELABEL 75 MO_PIC_BASE_OFFSET, 76 77 /// MO_GOT - On a symbol operand this indicates that the immediate is the 78 /// offset to the GOT entry for the symbol name from the base of the GOT. 79 /// 80 /// See the X86-64 ELF ABI supplement for more details. 81 /// SYMBOL_LABEL @GOT 82 MO_GOT, 83 84 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 85 /// the offset to the location of the symbol name from the base of the GOT. 86 /// 87 /// See the X86-64 ELF ABI supplement for more details. 88 /// SYMBOL_LABEL @GOTOFF 89 MO_GOTOFF, 90 91 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 92 /// offset to the GOT entry for the symbol name from the current code 93 /// location. 94 /// 95 /// See the X86-64 ELF ABI supplement for more details. 96 /// SYMBOL_LABEL @GOTPCREL 97 MO_GOTPCREL, 98 99 /// MO_PLT - On a symbol operand this indicates that the immediate is 100 /// offset to the PLT entry of symbol name from the current code location. 101 /// 102 /// See the X86-64 ELF ABI supplement for more details. 103 /// SYMBOL_LABEL @PLT 104 MO_PLT, 105 106 /// MO_TLSGD - On a symbol operand this indicates that the immediate is 107 /// the offset of the GOT entry with the TLS index structure that contains 108 /// the module number and variable offset for the symbol. Used in the 109 /// general dynamic TLS access model. 110 /// 111 /// See 'ELF Handling for Thread-Local Storage' for more details. 112 /// SYMBOL_LABEL @TLSGD 113 MO_TLSGD, 114 115 /// MO_TLSLD - On a symbol operand this indicates that the immediate is 116 /// the offset of the GOT entry with the TLS index for the module that 117 /// contains the symbol. When this index is passed to a call to 118 /// __tls_get_addr, the function will return the base address of the TLS 119 /// block for the symbol. Used in the x86-64 local dynamic TLS access model. 120 /// 121 /// See 'ELF Handling for Thread-Local Storage' for more details. 122 /// SYMBOL_LABEL @TLSLD 123 MO_TLSLD, 124 125 /// MO_TLSLDM - On a symbol operand this indicates that the immediate is 126 /// the offset of the GOT entry with the TLS index for the module that 127 /// contains the symbol. When this index is passed to a call to 128 /// ___tls_get_addr, the function will return the base address of the TLS 129 /// block for the symbol. Used in the IA32 local dynamic TLS access model. 130 /// 131 /// See 'ELF Handling for Thread-Local Storage' for more details. 132 /// SYMBOL_LABEL @TLSLDM 133 MO_TLSLDM, 134 135 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 136 /// the offset of the GOT entry with the thread-pointer offset for the 137 /// symbol. Used in the x86-64 initial exec TLS access model. 138 /// 139 /// See 'ELF Handling for Thread-Local Storage' for more details. 140 /// SYMBOL_LABEL @GOTTPOFF 141 MO_GOTTPOFF, 142 143 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 144 /// the absolute address of the GOT entry with the negative thread-pointer 145 /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access 146 /// model. 147 /// 148 /// See 'ELF Handling for Thread-Local Storage' for more details. 149 /// SYMBOL_LABEL @INDNTPOFF 150 MO_INDNTPOFF, 151 152 /// MO_TPOFF - On a symbol operand this indicates that the immediate is 153 /// the thread-pointer offset for the symbol. Used in the x86-64 local 154 /// exec TLS access model. 155 /// 156 /// See 'ELF Handling for Thread-Local Storage' for more details. 157 /// SYMBOL_LABEL @TPOFF 158 MO_TPOFF, 159 160 /// MO_DTPOFF - On a symbol operand this indicates that the immediate is 161 /// the offset of the GOT entry with the TLS offset of the symbol. Used 162 /// in the local dynamic TLS access model. 163 /// 164 /// See 'ELF Handling for Thread-Local Storage' for more details. 165 /// SYMBOL_LABEL @DTPOFF 166 MO_DTPOFF, 167 168 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 169 /// the negative thread-pointer offset for the symbol. Used in the IA32 170 /// local exec TLS access model. 171 /// 172 /// See 'ELF Handling for Thread-Local Storage' for more details. 173 /// SYMBOL_LABEL @NTPOFF 174 MO_NTPOFF, 175 176 /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is 177 /// the offset of the GOT entry with the negative thread-pointer offset for 178 /// the symbol. Used in the PIC IA32 initial exec TLS access model. 179 /// 180 /// See 'ELF Handling for Thread-Local Storage' for more details. 181 /// SYMBOL_LABEL @GOTNTPOFF 182 MO_GOTNTPOFF, 183 184 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 185 /// reference is actually to the "__imp_FOO" symbol. This is used for 186 /// dllimport linkage on windows. 187 MO_DLLIMPORT, 188 189 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the 190 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a 191 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 192 MO_DARWIN_NONLAZY, 193 194 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates 195 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is 196 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 197 MO_DARWIN_NONLAZY_PIC_BASE, 198 199 /// MO_TLVP - On a symbol operand this indicates that the immediate is 200 /// some TLS offset. 201 /// 202 /// This is the TLS offset for the Darwin TLS mechanism. 203 MO_TLVP, 204 205 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate 206 /// is some TLS offset from the picbase. 207 /// 208 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode. 209 MO_TLVP_PIC_BASE, 210 211 /// MO_SECREL - On a symbol operand this indicates that the immediate is 212 /// the offset from beginning of section. 213 /// 214 /// This is the TLS offset for the COFF/Windows TLS mechanism. 215 MO_SECREL 216 }; 217 218 enum : uint64_t { 219 //===------------------------------------------------------------------===// 220 // Instruction encodings. These are the standard/most common forms for X86 221 // instructions. 222 // 223 224 // PseudoFrm - This represents an instruction that is a pseudo instruction 225 // or one that has not been implemented yet. It is illegal to code generate 226 // it, but tolerated for intermediate implementation stages. 227 Pseudo = 0, 228 229 /// Raw - This form is for instructions that don't have any operands, so 230 /// they are just a fixed opcode value, like 'leave'. 231 RawFrm = 1, 232 233 /// AddRegFrm - This form is used for instructions like 'push r32' that have 234 /// their one register operand added to their opcode. 235 AddRegFrm = 2, 236 237 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 238 /// to specify a destination, which in this case is a register. 239 /// 240 MRMDestReg = 3, 241 242 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 243 /// to specify a destination, which in this case is memory. 244 /// 245 MRMDestMem = 4, 246 247 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 248 /// to specify a source, which in this case is a register. 249 /// 250 MRMSrcReg = 5, 251 252 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 253 /// to specify a source, which in this case is memory. 254 /// 255 MRMSrcMem = 6, 256 257 /// RawFrmMemOffs - This form is for instructions that store an absolute 258 /// memory offset as an immediate with a possible segment override. 259 RawFrmMemOffs = 7, 260 261 /// RawFrmSrc - This form is for instructions that use the source index 262 /// register SI/ESI/RSI with a possible segment override. 263 RawFrmSrc = 8, 264 265 /// RawFrmDst - This form is for instructions that use the destination index 266 /// register DI/EDI/ESI. 267 RawFrmDst = 9, 268 269 /// RawFrmSrc - This form is for instructions that use the source index 270 /// register SI/ESI/ERI with a possible segment override, and also the 271 /// destination index register DI/ESI/RDI. 272 RawFrmDstSrc = 10, 273 274 /// RawFrmImm8 - This is used for the ENTER instruction, which has two 275 /// immediates, the first of which is a 16-bit immediate (specified by 276 /// the imm encoding) and the second is a 8-bit fixed value. 277 RawFrmImm8 = 11, 278 279 /// RawFrmImm16 - This is used for CALL FAR instructions, which have two 280 /// immediates, the first of which is a 16 or 32-bit immediate (specified by 281 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD 282 /// manual, this operand is described as pntr16:32 and pntr16:16 283 RawFrmImm16 = 12, 284 285 /// MRMX[rm] - The forms are used to represent instructions that use a 286 /// Mod/RM byte, and don't use the middle field for anything. 287 MRMXr = 14, MRMXm = 15, 288 289 /// MRM[0-7][rm] - These forms are used to represent instructions that use 290 /// a Mod/RM byte, and use the middle field to hold extended opcode 291 /// information. In the intel manual these are represented as /0, /1, ... 292 /// 293 294 // First, instructions that operate on a register r/m operand... 295 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 296 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 297 298 // Next, instructions that operate on a memory r/m operand... 299 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 300 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 301 302 //// MRM_XX - A mod/rm byte of exactly 0xXX. 303 MRM_C0 = 32, MRM_C1 = 33, MRM_C2 = 34, MRM_C3 = 35, 304 MRM_C4 = 36, MRM_C5 = 37, MRM_C6 = 38, MRM_C7 = 39, 305 MRM_C8 = 40, MRM_C9 = 41, MRM_CA = 42, MRM_CB = 43, 306 MRM_CC = 44, MRM_CD = 45, MRM_CE = 46, MRM_CF = 47, 307 MRM_D0 = 48, MRM_D1 = 49, MRM_D2 = 50, MRM_D3 = 51, 308 MRM_D4 = 52, MRM_D5 = 53, MRM_D6 = 54, MRM_D7 = 55, 309 MRM_D8 = 56, MRM_D9 = 57, MRM_DA = 58, MRM_DB = 59, 310 MRM_DC = 60, MRM_DD = 61, MRM_DE = 62, MRM_DF = 63, 311 MRM_E0 = 64, MRM_E1 = 65, MRM_E2 = 66, MRM_E3 = 67, 312 MRM_E4 = 68, MRM_E5 = 69, MRM_E6 = 70, MRM_E7 = 71, 313 MRM_E8 = 72, MRM_E9 = 73, MRM_EA = 74, MRM_EB = 75, 314 MRM_EC = 76, MRM_ED = 77, MRM_EE = 78, MRM_EF = 79, 315 MRM_F0 = 80, MRM_F1 = 81, MRM_F2 = 82, MRM_F3 = 83, 316 MRM_F4 = 84, MRM_F5 = 85, MRM_F6 = 86, MRM_F7 = 87, 317 MRM_F8 = 88, MRM_F9 = 89, MRM_FA = 90, MRM_FB = 91, 318 MRM_FC = 92, MRM_FD = 93, MRM_FE = 94, MRM_FF = 95, 319 320 FormMask = 127, 321 322 //===------------------------------------------------------------------===// 323 // Actual flags... 324 325 // OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix. 326 // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in 327 // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66 328 // prefix in 16-bit mode. 329 OpSizeShift = 7, 330 OpSizeMask = 0x3 << OpSizeShift, 331 332 OpSizeFixed = 0 << OpSizeShift, 333 OpSize16 = 1 << OpSizeShift, 334 OpSize32 = 2 << OpSizeShift, 335 336 // AsSize - AdSizeX implies this instruction determines its need of 0x67 337 // prefix from a normal ModRM memory operand. The other types indicate that 338 // an operand is encoded with a specific width and a prefix is needed if 339 // it differs from the current mode. 340 AdSizeShift = OpSizeShift + 2, 341 AdSizeMask = 0x3 << AdSizeShift, 342 343 AdSizeX = 1 << AdSizeShift, 344 AdSize16 = 1 << AdSizeShift, 345 AdSize32 = 2 << AdSizeShift, 346 AdSize64 = 3 << AdSizeShift, 347 348 //===------------------------------------------------------------------===// 349 // OpPrefix - There are several prefix bytes that are used as opcode 350 // extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is 351 // no prefix. 352 // 353 OpPrefixShift = AdSizeShift + 2, 354 OpPrefixMask = 0x7 << OpPrefixShift, 355 356 // PS, PD - Prefix code for packed single and double precision vector 357 // floating point operations performed in the SSE registers. 358 PS = 1 << OpPrefixShift, PD = 2 << OpPrefixShift, 359 360 // XS, XD - These prefix codes are for single and double precision scalar 361 // floating point operations performed in the SSE registers. 362 XS = 3 << OpPrefixShift, XD = 4 << OpPrefixShift, 363 364 //===------------------------------------------------------------------===// 365 // OpMap - This field determines which opcode map this instruction 366 // belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc. 367 // 368 OpMapShift = OpPrefixShift + 3, 369 OpMapMask = 0x7 << OpMapShift, 370 371 // OB - OneByte - Set if this instruction has a one byte opcode. 372 OB = 0 << OpMapShift, 373 374 // TB - TwoByte - Set if this instruction has a two byte opcode, which 375 // starts with a 0x0F byte before the real opcode. 376 TB = 1 << OpMapShift, 377 378 // T8, TA - Prefix after the 0x0F prefix. 379 T8 = 2 << OpMapShift, TA = 3 << OpMapShift, 380 381 // XOP8 - Prefix to include use of imm byte. 382 XOP8 = 4 << OpMapShift, 383 384 // XOP9 - Prefix to exclude use of imm byte. 385 XOP9 = 5 << OpMapShift, 386 387 // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions. 388 XOPA = 6 << OpMapShift, 389 390 //===------------------------------------------------------------------===// 391 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 392 // They are used to specify GPRs and SSE registers, 64-bit operand size, 393 // etc. We only cares about REX.W and REX.R bits and only the former is 394 // statically determined. 395 // 396 REXShift = OpMapShift + 3, 397 REX_W = 1 << REXShift, 398 399 //===------------------------------------------------------------------===// 400 // This three-bit field describes the size of an immediate operand. Zero is 401 // unused so that we can tell if we forgot to set a value. 402 ImmShift = REXShift + 1, 403 ImmMask = 15 << ImmShift, 404 Imm8 = 1 << ImmShift, 405 Imm8PCRel = 2 << ImmShift, 406 Imm16 = 3 << ImmShift, 407 Imm16PCRel = 4 << ImmShift, 408 Imm32 = 5 << ImmShift, 409 Imm32PCRel = 6 << ImmShift, 410 Imm32S = 7 << ImmShift, 411 Imm64 = 8 << ImmShift, 412 413 //===------------------------------------------------------------------===// 414 // FP Instruction Classification... Zero is non-fp instruction. 415 416 // FPTypeMask - Mask for all of the FP types... 417 FPTypeShift = ImmShift + 4, 418 FPTypeMask = 7 << FPTypeShift, 419 420 // NotFP - The default, set for instructions that do not use FP registers. 421 NotFP = 0 << FPTypeShift, 422 423 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 424 ZeroArgFP = 1 << FPTypeShift, 425 426 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 427 OneArgFP = 2 << FPTypeShift, 428 429 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 430 // result back to ST(0). For example, fcos, fsqrt, etc. 431 // 432 OneArgFPRW = 3 << FPTypeShift, 433 434 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 435 // explicit argument, storing the result to either ST(0) or the implicit 436 // argument. For example: fadd, fsub, fmul, etc... 437 TwoArgFP = 4 << FPTypeShift, 438 439 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 440 // explicit argument, but have no destination. Example: fucom, fucomi, ... 441 CompareFP = 5 << FPTypeShift, 442 443 // CondMovFP - "2 operand" floating point conditional move instructions. 444 CondMovFP = 6 << FPTypeShift, 445 446 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 447 SpecialFP = 7 << FPTypeShift, 448 449 // Lock prefix 450 LOCKShift = FPTypeShift + 3, 451 LOCK = 1 << LOCKShift, 452 453 // REP prefix 454 REPShift = LOCKShift + 1, 455 REP = 1 << REPShift, 456 457 // Execution domain for SSE instructions. 458 // 0 means normal, non-SSE instruction. 459 SSEDomainShift = REPShift + 1, 460 461 // Encoding 462 EncodingShift = SSEDomainShift + 2, 463 EncodingMask = 0x3 << EncodingShift, 464 465 // VEX - encoding using 0xC4/0xC5 466 VEX = 1 << EncodingShift, 467 468 /// XOP - Opcode prefix used by XOP instructions. 469 XOP = 2 << EncodingShift, 470 471 // VEX_EVEX - Specifies that this instruction use EVEX form which provides 472 // syntax support up to 32 512-bit register operands and up to 7 16-bit 473 // mask operands as well as source operand data swizzling/memory operand 474 // conversion, eviction hint, and rounding mode. 475 EVEX = 3 << EncodingShift, 476 477 // Opcode 478 OpcodeShift = EncodingShift + 2, 479 480 /// VEX_W - Has a opcode specific functionality, but is used in the same 481 /// way as REX_W is for regular SSE instructions. 482 VEX_WShift = OpcodeShift + 8, 483 VEX_W = 1ULL << VEX_WShift, 484 485 /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2 486 /// address instructions in SSE are represented as 3 address ones in AVX 487 /// and the additional register is encoded in VEX_VVVV prefix. 488 VEX_4VShift = VEX_WShift + 1, 489 VEX_4V = 1ULL << VEX_4VShift, 490 491 /// VEX_4VOp3 - Similar to VEX_4V, but used on instructions that encode 492 /// operand 3 with VEX.vvvv. 493 VEX_4VOp3Shift = VEX_4VShift + 1, 494 VEX_4VOp3 = 1ULL << VEX_4VOp3Shift, 495 496 /// VEX_I8IMM - Specifies that the last register used in a AVX instruction, 497 /// must be encoded in the i8 immediate field. This usually happens in 498 /// instructions with 4 operands. 499 VEX_I8IMMShift = VEX_4VOp3Shift + 1, 500 VEX_I8IMM = 1ULL << VEX_I8IMMShift, 501 502 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current 503 /// instruction uses 256-bit wide registers. This is usually auto detected 504 /// if a VR256 register is used, but some AVX instructions also have this 505 /// field marked when using a f256 memory references. 506 VEX_LShift = VEX_I8IMMShift + 1, 507 VEX_L = 1ULL << VEX_LShift, 508 509 // VEX_LIG - Specifies that this instruction ignores the L-bit in the VEX 510 // prefix. Usually used for scalar instructions. Needed by disassembler. 511 VEX_LIGShift = VEX_LShift + 1, 512 VEX_LIG = 1ULL << VEX_LIGShift, 513 514 // TODO: we should combine VEX_L and VEX_LIG together to form a 2-bit field 515 // with following encoding: 516 // - 00 V128 517 // - 01 V256 518 // - 10 V512 519 // - 11 LIG (but, in insn encoding, leave VEX.L and EVEX.L in zeros. 520 // this will save 1 tsflag bit 521 522 // EVEX_K - Set if this instruction requires masking 523 EVEX_KShift = VEX_LIGShift + 1, 524 EVEX_K = 1ULL << EVEX_KShift, 525 526 // EVEX_Z - Set if this instruction has EVEX.Z field set. 527 EVEX_ZShift = EVEX_KShift + 1, 528 EVEX_Z = 1ULL << EVEX_ZShift, 529 530 // EVEX_L2 - Set if this instruction has EVEX.L' field set. 531 EVEX_L2Shift = EVEX_ZShift + 1, 532 EVEX_L2 = 1ULL << EVEX_L2Shift, 533 534 // EVEX_B - Set if this instruction has EVEX.B field set. 535 EVEX_BShift = EVEX_L2Shift + 1, 536 EVEX_B = 1ULL << EVEX_BShift, 537 538 // The scaling factor for the AVX512's 8-bit compressed displacement. 539 CD8_Scale_Shift = EVEX_BShift + 1, 540 CD8_Scale_Mask = 127ULL << CD8_Scale_Shift, 541 542 /// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the 543 /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents 544 /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction 545 /// storing a classifier in the imm8 field. To simplify our implementation, 546 /// we handle this by storeing the classifier in the opcode field and using 547 /// this flag to indicate that the encoder should do the wacky 3DNow! thing. 548 Has3DNow0F0FOpcodeShift = CD8_Scale_Shift + 7, 549 Has3DNow0F0FOpcode = 1ULL << Has3DNow0F0FOpcodeShift, 550 551 /// MemOp4 - Used to indicate swapping of operand 3 and 4 to be encoded in 552 /// ModRM or I8IMM. This is used for FMA4 and XOP instructions. 553 MemOp4Shift = Has3DNow0F0FOpcodeShift + 1, 554 MemOp4 = 1ULL << MemOp4Shift, 555 556 /// Explicitly specified rounding control 557 EVEX_RCShift = MemOp4Shift + 1, 558 EVEX_RC = 1ULL << EVEX_RCShift 559 }; 560 561 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 562 // specified machine instruction. 563 // 564 inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { 565 return TSFlags >> X86II::OpcodeShift; 566 } 567 568 inline bool hasImm(uint64_t TSFlags) { 569 return (TSFlags & X86II::ImmMask) != 0; 570 } 571 572 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field 573 /// of the specified instruction. 574 inline unsigned getSizeOfImm(uint64_t TSFlags) { 575 switch (TSFlags & X86II::ImmMask) { 576 default: llvm_unreachable("Unknown immediate size"); 577 case X86II::Imm8: 578 case X86II::Imm8PCRel: return 1; 579 case X86II::Imm16: 580 case X86II::Imm16PCRel: return 2; 581 case X86II::Imm32: 582 case X86II::Imm32S: 583 case X86II::Imm32PCRel: return 4; 584 case X86II::Imm64: return 8; 585 } 586 } 587 588 /// isImmPCRel - Return true if the immediate of the specified instruction's 589 /// TSFlags indicates that it is pc relative. 590 inline unsigned isImmPCRel(uint64_t TSFlags) { 591 switch (TSFlags & X86II::ImmMask) { 592 default: llvm_unreachable("Unknown immediate size"); 593 case X86II::Imm8PCRel: 594 case X86II::Imm16PCRel: 595 case X86II::Imm32PCRel: 596 return true; 597 case X86II::Imm8: 598 case X86II::Imm16: 599 case X86II::Imm32: 600 case X86II::Imm32S: 601 case X86II::Imm64: 602 return false; 603 } 604 } 605 606 /// isImmSigned - Return true if the immediate of the specified instruction's 607 /// TSFlags indicates that it is signed. 608 inline unsigned isImmSigned(uint64_t TSFlags) { 609 switch (TSFlags & X86II::ImmMask) { 610 default: llvm_unreachable("Unknown immediate signedness"); 611 case X86II::Imm32S: 612 return true; 613 case X86II::Imm8: 614 case X86II::Imm8PCRel: 615 case X86II::Imm16: 616 case X86II::Imm16PCRel: 617 case X86II::Imm32: 618 case X86II::Imm32PCRel: 619 case X86II::Imm64: 620 return false; 621 } 622 } 623 624 /// getOperandBias - compute any additional adjustment needed to 625 /// the offset to the start of the memory operand 626 /// in this instruction. 627 /// If this is a two-address instruction,skip one of the register operands. 628 /// FIXME: This should be handled during MCInst lowering. 629 inline int getOperandBias(const MCInstrDesc& Desc) 630 { 631 unsigned NumOps = Desc.getNumOperands(); 632 unsigned CurOp = 0; 633 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) 634 ++CurOp; 635 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && 636 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1) 637 // Special case for AVX-512 GATHER with 2 TIED_TO operands 638 // Skip the first 2 operands: dst, mask_wb 639 CurOp += 2; 640 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && 641 Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1) 642 // Special case for GATHER with 2 TIED_TO operands 643 // Skip the first 2 operands: dst, mask_wb 644 CurOp += 2; 645 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps - 2, MCOI::TIED_TO) == 0) 646 // SCATTER 647 ++CurOp; 648 return CurOp; 649 } 650 651 /// getMemoryOperandNo - The function returns the MCInst operand # for the 652 /// first field of the memory operand. If the instruction doesn't have a 653 /// memory operand, this returns -1. 654 /// 655 /// Note that this ignores tied operands. If there is a tied register which 656 /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only 657 /// counted as one operand. 658 /// 659 inline int getMemoryOperandNo(uint64_t TSFlags) { 660 bool HasVEX_4V = TSFlags & X86II::VEX_4V; 661 bool HasMemOp4 = TSFlags & X86II::MemOp4; 662 bool HasEVEX_K = TSFlags & X86II::EVEX_K; 663 664 switch (TSFlags & X86II::FormMask) { 665 default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!"); 666 case X86II::Pseudo: 667 case X86II::RawFrm: 668 case X86II::AddRegFrm: 669 case X86II::MRMDestReg: 670 case X86II::MRMSrcReg: 671 case X86II::RawFrmImm8: 672 case X86II::RawFrmImm16: 673 case X86II::RawFrmMemOffs: 674 case X86II::RawFrmSrc: 675 case X86II::RawFrmDst: 676 case X86II::RawFrmDstSrc: 677 return -1; 678 case X86II::MRMDestMem: 679 return 0; 680 case X86II::MRMSrcMem: 681 // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a 682 // mask register. 683 return 1 + HasVEX_4V + HasMemOp4 + HasEVEX_K; 684 case X86II::MRMXr: 685 case X86II::MRM0r: case X86II::MRM1r: 686 case X86II::MRM2r: case X86II::MRM3r: 687 case X86II::MRM4r: case X86II::MRM5r: 688 case X86II::MRM6r: case X86II::MRM7r: 689 return -1; 690 case X86II::MRMXm: 691 case X86II::MRM0m: case X86II::MRM1m: 692 case X86II::MRM2m: case X86II::MRM3m: 693 case X86II::MRM4m: case X86II::MRM5m: 694 case X86II::MRM6m: case X86II::MRM7m: 695 // Start from 0, skip registers encoded in VEX_VVVV or a mask register. 696 return 0 + HasVEX_4V + HasEVEX_K; 697 case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2: 698 case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5: 699 case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8: 700 case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB: 701 case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE: 702 case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1: 703 case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4: 704 case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7: 705 case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA: 706 case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD: 707 case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0: 708 case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3: 709 case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6: 710 case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9: 711 case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC: 712 case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF: 713 case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2: 714 case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5: 715 case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8: 716 case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB: 717 case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE: 718 case X86II::MRM_FF: 719 return -1; 720 } 721 } 722 723 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or 724 /// higher) register? e.g. r8, xmm8, xmm13, etc. 725 inline bool isX86_64ExtendedReg(unsigned RegNo) { 726 if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM15) || 727 (RegNo >= X86::XMM24 && RegNo <= X86::XMM31) || 728 (RegNo >= X86::YMM8 && RegNo <= X86::YMM15) || 729 (RegNo >= X86::YMM24 && RegNo <= X86::YMM31) || 730 (RegNo >= X86::ZMM8 && RegNo <= X86::ZMM15) || 731 (RegNo >= X86::ZMM24 && RegNo <= X86::ZMM31)) 732 return true; 733 734 switch (RegNo) { 735 default: break; 736 case X86::R8: case X86::R9: case X86::R10: case X86::R11: 737 case X86::R12: case X86::R13: case X86::R14: case X86::R15: 738 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: 739 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: 740 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: 741 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: 742 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: 743 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: 744 case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11: 745 case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15: 746 return true; 747 } 748 return false; 749 } 750 751 /// is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher) 752 /// registers? e.g. zmm21, etc. 753 static inline bool is32ExtendedReg(unsigned RegNo) { 754 return ((RegNo >= X86::XMM16 && RegNo <= X86::XMM31) || 755 (RegNo >= X86::YMM16 && RegNo <= X86::YMM31) || 756 (RegNo >= X86::ZMM16 && RegNo <= X86::ZMM31)); 757 } 758 759 760 inline bool isX86_64NonExtLowByteReg(unsigned reg) { 761 return (reg == X86::SPL || reg == X86::BPL || 762 reg == X86::SIL || reg == X86::DIL); 763 } 764 } 765 766 } // end namespace llvm; 767 768 #endif 769
