1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions -----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides X86 specific target descriptions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86MCTargetDesc.h" 15 #include "X86MCAsmInfo.h" 16 #include "InstPrinter/X86ATTInstPrinter.h" 17 #include "InstPrinter/X86IntelInstPrinter.h" 18 #include "llvm/MC/MachineLocation.h" 19 #include "llvm/MC/MCCodeGenInfo.h" 20 #include "llvm/MC/MCInstrAnalysis.h" 21 #include "llvm/MC/MCInstrInfo.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCStreamer.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/ADT/Triple.h" 26 #include "llvm/Support/Host.h" 27 #include "llvm/Support/TargetRegistry.h" 28 29 #define GET_REGINFO_MC_DESC 30 #include "X86GenRegisterInfo.inc" 31 32 #define GET_INSTRINFO_MC_DESC 33 #include "X86GenInstrInfo.inc" 34 35 #define GET_SUBTARGETINFO_MC_DESC 36 #include "X86GenSubtargetInfo.inc" 37 38 #ifdef _MSC_VER 39 #include <intrin.h> 40 #endif 41 42 using namespace llvm; 43 44 45 std::string X86_MC::ParseX86Triple(StringRef TT) { 46 Triple TheTriple(TT); 47 std::string FS; 48 if (TheTriple.getArch() == Triple::x86_64) 49 FS = "+64bit-mode"; 50 else 51 FS = "-64bit-mode"; 52 if (TheTriple.getOS() == Triple::NativeClient) 53 FS += ",+nacl-mode"; 54 else 55 FS += ",-nacl-mode"; 56 return FS; 57 } 58 59 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the 60 /// specified arguments. If we can't run cpuid on the host, return true. 61 bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, 62 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) { 63 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) 64 #if defined(__GNUC__) 65 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. 66 asm ("movq\t%%rbx, %%rsi\n\t" 67 "cpuid\n\t" 68 "xchgq\t%%rbx, %%rsi\n\t" 69 : "=a" (*rEAX), 70 "=S" (*rEBX), 71 "=c" (*rECX), 72 "=d" (*rEDX) 73 : "a" (value)); 74 return false; 75 #elif defined(_MSC_VER) 76 int registers[4]; 77 __cpuid(registers, value); 78 *rEAX = registers[0]; 79 *rEBX = registers[1]; 80 *rECX = registers[2]; 81 *rEDX = registers[3]; 82 return false; 83 #endif 84 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) 85 #if defined(__GNUC__) 86 asm ("movl\t%%ebx, %%esi\n\t" 87 "cpuid\n\t" 88 "xchgl\t%%ebx, %%esi\n\t" 89 : "=a" (*rEAX), 90 "=S" (*rEBX), 91 "=c" (*rECX), 92 "=d" (*rEDX) 93 : "a" (value)); 94 return false; 95 #elif defined(_MSC_VER) 96 __asm { 97 mov eax,value 98 cpuid 99 mov esi,rEAX 100 mov dword ptr [esi],eax 101 mov esi,rEBX 102 mov dword ptr [esi],ebx 103 mov esi,rECX 104 mov dword ptr [esi],ecx 105 mov esi,rEDX 106 mov dword ptr [esi],edx 107 } 108 return false; 109 #endif 110 #endif 111 return true; 112 } 113 114 void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family, 115 unsigned &Model) { 116 Family = (EAX >> 8) & 0xf; // Bits 8 - 11 117 Model = (EAX >> 4) & 0xf; // Bits 4 - 7 118 if (Family == 6 || Family == 0xf) { 119 if (Family == 0xf) 120 // Examine extended family ID if family ID is F. 121 Family += (EAX >> 20) & 0xff; // Bits 20 - 27 122 // Examine extended model ID if family ID is 6 or F. 123 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 124 } 125 } 126 127 unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) { 128 Triple TheTriple(TT); 129 if (TheTriple.getArch() == Triple::x86_64) 130 return DWARFFlavour::X86_64; 131 132 if (TheTriple.isOSDarwin()) 133 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic; 134 if (TheTriple.getOS() == Triple::MinGW32 || 135 TheTriple.getOS() == Triple::Cygwin) 136 // Unsupported by now, just quick fallback 137 return DWARFFlavour::X86_32_Generic; 138 return DWARFFlavour::X86_32_Generic; 139 } 140 141 /// getX86RegNum - This function maps LLVM register identifiers to their X86 142 /// specific numbering, which is used in various places encoding instructions. 143 unsigned X86_MC::getX86RegNum(unsigned RegNo) { 144 switch(RegNo) { 145 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX; 146 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX; 147 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX; 148 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX; 149 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH: 150 return N86::ESP; 151 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH: 152 return N86::EBP; 153 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH: 154 return N86::ESI; 155 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH: 156 return N86::EDI; 157 158 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: 159 return N86::EAX; 160 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B: 161 return N86::ECX; 162 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B: 163 return N86::EDX; 164 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B: 165 return N86::EBX; 166 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B: 167 return N86::ESP; 168 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B: 169 return N86::EBP; 170 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B: 171 return N86::ESI; 172 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B: 173 return N86::EDI; 174 175 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3: 176 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7: 177 return RegNo-X86::ST0; 178 179 case X86::XMM0: case X86::XMM8: 180 case X86::YMM0: case X86::YMM8: case X86::MM0: 181 return 0; 182 case X86::XMM1: case X86::XMM9: 183 case X86::YMM1: case X86::YMM9: case X86::MM1: 184 return 1; 185 case X86::XMM2: case X86::XMM10: 186 case X86::YMM2: case X86::YMM10: case X86::MM2: 187 return 2; 188 case X86::XMM3: case X86::XMM11: 189 case X86::YMM3: case X86::YMM11: case X86::MM3: 190 return 3; 191 case X86::XMM4: case X86::XMM12: 192 case X86::YMM4: case X86::YMM12: case X86::MM4: 193 return 4; 194 case X86::XMM5: case X86::XMM13: 195 case X86::YMM5: case X86::YMM13: case X86::MM5: 196 return 5; 197 case X86::XMM6: case X86::XMM14: 198 case X86::YMM6: case X86::YMM14: case X86::MM6: 199 return 6; 200 case X86::XMM7: case X86::XMM15: 201 case X86::YMM7: case X86::YMM15: case X86::MM7: 202 return 7; 203 204 case X86::ES: return 0; 205 case X86::CS: return 1; 206 case X86::SS: return 2; 207 case X86::DS: return 3; 208 case X86::FS: return 4; 209 case X86::GS: return 5; 210 211 case X86::CR0: case X86::CR8 : case X86::DR0: return 0; 212 case X86::CR1: case X86::CR9 : case X86::DR1: return 1; 213 case X86::CR2: case X86::CR10: case X86::DR2: return 2; 214 case X86::CR3: case X86::CR11: case X86::DR3: return 3; 215 case X86::CR4: case X86::CR12: case X86::DR4: return 4; 216 case X86::CR5: case X86::CR13: case X86::DR5: return 5; 217 case X86::CR6: case X86::CR14: case X86::DR6: return 6; 218 case X86::CR7: case X86::CR15: case X86::DR7: return 7; 219 220 // Pseudo index registers are equivalent to a "none" 221 // scaled index (See Intel Manual 2A, table 2-3) 222 case X86::EIZ: 223 case X86::RIZ: 224 return 4; 225 226 default: 227 assert((int(RegNo) > 0) && "Unknown physical register!"); 228 return 0; 229 } 230 } 231 232 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) { 233 // FIXME: TableGen these. 234 for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) { 235 int SEH = X86_MC::getX86RegNum(Reg); 236 switch (Reg) { 237 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: 238 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B: 239 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B: 240 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B: 241 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B: 242 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B: 243 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B: 244 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B: 245 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: 246 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15: 247 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11: 248 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15: 249 SEH += 8; 250 break; 251 } 252 MRI->mapLLVMRegToSEHReg(Reg, SEH); 253 } 254 } 255 256 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU, 257 StringRef FS) { 258 std::string ArchFS = X86_MC::ParseX86Triple(TT); 259 if (!FS.empty()) { 260 if (!ArchFS.empty()) 261 ArchFS = ArchFS + "," + FS.str(); 262 else 263 ArchFS = FS; 264 } 265 266 std::string CPUName = CPU; 267 if (CPUName.empty()) { 268 #if defined (__x86_64__) || defined(__i386__) 269 CPUName = sys::getHostCPUName(); 270 #else 271 CPUName = "generic"; 272 #endif 273 } 274 275 MCSubtargetInfo *X = new MCSubtargetInfo(); 276 InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS); 277 return X; 278 } 279 280 static MCInstrInfo *createX86MCInstrInfo() { 281 MCInstrInfo *X = new MCInstrInfo(); 282 InitX86MCInstrInfo(X); 283 return X; 284 } 285 286 static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) { 287 Triple TheTriple(TT); 288 unsigned RA = (TheTriple.getArch() == Triple::x86_64) 289 ? X86::RIP // Should have dwarf #16. 290 : X86::EIP; // Should have dwarf #8. 291 292 MCRegisterInfo *X = new MCRegisterInfo(); 293 InitX86MCRegisterInfo(X, RA, 294 X86_MC::getDwarfRegFlavour(TT, false), 295 X86_MC::getDwarfRegFlavour(TT, true)); 296 X86_MC::InitLLVM2SEHRegisterMapping(X); 297 return X; 298 } 299 300 static MCAsmInfo *createX86MCAsmInfo(const Target &T, StringRef TT) { 301 Triple TheTriple(TT); 302 bool is64Bit = TheTriple.getArch() == Triple::x86_64; 303 304 MCAsmInfo *MAI; 305 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) { 306 if (is64Bit) 307 MAI = new X86_64MCAsmInfoDarwin(TheTriple); 308 else 309 MAI = new X86MCAsmInfoDarwin(TheTriple); 310 } else if (TheTriple.isOSWindows()) { 311 MAI = new X86MCAsmInfoCOFF(TheTriple); 312 } else { 313 MAI = new X86ELFMCAsmInfo(TheTriple); 314 } 315 316 // Initialize initial frame state. 317 // Calculate amount of bytes used for return address storing 318 int stackGrowth = is64Bit ? -8 : -4; 319 320 // Initial state of the frame pointer is esp+stackGrowth. 321 MachineLocation Dst(MachineLocation::VirtualFP); 322 MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth); 323 MAI->addInitialFrameState(0, Dst, Src); 324 325 // Add return address to move list 326 MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth); 327 MachineLocation CSSrc(is64Bit ? X86::RIP : X86::EIP); 328 MAI->addInitialFrameState(0, CSDst, CSSrc); 329 330 return MAI; 331 } 332 333 static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM, 334 CodeModel::Model CM) { 335 MCCodeGenInfo *X = new MCCodeGenInfo(); 336 337 Triple T(TT); 338 bool is64Bit = T.getArch() == Triple::x86_64; 339 340 if (RM == Reloc::Default) { 341 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode. 342 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we 343 // use static relocation model by default. 344 if (T.isOSDarwin()) { 345 if (is64Bit) 346 RM = Reloc::PIC_; 347 else 348 RM = Reloc::DynamicNoPIC; 349 } else if (T.isOSWindows() && is64Bit) 350 RM = Reloc::PIC_; 351 else 352 RM = Reloc::Static; 353 } 354 355 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC 356 // is defined as a model for code which may be used in static or dynamic 357 // executables but not necessarily a shared library. On X86-32 we just 358 // compile in -static mode, in x86-64 we use PIC. 359 if (RM == Reloc::DynamicNoPIC) { 360 if (is64Bit) 361 RM = Reloc::PIC_; 362 else if (!T.isOSDarwin()) 363 RM = Reloc::Static; 364 } 365 366 // If we are on Darwin, disallow static relocation model in X86-64 mode, since 367 // the Mach-O file format doesn't support it. 368 if (RM == Reloc::Static && T.isOSDarwin() && is64Bit) 369 RM = Reloc::PIC_; 370 371 // For static codegen, if we're not already set, use Small codegen. 372 if (CM == CodeModel::Default) 373 CM = CodeModel::Small; 374 else if (CM == CodeModel::JITDefault) 375 // 64-bit JIT places everything in the same buffer except external funcs. 376 CM = is64Bit ? CodeModel::Large : CodeModel::Small; 377 378 X->InitMCCodeGenInfo(RM, CM); 379 return X; 380 } 381 382 static MCStreamer *createMCStreamer(const Target &T, StringRef TT, 383 MCContext &Ctx, MCAsmBackend &MAB, 384 raw_ostream &_OS, 385 MCCodeEmitter *_Emitter, 386 bool RelaxAll, 387 bool NoExecStack) { 388 Triple TheTriple(TT); 389 390 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) 391 return createMachOStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll); 392 393 if (TheTriple.isOSWindows()) 394 return createWinCOFFStreamer(Ctx, MAB, *_Emitter, _OS, RelaxAll); 395 396 return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack); 397 } 398 399 static MCInstPrinter *createX86MCInstPrinter(const Target &T, 400 unsigned SyntaxVariant, 401 const MCAsmInfo &MAI, 402 const MCSubtargetInfo &STI) { 403 if (SyntaxVariant == 0) 404 return new X86ATTInstPrinter(MAI); 405 if (SyntaxVariant == 1) 406 return new X86IntelInstPrinter(MAI); 407 return 0; 408 } 409 410 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) { 411 return new MCInstrAnalysis(Info); 412 } 413 414 // Force static initialization. 415 extern "C" void LLVMInitializeX86TargetMC() { 416 // Register the MC asm info. 417 RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo); 418 RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo); 419 420 // Register the MC codegen info. 421 RegisterMCCodeGenInfoFn C(TheX86_32Target, createX86MCCodeGenInfo); 422 RegisterMCCodeGenInfoFn D(TheX86_64Target, createX86MCCodeGenInfo); 423 424 // Register the MC instruction info. 425 TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo); 426 TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo); 427 428 // Register the MC register info. 429 TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo); 430 TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo); 431 432 // Register the MC subtarget info. 433 TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target, 434 X86_MC::createX86MCSubtargetInfo); 435 TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target, 436 X86_MC::createX86MCSubtargetInfo); 437 438 // Register the MC instruction analyzer. 439 TargetRegistry::RegisterMCInstrAnalysis(TheX86_32Target, 440 createX86MCInstrAnalysis); 441 TargetRegistry::RegisterMCInstrAnalysis(TheX86_64Target, 442 createX86MCInstrAnalysis); 443 444 // Register the code emitter. 445 TargetRegistry::RegisterMCCodeEmitter(TheX86_32Target, 446 createX86MCCodeEmitter); 447 TargetRegistry::RegisterMCCodeEmitter(TheX86_64Target, 448 createX86MCCodeEmitter); 449 450 // Register the asm backend. 451 TargetRegistry::RegisterMCAsmBackend(TheX86_32Target, 452 createX86_32AsmBackend); 453 TargetRegistry::RegisterMCAsmBackend(TheX86_64Target, 454 createX86_64AsmBackend); 455 456 // Register the object streamer. 457 TargetRegistry::RegisterMCObjectStreamer(TheX86_32Target, 458 createMCStreamer); 459 TargetRegistry::RegisterMCObjectStreamer(TheX86_64Target, 460 createMCStreamer); 461 462 // Register the MCInstPrinter. 463 TargetRegistry::RegisterMCInstPrinter(TheX86_32Target, 464 createX86MCInstPrinter); 465 TargetRegistry::RegisterMCInstPrinter(TheX86_64Target, 466 createX86MCInstPrinter); 467 } 468