1 //==-- llvm/CodeGen/GlobalISel/RegisterBankInfo.h ----------------*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file This file declares the API for the register bank info. 11 /// This API is responsible for handling the register banks. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_CODEGEN_GLOBALISEL_REGBANKINFO_H 16 #define LLVM_CODEGEN_GLOBALISEL_REGBANKINFO_H 17 18 #include "llvm/ADT/APInt.h" 19 #include "llvm/ADT/DenseMap.h" 20 #include "llvm/ADT/Hashing.h" 21 #include "llvm/ADT/SmallVector.h" 22 #include "llvm/CodeGen/GlobalISel/RegisterBank.h" 23 #include "llvm/CodeGen/MachineValueType.h" // For SimpleValueType. 24 #include "llvm/Support/ErrorHandling.h" 25 26 #include <cassert> 27 #include <memory> // For unique_ptr. 28 29 namespace llvm { 30 class MachineInstr; 31 class MachineRegisterInfo; 32 class TargetInstrInfo; 33 class TargetRegisterInfo; 34 class raw_ostream; 35 36 /// Holds all the information related to register banks. 37 class RegisterBankInfo { 38 public: 39 /// Helper struct that represents how a value is partially mapped 40 /// into a register. 41 /// The StartIdx and Length represent what region of the orginal 42 /// value this partial mapping covers. 43 /// This can be represented as a Mask of contiguous bit starting 44 /// at StartIdx bit and spanning Length bits. 45 /// StartIdx is the number of bits from the less significant bits. 46 struct PartialMapping { 47 /// Number of bits at which this partial mapping starts in the 48 /// original value. The bits are counted from less significant 49 /// bits to most significant bits. 50 unsigned StartIdx; 51 /// Length of this mapping in bits. This is how many bits this 52 /// partial mapping covers in the original value: 53 /// from StartIdx to StartIdx + Length -1. 54 unsigned Length; 55 /// Register bank where the partial value lives. 56 const RegisterBank *RegBank; 57 58 PartialMapping() = default; 59 60 /// Provide a shortcut for quickly building PartialMapping. 61 PartialMapping(unsigned StartIdx, unsigned Length, 62 const RegisterBank &RegBank) 63 : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {} 64 65 /// \return the index of in the original value of the most 66 /// significant bit that this partial mapping covers. 67 unsigned getHighBitIdx() const { return StartIdx + Length - 1; } 68 69 /// Print this partial mapping on dbgs() stream. 70 void dump() const; 71 72 /// Print this partial mapping on \p OS; 73 void print(raw_ostream &OS) const; 74 75 /// Check that the Mask is compatible with the RegBank. 76 /// Indeed, if the RegBank cannot accomadate the "active bits" of the mask, 77 /// there is no way this mapping is valid. 78 /// 79 /// \note This method does not check anything when assertions are disabled. 80 /// 81 /// \return True is the check was successful. 82 bool verify() const; 83 }; 84 85 /// Helper struct that represents how a value is mapped through 86 /// different register banks. 87 /// 88 /// \note: So far we do not have any users of the complex mappings 89 /// (mappings with more than one partial mapping), but when we do, 90 /// we would have needed to duplicate partial mappings. 91 /// The alternative could be to use an array of pointers of partial 92 /// mapping (i.e., PartialMapping **BreakDown) and duplicate the 93 /// pointers instead. 94 /// 95 /// E.g., 96 /// Let say we have a 32-bit add and a <2 x 32-bit> vadd. We 97 /// can expand the 98 /// <2 x 32-bit> add into 2 x 32-bit add. 99 /// 100 /// Currently the TableGen-like file would look like: 101 /// \code 102 /// PartialMapping[] = { 103 /// /*32-bit add*/ {0, 32, GPR}, 104 /// /*2x32-bit add*/ {0, 32, GPR}, {0, 32, GPR}, // <-- Same entry 3x 105 /// /*<2x32-bit> vadd {0, 64, VPR} 106 /// }; // PartialMapping duplicated. 107 /// 108 /// ValueMapping[] { 109 /// /*plain 32-bit add*/ {&PartialMapping[0], 1}, 110 /// /*expanded vadd on 2xadd*/ {&PartialMapping[1], 2}, 111 /// /*plain <2x32-bit> vadd*/ {&PartialMapping[3], 1} 112 /// }; 113 /// \endcode 114 /// 115 /// With the array of pointer, we would have: 116 /// \code 117 /// PartialMapping[] = { 118 /// /*32-bit add*/ {0, 32, GPR}, 119 /// /*<2x32-bit> vadd {0, 64, VPR} 120 /// }; // No more duplication. 121 /// 122 /// BreakDowns[] = { 123 /// /*AddBreakDown*/ &PartialMapping[0], 124 /// /*2xAddBreakDown*/ &PartialMapping[0], &PartialMapping[0], 125 /// /*VAddBreakDown*/ &PartialMapping[1] 126 /// }; // Addresses of PartialMapping duplicated (smaller). 127 /// 128 /// ValueMapping[] { 129 /// /*plain 32-bit add*/ {&BreakDowns[0], 1}, 130 /// /*expanded vadd on 2xadd*/ {&BreakDowns[1], 2}, 131 /// /*plain <2x32-bit> vadd*/ {&BreakDowns[3], 1} 132 /// }; 133 /// \endcode 134 /// 135 /// Given that a PartialMapping is actually small, the code size 136 /// impact is actually a degradation. Moreover the compile time will 137 /// be hit by the additional indirection. 138 /// If PartialMapping gets bigger we may reconsider. 139 struct ValueMapping { 140 /// How the value is broken down between the different register banks. 141 const PartialMapping *BreakDown; 142 143 /// Number of partial mapping to break down this value. 144 unsigned NumBreakDowns; 145 146 /// The default constructor creates an invalid (isValid() == false) 147 /// instance. 148 ValueMapping() : ValueMapping(nullptr, 0) {} 149 150 /// Initialize a ValueMapping with the given parameter. 151 /// \p BreakDown needs to have a life time at least as long 152 /// as this instance. 153 ValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns) 154 : BreakDown(BreakDown), NumBreakDowns(NumBreakDowns) {} 155 156 /// Iterators through the PartialMappings. 157 const PartialMapping *begin() const { return BreakDown; } 158 const PartialMapping *end() const { return BreakDown + NumBreakDowns; } 159 160 /// Check if this ValueMapping is valid. 161 bool isValid() const { return BreakDown && NumBreakDowns; } 162 163 /// Verify that this mapping makes sense for a value of 164 /// \p MeaningfulBitWidth. 165 /// \note This method does not check anything when assertions are disabled. 166 /// 167 /// \return True is the check was successful. 168 bool verify(unsigned MeaningfulBitWidth) const; 169 170 /// Print this on dbgs() stream. 171 void dump() const; 172 173 /// Print this on \p OS; 174 void print(raw_ostream &OS) const; 175 }; 176 177 /// Helper class that represents how the value of an instruction may be 178 /// mapped and what is the related cost of such mapping. 179 class InstructionMapping { 180 /// Identifier of the mapping. 181 /// This is used to communicate between the target and the optimizers 182 /// which mapping should be realized. 183 unsigned ID; 184 /// Cost of this mapping. 185 unsigned Cost; 186 /// Mapping of all the operands. 187 const ValueMapping *OperandsMapping; 188 /// Number of operands. 189 unsigned NumOperands; 190 191 const ValueMapping &getOperandMapping(unsigned i) { 192 assert(i < getNumOperands() && "Out of bound operand"); 193 return OperandsMapping[i]; 194 } 195 196 public: 197 /// Constructor for the mapping of an instruction. 198 /// \p NumOperands must be equal to number of all the operands of 199 /// the related instruction. 200 /// The rationale is that it is more efficient for the optimizers 201 /// to be able to assume that the mapping of the ith operand is 202 /// at the index i. 203 /// 204 /// \pre ID != InvalidMappingID 205 InstructionMapping(unsigned ID, unsigned Cost, 206 const ValueMapping *OperandsMapping, 207 unsigned NumOperands) 208 : ID(ID), Cost(Cost), OperandsMapping(OperandsMapping), 209 NumOperands(NumOperands) { 210 assert(getID() != InvalidMappingID && 211 "Use the default constructor for invalid mapping"); 212 } 213 214 /// Default constructor. 215 /// Use this constructor to express that the mapping is invalid. 216 InstructionMapping() : ID(InvalidMappingID), Cost(0), NumOperands(0) {} 217 218 /// Get the cost. 219 unsigned getCost() const { return Cost; } 220 221 /// Get the ID. 222 unsigned getID() const { return ID; } 223 224 /// Get the number of operands. 225 unsigned getNumOperands() const { return NumOperands; } 226 227 /// Get the value mapping of the ith operand. 228 /// \pre The mapping for the ith operand has been set. 229 /// \pre The ith operand is a register. 230 const ValueMapping &getOperandMapping(unsigned i) const { 231 const ValueMapping &ValMapping = 232 const_cast<InstructionMapping *>(this)->getOperandMapping(i); 233 return ValMapping; 234 } 235 236 /// Set the mapping for all the operands. 237 /// In other words, OpdsMapping should hold at least getNumOperands 238 /// ValueMapping. 239 void setOperandsMapping(const ValueMapping *OpdsMapping) { 240 OperandsMapping = OpdsMapping; 241 } 242 243 /// Check whether this object is valid. 244 /// This is a lightweight check for obvious wrong instance. 245 bool isValid() const { 246 return getID() != InvalidMappingID && OperandsMapping; 247 } 248 249 /// Verifiy that this mapping makes sense for \p MI. 250 /// \pre \p MI must be connected to a MachineFunction. 251 /// 252 /// \note This method does not check anything when assertions are disabled. 253 /// 254 /// \return True is the check was successful. 255 bool verify(const MachineInstr &MI) const; 256 257 /// Print this on dbgs() stream. 258 void dump() const; 259 260 /// Print this on \p OS; 261 void print(raw_ostream &OS) const; 262 }; 263 264 /// Convenient type to represent the alternatives for mapping an 265 /// instruction. 266 /// \todo When we move to TableGen this should be an array ref. 267 typedef SmallVector<InstructionMapping, 4> InstructionMappings; 268 269 /// Helper class used to get/create the virtual registers that will be used 270 /// to replace the MachineOperand when applying a mapping. 271 class OperandsMapper { 272 /// The OpIdx-th cell contains the index in NewVRegs where the VRegs of the 273 /// OpIdx-th operand starts. -1 means we do not have such mapping yet. 274 /// Note: We use a SmallVector to avoid heap allocation for most cases. 275 SmallVector<int, 8> OpToNewVRegIdx; 276 /// Hold the registers that will be used to map MI with InstrMapping. 277 SmallVector<unsigned, 8> NewVRegs; 278 /// Current MachineRegisterInfo, used to create new virtual registers. 279 MachineRegisterInfo &MRI; 280 /// Instruction being remapped. 281 MachineInstr &MI; 282 /// New mapping of the instruction. 283 const InstructionMapping &InstrMapping; 284 285 /// Constant value identifying that the index in OpToNewVRegIdx 286 /// for an operand has not been set yet. 287 static const int DontKnowIdx; 288 289 /// Get the range in NewVRegs to store all the partial 290 /// values for the \p OpIdx-th operand. 291 /// 292 /// \return The iterator range for the space created. 293 // 294 /// \pre getMI().getOperand(OpIdx).isReg() 295 iterator_range<SmallVectorImpl<unsigned>::iterator> 296 getVRegsMem(unsigned OpIdx); 297 298 /// Get the end iterator for a range starting at \p StartIdx and 299 /// spannig \p NumVal in NewVRegs. 300 /// \pre StartIdx + NumVal <= NewVRegs.size() 301 SmallVectorImpl<unsigned>::const_iterator 302 getNewVRegsEnd(unsigned StartIdx, unsigned NumVal) const; 303 SmallVectorImpl<unsigned>::iterator getNewVRegsEnd(unsigned StartIdx, 304 unsigned NumVal); 305 306 public: 307 /// Create an OperandsMapper that will hold the information to apply \p 308 /// InstrMapping to \p MI. 309 /// \pre InstrMapping.verify(MI) 310 OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping, 311 MachineRegisterInfo &MRI); 312 313 /// Getters. 314 /// @{ 315 /// The MachineInstr being remapped. 316 MachineInstr &getMI() const { return MI; } 317 318 /// The final mapping of the instruction. 319 const InstructionMapping &getInstrMapping() const { return InstrMapping; } 320 321 /// The MachineRegisterInfo we used to realize the mapping. 322 MachineRegisterInfo &getMRI() const { return MRI; } 323 /// @} 324 325 /// Create as many new virtual registers as needed for the mapping of the \p 326 /// OpIdx-th operand. 327 /// The number of registers is determined by the number of breakdown for the 328 /// related operand in the instruction mapping. 329 /// The type of the new registers is a plain scalar of the right size. 330 /// The proper type is expected to be set when the mapping is applied to 331 /// the instruction(s) that realizes the mapping. 332 /// 333 /// \pre getMI().getOperand(OpIdx).isReg() 334 /// 335 /// \post All the partial mapping of the \p OpIdx-th operand have been 336 /// assigned a new virtual register. 337 void createVRegs(unsigned OpIdx); 338 339 /// Set the virtual register of the \p PartialMapIdx-th partial mapping of 340 /// the OpIdx-th operand to \p NewVReg. 341 /// 342 /// \pre getMI().getOperand(OpIdx).isReg() 343 /// \pre getInstrMapping().getOperandMapping(OpIdx).BreakDown.size() > 344 /// PartialMapIdx 345 /// \pre NewReg != 0 346 /// 347 /// \post the \p PartialMapIdx-th register of the value mapping of the \p 348 /// OpIdx-th operand has been set. 349 void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, unsigned NewVReg); 350 351 /// Get all the virtual registers required to map the \p OpIdx-th operand of 352 /// the instruction. 353 /// 354 /// This return an empty range when createVRegs or setVRegs has not been 355 /// called. 356 /// The iterator may be invalidated by a call to setVRegs or createVRegs. 357 /// 358 /// When \p ForDebug is true, we will not check that the list of new virtual 359 /// registers does not contain uninitialized values. 360 /// 361 /// \pre getMI().getOperand(OpIdx).isReg() 362 /// \pre ForDebug || All partial mappings have been set a register 363 iterator_range<SmallVectorImpl<unsigned>::const_iterator> 364 getVRegs(unsigned OpIdx, bool ForDebug = false) const; 365 366 /// Print this operands mapper on dbgs() stream. 367 void dump() const; 368 369 /// Print this operands mapper on \p OS stream. 370 void print(raw_ostream &OS, bool ForDebug = false) const; 371 }; 372 373 protected: 374 /// Hold the set of supported register banks. 375 RegisterBank **RegBanks; 376 /// Total number of register banks. 377 unsigned NumRegBanks; 378 379 /// Keep dynamically allocated PartialMapping in a separate map. 380 /// This shouldn't be needed when everything gets TableGen'ed. 381 mutable DenseMap<unsigned, std::unique_ptr<const PartialMapping>> MapOfPartialMappings; 382 383 /// Keep dynamically allocated ValueMapping in a separate map. 384 /// This shouldn't be needed when everything gets TableGen'ed. 385 mutable DenseMap<unsigned, std::unique_ptr<const ValueMapping> > MapOfValueMappings; 386 387 /// Keep dynamically allocated array of ValueMapping in a separate map. 388 /// This shouldn't be needed when everything gets TableGen'ed. 389 mutable DenseMap<unsigned, std::unique_ptr<ValueMapping[]>> MapOfOperandsMappings; 390 391 /// Create a RegisterBankInfo that can accomodate up to \p NumRegBanks 392 /// RegisterBank instances. 393 RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks); 394 395 /// This constructor is meaningless. 396 /// It just provides a default constructor that can be used at link time 397 /// when GlobalISel is not built. 398 /// That way, targets can still inherit from this class without doing 399 /// crazy gymnastic to avoid link time failures. 400 /// \note That works because the constructor is inlined. 401 RegisterBankInfo() { 402 llvm_unreachable("This constructor should not be executed"); 403 } 404 405 /// Get the register bank identified by \p ID. 406 RegisterBank &getRegBank(unsigned ID) { 407 assert(ID < getNumRegBanks() && "Accessing an unknown register bank"); 408 return *RegBanks[ID]; 409 } 410 411 /// Try to get the mapping of \p MI. 412 /// See getInstrMapping for more details on what a mapping represents. 413 /// 414 /// Unlike getInstrMapping the returned InstructionMapping may be invalid 415 /// (isValid() == false). 416 /// This means that the target independent code is not smart enough 417 /// to get the mapping of \p MI and thus, the target has to provide the 418 /// information for \p MI. 419 /// 420 /// This implementation is able to get the mapping of: 421 /// - Target specific instructions by looking at the encoding constraints. 422 /// - Any instruction if all the register operands have already been assigned 423 /// a register, a register class, or a register bank. 424 /// - Copies and phis if at least one of the operands has been assigned a 425 /// register, a register class, or a register bank. 426 /// In other words, this method will likely fail to find a mapping for 427 /// any generic opcode that has not been lowered by target specific code. 428 InstructionMapping getInstrMappingImpl(const MachineInstr &MI) const; 429 430 /// Get the uniquely generated PartialMapping for the 431 /// given arguments. 432 const PartialMapping &getPartialMapping(unsigned StartIdx, unsigned Length, 433 const RegisterBank &RegBank) const; 434 435 /// Methods to get a uniquely generated ValueMapping. 436 /// @{ 437 438 /// The most common ValueMapping consists of a single PartialMapping. 439 /// Feature a method for that. 440 const ValueMapping &getValueMapping(unsigned StartIdx, unsigned Length, 441 const RegisterBank &RegBank) const; 442 443 /// Get the ValueMapping for the given arguments. 444 const ValueMapping &getValueMapping(const PartialMapping *BreakDown, 445 unsigned NumBreakDowns) const; 446 /// @} 447 448 /// Methods to get a uniquely generated array of ValueMapping. 449 /// @{ 450 451 /// Get the uniquely generated array of ValueMapping for the 452 /// elements of between \p Begin and \p End. 453 /// 454 /// Elements that are nullptr will be replaced by 455 /// invalid ValueMapping (ValueMapping::isValid == false). 456 /// 457 /// \pre The pointers on ValueMapping between \p Begin and \p End 458 /// must uniquely identify a ValueMapping. Otherwise, there is no 459 /// guarantee that the return instance will be unique, i.e., another 460 /// OperandsMapping could have the same content. 461 template <typename Iterator> 462 const ValueMapping *getOperandsMapping(Iterator Begin, Iterator End) const; 463 464 /// Get the uniquely generated array of ValueMapping for the 465 /// elements of \p OpdsMapping. 466 /// 467 /// Elements of \p OpdsMapping that are nullptr will be replaced by 468 /// invalid ValueMapping (ValueMapping::isValid == false). 469 const ValueMapping *getOperandsMapping( 470 const SmallVectorImpl<const ValueMapping *> &OpdsMapping) const; 471 472 /// Get the uniquely generated array of ValueMapping for the 473 /// given arguments. 474 /// 475 /// Arguments that are nullptr will be replaced by invalid 476 /// ValueMapping (ValueMapping::isValid == false). 477 const ValueMapping *getOperandsMapping( 478 std::initializer_list<const ValueMapping *> OpdsMapping) const; 479 /// @} 480 481 /// Get the register bank for the \p OpIdx-th operand of \p MI form 482 /// the encoding constraints, if any. 483 /// 484 /// \return A register bank that covers the register class of the 485 /// related encoding constraints or nullptr if \p MI did not provide 486 /// enough information to deduce it. 487 const RegisterBank * 488 getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, 489 const TargetInstrInfo &TII, 490 const TargetRegisterInfo &TRI) const; 491 492 /// Helper method to apply something that is like the default mapping. 493 /// Basically, that means that \p OpdMapper.getMI() is left untouched 494 /// aside from the reassignment of the register operand that have been 495 /// remapped. 496 /// 497 /// The type of all the new registers that have been created by the 498 /// mapper are properly remapped to the type of the original registers 499 /// they replace. In other words, the semantic of the instruction does 500 /// not change, only the register banks. 501 /// 502 /// If the mapping of one of the operand spans several registers, this 503 /// method will abort as this is not like a default mapping anymore. 504 /// 505 /// \pre For OpIdx in {0..\p OpdMapper.getMI().getNumOperands()) 506 /// the range OpdMapper.getVRegs(OpIdx) is empty or of size 1. 507 static void applyDefaultMapping(const OperandsMapper &OpdMapper); 508 509 /// See ::applyMapping. 510 virtual void applyMappingImpl(const OperandsMapper &OpdMapper) const { 511 llvm_unreachable("The target has to implement that part"); 512 } 513 514 public: 515 virtual ~RegisterBankInfo() = default; 516 517 /// Get the register bank identified by \p ID. 518 const RegisterBank &getRegBank(unsigned ID) const { 519 return const_cast<RegisterBankInfo *>(this)->getRegBank(ID); 520 } 521 522 /// Get the register bank of \p Reg. 523 /// If Reg has not been assigned a register, a register class, 524 /// or a register bank, then this returns nullptr. 525 /// 526 /// \pre Reg != 0 (NoRegister) 527 const RegisterBank *getRegBank(unsigned Reg, const MachineRegisterInfo &MRI, 528 const TargetRegisterInfo &TRI) const; 529 530 /// Get the total number of register banks. 531 unsigned getNumRegBanks() const { return NumRegBanks; } 532 533 /// Get a register bank that covers \p RC. 534 /// 535 /// \pre \p RC is a user-defined register class (as opposed as one 536 /// generated by TableGen). 537 /// 538 /// \note The mapping RC -> RegBank could be built while adding the 539 /// coverage for the register banks. However, we do not do it, because, 540 /// at least for now, we only need this information for register classes 541 /// that are used in the description of instruction. In other words, 542 /// there are just a handful of them and we do not want to waste space. 543 /// 544 /// \todo This should be TableGen'ed. 545 virtual const RegisterBank & 546 getRegBankFromRegClass(const TargetRegisterClass &RC) const { 547 llvm_unreachable("The target must override this method"); 548 } 549 550 /// Get the cost of a copy from \p B to \p A, or put differently, 551 /// get the cost of A = COPY B. Since register banks may cover 552 /// different size, \p Size specifies what will be the size in bits 553 /// that will be copied around. 554 /// 555 /// \note Since this is a copy, both registers have the same size. 556 virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, 557 unsigned Size) const { 558 // Optimistically assume that copies are coalesced. I.e., when 559 // they are on the same bank, they are free. 560 // Otherwise assume a non-zero cost of 1. The targets are supposed 561 // to override that properly anyway if they care. 562 return &A != &B; 563 } 564 565 /// Constrain the (possibly generic) virtual register \p Reg to \p RC. 566 /// 567 /// \pre \p Reg is a virtual register that either has a bank or a class. 568 /// \returns The constrained register class, or nullptr if there is none. 569 /// \note This is a generic variant of MachineRegisterInfo::constrainRegClass 570 static const TargetRegisterClass * 571 constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, 572 MachineRegisterInfo &MRI); 573 574 /// Identifier used when the related instruction mapping instance 575 /// is generated by target independent code. 576 /// Make sure not to use that identifier to avoid possible collision. 577 static const unsigned DefaultMappingID; 578 579 /// Identifier used when the related instruction mapping instance 580 /// is generated by the default constructor. 581 /// Make sure not to use that identifier. 582 static const unsigned InvalidMappingID; 583 584 /// Get the mapping of the different operands of \p MI 585 /// on the register bank. 586 /// This mapping should be the direct translation of \p MI. 587 /// In other words, when \p MI is mapped with the returned mapping, 588 /// only the register banks of the operands of \p MI need to be updated. 589 /// In particular, neither the opcode nor the type of \p MI needs to be 590 /// updated for this direct mapping. 591 /// 592 /// The target independent implementation gives a mapping based on 593 /// the register classes for the target specific opcode. 594 /// It uses the ID RegisterBankInfo::DefaultMappingID for that mapping. 595 /// Make sure you do not use that ID for the alternative mapping 596 /// for MI. See getInstrAlternativeMappings for the alternative 597 /// mappings. 598 /// 599 /// For instance, if \p MI is a vector add, the mapping should 600 /// not be a scalarization of the add. 601 /// 602 /// \post returnedVal.verify(MI). 603 /// 604 /// \note If returnedVal does not verify MI, this would probably mean 605 /// that the target does not support that instruction. 606 virtual InstructionMapping getInstrMapping(const MachineInstr &MI) const; 607 608 /// Get the alternative mappings for \p MI. 609 /// Alternative in the sense different from getInstrMapping. 610 virtual InstructionMappings 611 getInstrAlternativeMappings(const MachineInstr &MI) const; 612 613 /// Get the possible mapping for \p MI. 614 /// A mapping defines where the different operands may live and at what cost. 615 /// For instance, let us consider: 616 /// v0(16) = G_ADD <2 x i8> v1, v2 617 /// The possible mapping could be: 618 /// 619 /// {/*ID*/VectorAdd, /*Cost*/1, /*v0*/{(0xFFFF, VPR)}, /*v1*/{(0xFFFF, VPR)}, 620 /// /*v2*/{(0xFFFF, VPR)}} 621 /// {/*ID*/ScalarAddx2, /*Cost*/2, /*v0*/{(0x00FF, GPR),(0xFF00, GPR)}, 622 /// /*v1*/{(0x00FF, GPR),(0xFF00, GPR)}, 623 /// /*v2*/{(0x00FF, GPR),(0xFF00, GPR)}} 624 /// 625 /// \note The first alternative of the returned mapping should be the 626 /// direct translation of \p MI current form. 627 /// 628 /// \post !returnedVal.empty(). 629 InstructionMappings getInstrPossibleMappings(const MachineInstr &MI) const; 630 631 /// Apply \p OpdMapper.getInstrMapping() to \p OpdMapper.getMI(). 632 /// After this call \p OpdMapper.getMI() may not be valid anymore. 633 /// \p OpdMapper.getInstrMapping().getID() carries the information of 634 /// what has been chosen to map \p OpdMapper.getMI(). This ID is set 635 /// by the various getInstrXXXMapping method. 636 /// 637 /// Therefore, getting the mapping and applying it should be kept in 638 /// sync. 639 void applyMapping(const OperandsMapper &OpdMapper) const { 640 // The only mapping we know how to handle is the default mapping. 641 if (OpdMapper.getInstrMapping().getID() == DefaultMappingID) 642 return applyDefaultMapping(OpdMapper); 643 // For other mapping, the target needs to do the right thing. 644 // If that means calling applyDefaultMapping, fine, but this 645 // must be explicitly stated. 646 applyMappingImpl(OpdMapper); 647 } 648 649 /// Get the size in bits of \p Reg. 650 /// Utility method to get the size of any registers. Unlike 651 /// MachineRegisterInfo::getSize, the register does not need to be a 652 /// virtual register. 653 /// 654 /// \pre \p Reg != 0 (NoRegister). 655 static unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, 656 const TargetRegisterInfo &TRI); 657 658 /// Check that information hold by this instance make sense for the 659 /// given \p TRI. 660 /// 661 /// \note This method does not check anything when assertions are disabled. 662 /// 663 /// \return True is the check was successful. 664 bool verify(const TargetRegisterInfo &TRI) const; 665 }; 666 667 inline raw_ostream & 668 operator<<(raw_ostream &OS, 669 const RegisterBankInfo::PartialMapping &PartMapping) { 670 PartMapping.print(OS); 671 return OS; 672 } 673 674 inline raw_ostream & 675 operator<<(raw_ostream &OS, const RegisterBankInfo::ValueMapping &ValMapping) { 676 ValMapping.print(OS); 677 return OS; 678 } 679 680 inline raw_ostream & 681 operator<<(raw_ostream &OS, 682 const RegisterBankInfo::InstructionMapping &InstrMapping) { 683 InstrMapping.print(OS); 684 return OS; 685 } 686 687 inline raw_ostream & 688 operator<<(raw_ostream &OS, const RegisterBankInfo::OperandsMapper &OpdMapper) { 689 OpdMapper.print(OS, /*ForDebug*/ false); 690 return OS; 691 } 692 693 /// Hashing function for PartialMapping. 694 /// It is required for the hashing of ValueMapping. 695 hash_code hash_value(const RegisterBankInfo::PartialMapping &PartMapping); 696 } // End namespace llvm. 697 698 #endif 699