1 /* illegal.s Test file for AArch64 instructions that should be rejected 2 by the assembler. 3 4 Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. 5 6 This file is part of GAS. 7 8 GAS is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the license, or 11 (at your option) any later version. 12 13 GAS is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; see the file COPYING3. If not, 20 see <http://www.gnu.org/licenses/>. */ 21 22 .text 23 // For urecpe and ursqrte, only 2s and 4s are accepted qualifiers. 24 urecpe v0.1d, v7.1d 25 urecpe v0.2d, v7.2d 26 ursqrte v0.1d, v7.1d 27 ursqrte v0.2d, v7.2d 28 29 // For AdvSIMD (across) instructions, there are restraints on the register type and qualifiers. 30 saddlv b7, v31.8b 31 saddlv d7, v31.2s 32 saddlv q7, v31.2d 33 smaxv s7, v31.2s 34 sminv d7, v31.2d 35 fmaxv h7, v31.2h 36 fmaxv s7, v31.4h 37 fminv d7, v31.2d 38 39 abs b0, b31 40 neg b0, b31 41 abs h0, h31 42 neg h0, h31 43 abs s0, s31 44 neg s0, s31 45 46 fcvt s0, s0 47 48 bfm w0, w1, 8, 43 49 ubfm w0, x1, 8, 31 50 51 aese v1.8b, v2.8b 52 sha1h s7, d31 53 sha1h q7, d31 54 sha1su1 v7.4s, v7.2s 55 sha256su0 v7.2d, v7.2d 56 sha1c q7, q3, v7.4s 57 sha1p s7, q8, v9.4s 58 sha1m v8.4s, v7.4s, q8 59 sha1su0 v0.2d, v1.2d, v2.2d 60 sha256h q7, s2, v8.4s 61 62 pmull v7.8b, v15.8b, v31.8b 63 pmull v7.1q, v15.1q, v31.1d 64 pmull2 v7.8h, v15.8b, v31.8b 65 pmull2 v7.1q, v15.2d, v31.1q 66 67 ld2 {v1.4h, v0.4h}, [x1] 68 strb x0, [sp, x1, lsl #0] 69 strb w7, [x30, x0, lsl] 70 strb w7, [x30, x0, lsl #1] 71 ldtr x7, [x15, 266] 72 sttr x7, [x15, #1]! 73 stxrb x2, w1, [sp] 74 stxp w2, x3, w4, [x0] 75 ldxp w3, x4, [x30] 76 77 st2 {v4.2d, v5.2d}, [x3, #3] 78 st2 {v4.2d, v5.2d, v6.2d}, [x3] 79 st1 {v4.2d, v6.2d, v8.2d}, [x3] 80 st3 {v4.2d, v6.2d}, [x3] 81 st4 {v4.2d, v6.2d}, [x3] 82 st2 {v4.2d, v6.2d, v8.2d, v10.2d}, [x3] 83 st2 {v4.2d, v6.2d, v8.2d, v10.2d}, [x3], 48 84 85 ext v0.8b, v1.8b, v2.8b, 8 86 ext v0.16b, v1.16b, v2.16b, 20 87 88 tbz w0, #40, 0x17c 89 90 svc 91 92 fmov v1.D[0], x0 93 fmov v2.S[2], x0 94 fmov v2.S[1], x0 95 fmov v2.D[1], w0 96 97 smaddl w0, w1, w2, x3 98 smaddl x0, x1, w2, x3 99 smaddl x0, w1, x2, x3 100 smaddl x0, w1, w2, w3 101 102 ld1 {v1.s, v2.s}[1], [x3] 103 st1 {v2.s, v3.s}[1], [x4] 104 ld2 {v1.s, v2.s, v3.s}[1], [x3] 105 st2 {v2.s, v2.s, v3.s}[1], [x4] 106 ld3 {v1.s, v2.s, v3.s, v4.s}[1], [x3] 107 st3 {v2.s, v3.s, v4.s, v5.s}[1], [x4] 108 ld4 {v1.s}[1], [x3] 109 st4 {v2.s}[1], [x4] 110 111 ld2 {v1.b, v3.b}[1], [x3] 112 st2 {v2.b, v4.b}[1], [x4] 113 ld3 {v1.b, v3.b, v5.b}[1], [x3] 114 st3 {v2.b, v4.b, v6.b}[1], [x4] 115 ld4 {v1.b, v3.b, v5.b, v7.b}[1], [x3] 116 st4 {v2.b, v4.b, v6.b, v8.b}[1], [x4] 117 118 ld1 {v1.q}[1], [x3] 119 120 ld1r {v1.4s, v3.4s}, [x3] 121 ld1r {v1.4s, v2.4s, v3.4s}, [x3] 122 ld2r {v1.4s, v2.4s, v3.4s}, [x3] 123 ld3r {v1.4s, v2.4s, v3.4s, v4.4s}, [x3] 124 ld4r {v1.4s}, [x3] 125 126 ld1r {v1.4s, v3.4s}, [x3], x4 127 ld1r {v1.4s, v2.4s, v3.4s}, [x3], x4 128 ld2r {v1.4s, v2.4s, v3.4s}, [x3], x4 129 ld3r {v1.4s, v2.4s, v3.4s, v4.4s}, [x3], x4 130 ld4r {v1.4s}, [x3], x4 131 132 ld1r {v1.4s}, [x3], #1 133 ld1r {v1.4s, v2.4s}, [x3], #8 134 ld2r {v1.4s, v2.4s}, [x3], #4 135 ld3r {v1.4s, v2.4s, v3.4s}, [x3], #16 136 ld4r {v1.4s, v2.4s, v3.4s, v4.4s}, [x3], #32 137 138 addp s1, v2.2s 139 addp s1, v2.2d 140 addp d1, v2.2s 141 fmaxp s1, v2.4s 142 143 add s1, s2, s3 144 cmhi d1, d2, s3 145 146 shll v0.8h, v1.8b, 16 147 shll2 v0.2d, v1.4s, 16 148 149 dup s1, v2.d[1] 150 dup s1, v2.s[4] 151 mov s1, v2.h[1] 152 153 clrex #16 154 155 msr daif, w5 156 mrs w15, midr_el1 157 mrs x0, dummy 158 159 sshr v0.4s, v1.4s, #0 160 sshr v0.4s, v1.4s, #33 161 sshr v0.4h, v1.4h, #20 162 163 shl v0.4s, v1.4s, #32 164 fcvtzs v0.2h, v1.2h, #2 165 uqshrn v0.2s, v1.2d, 33 166 uqrshrn v0.2s, v1.2s, 32 167 sshll v8.8h, v2.8b, #8 168 169 sysl x7, #10, C15, C7, #11 170 sysl w7, #1, C15, C7, #1 171 172 dsb dummy 173 dmb #16 174 isb osh 175 176 prfm 0x2f, LABEL1 177 prfm pldl3strm, [sp, #8]! 178 prfm pldl3strm, [sp], #8 179 prfm pldl3strm, [sp, w0, sxtw #3]! 180 prfm pldl3strm, =0x100 181 182 sttr x0, LABEL1 183 sttr x0, [sp, #16]! 184 sttr x0, [sp], #16 185 sttr x0, [sp, x1] 186 187 ldur x0, LABEL1 188 ldur x0, [sp, #16]! 189 ldur x0, [sp], #16 190 ldur x0, [sp, x1] 191 192 ldr b0, =0x100 193 ldr h0, LABEL1 194 195 ic ivau 196 ic ivau, w0 197 ic ialluis, xzr 198 ic ialluis, x0 199 sys #0, c0, c0, 0, w0 200 msr spsel, #16 201 msr cptr_el2, #15 202 203 movz x1,#:abs_g2:u48, lsl #16 204 movz x1, 0xddee, lsl #8 205 movz w1,#:abs_g2:u48 206 movz w1,#:abs_g3:u48 207 movk x1,#:abs_g1_s:s12 208 209 movi v0.4s, #256 210 movi v0.2d, #0xabcdef 211 212 bic v0.4s, #255, msl #8 213 bic v0.4s, #512 214 bic v0.4s, #1, lsl #31 215 // bic v0.4h, #1, lsl #16 216 217 orr v0.4s, #255, msl #8 218 orr v0.4s, #512 219 220 movi v0.4s, #127, lsl #4 221 movi v0.4s, #127, msl #24 222 // movi v0.4h, #127, lsl #16 223 224 mvni v0.4s, #127, lsl #4 225 mvni v0.4s, #127, msl #24 226 // mvni v0.4h, #127, lsl #16 227 228 fmov v0.2s, #3.1415926 229 fmov v0.4s, #3.1415926 230 fmov v0.2d, #3.1415926 231 fmov x0, #1.0 232 fmov w0, w1 233 234 msr #5, #0 235 msr SPSel, #2 236 237 tbl v0.16b, {v1.16b, v3.16b, v5.16b}, v2.16b 238 tbx v0.8b, {v1.16b, v3.16b, v5.16b, v7.16b}, v2.8b 239 240 // Alternating register list forms are no longer available A64 ISA 241 242 .macro ldst2_reg_list_post_imm_reg_64 inst type postreg 243 \inst\()2 {v0.\type, v2.\type}, [x0], #16 244 \inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #32 245 .ifnb \postreg 246 \inst\()2 {v0.\type, v2.\type}, [x0], \postreg 247 \inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg 248 .endif 249 .endm 250 251 .macro ldst2_reg_list_post_imm_reg_128 inst type postreg 252 \inst\()2 {v0.\type, v2.\type}, [x0], #32 253 \inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #64 254 .ifnb \postreg 255 \inst\()2 {v0.\type, v2.\type}, [x0], \postreg 256 \inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg 257 .endif 258 .endm 259 260 .irp instr ld,st 261 .irp bits_64 8b, 4h, 2s 262 ldst2_reg_list_post_imm_reg_64 \instr \bits_64 x7 263 .endr 264 .endr 265 266 .irp instr ld,st 267 .irp bits_128 16b, 8h, 4s, 2d 268 ldst2_reg_list_post_imm_reg_128 \instr \bits_128 x7 269 .endr 270 .endr 271 272 .macro ldst34_reg_list_post_imm_reg_64 inst type postreg 273 \inst\()3 {v0.\type, v2.\type, v4.\type}, [x0], #24 274 \inst\()4 {v0.\type, v2.\type, v4.\type, v6.\type}, [x0], #32 275 \inst\()3 {v0.\type, v2.\type, v4.\type}, [x0], \postreg 276 \inst\()4 {v0.\type, v2.\type, v4.\type, v6.\type}, [x0], \postreg 277 .endm 278 279 .macro ldst34_reg_list_post_imm_reg_128 inst type postreg 280 \inst\()3 {v0.\type, v2.\type, v4.\type}, [x0], #48 281 \inst\()4 {v0.\type, v2.\type, v4.\type, v6.\type}, [x0], #64 282 \inst\()3 {v0.\type, v2.\type, v4.\type}, [x0], \postreg 283 \inst\()4 {v0.\type, v2.\type, v4.\type, v6.\type}, [x0], \postreg 284 .endm 285 286 .irp instr ld,st 287 .irp bits_64 8b, 4h, 2s 288 ldst34_reg_list_post_imm_reg_64 \instr \bits_64 x7 289 .endr 290 .endr 291 292 .irp instr ld,st 293 .irp bits_128 16b, 8h, 4s, 2d 294 ldst34_reg_list_post_imm_reg_128 \instr \bits_128 x7 295 .endr 296 .endr 297 298 // LD1R expects one register only. 299 300 ld1r {v0.8b, v1.8b}, [x0], #1 301 ld1r {v0.16b, v1.16b}, [x0], #1 302 ld1r {v0.4h, v1.4h}, [x0], #2 303 ld1r {v0.8h, v1.8h}, [x0], #2 304 ld1r {v0.2s, v1.2s}, [x0], #4 305 ld1r {v0.4s, v1.4s}, [x0], #4 306 ld1r {v0.1d, v1.1d}, [x0], #8 307 ld1r {v0.2d, v1.2d}, [x0], #8 308 309 .macro ldstn_index_rep_H_altreg_imm inst index type rep 310 \inst\()2\rep {v0.\type, v2.\type}\index, [x0], #4 311 \inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0], #6 312 \inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0], #8 313 .endm 314 315 .irp instr, ld, st 316 ldstn_index_rep_H_altreg_imm \instr index="[1]" type=h rep="" 317 .ifnc \instr, st 318 .irp types 4h, 8h 319 ldstn_index_rep_H_altreg_imm \instr index="" type=\types rep="r" 320 .endr 321 .endif 322 .endr 323 324 .macro ldstn_index_rep_S_altreg_imm inst index type rep 325 \inst\()2\rep {v0.\type, v2.\type}\index, [x0], #8 326 \inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0], #12 327 \inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0], #16 328 .endm 329 330 .irp instr, ld, st 331 ldstn_index_rep_S_altreg_imm \instr index="[1]" type=s rep="" 332 .ifnc \instr, st 333 .irp types 2s, 4s 334 ldstn_index_rep_S_altreg_imm \instr index="" type=\types rep="r" 335 .endr 336 .endif 337 .endr 338 339 .macro ldstn_index_rep_D_altreg_imm inst index type rep 340 \inst\()2\rep {v0.\type, v2.\type}\index, [x0], #16 341 \inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0], #24 342 \inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0], #32 343 .endm 344 345 .irp instr, ld, st 346 ldstn_index_rep_D_altreg_imm \instr index="[1]" type=d rep="" 347 .ifnc \instr, st 348 .irp types 1d, 2d 349 ldstn_index_rep_D_altreg_imm \instr index="" type=\types rep="r" 350 .endr 351 .endif 352 .endr 353 354 .irp type 8b, 16b, 4h, 8h, 2s, 4s, 1d, 2d 355 ld1r {v0.\type, v1.\type}, [x0], x7 356 .endr 357 358 .macro ldstn_index_rep_reg_altreg inst index type rep postreg 359 \inst\()2\rep {v0.\type, v2.\type}\index, [x0], \postreg 360 \inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0], \postreg 361 \inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0], \postreg 362 .endm 363 364 .irp instr, ld, st 365 .irp itypes b,h,s,d 366 ldstn_index_rep_reg_altreg \instr index="[1]" type=\itypes rep="" postreg=x7 367 .endr 368 .ifnc \instr, st 369 .irp types 8b, 16b, 4h, 8h, 2s, 4s, 1d, 2d 370 ldstn_index_rep_reg_altreg \instr index="" type=\types rep="r" postreg=x7 371 .endr 372 .endif 373 .endr 374 375 .macro ldnstn_reg_list type inst index rep 376 .ifb \index 377 .ifnb \rep 378 \inst\()1\rep {v0.\type, v1.\type}\index, [x0] 379 .endif 380 .endif 381 382 .ifnc \type, B 383 \inst\()2\rep {v0.\type, v2.\type}\index, [x0] 384 .endif 385 386 .ifnc \type, B 387 \inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0] 388 .endif 389 390 .ifnc \type, B 391 \inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0] 392 .endif 393 394 .endm 395 396 ldnstn_reg_list type="8B", inst="ld" index="" rep="" 397 ldnstn_reg_list type="8B", inst="st" index="" rep="" 398 399 ldnstn_reg_list type="16B", inst="ld" index="" rep="" 400 ldnstn_reg_list type="16B", inst="st" index="" rep="" 401 402 ldnstn_reg_list type="4H", inst="ld" index="" rep="" 403 ldnstn_reg_list type="4H", inst="st" index="" rep="" 404 405 ldnstn_reg_list type="8H", inst="ld" index="" rep="" 406 ldnstn_reg_list type="8H", inst="st" index="" rep="" 407 408 ldnstn_reg_list type="2S", inst="ld" index="" rep="" 409 ldnstn_reg_list type="2S", inst="st" index="" rep="" 410 411 ldnstn_reg_list type="4S", inst="ld" index="" rep="" 412 ldnstn_reg_list type="4S", inst="st" index="" rep="" 413 414 ldnstn_reg_list type="2D", inst="ld" index="" rep="" 415 ldnstn_reg_list type="2D", inst="st" index="" rep="" 416 417 ldnstn_reg_list type="B", inst="ld" index="[1]" rep="" 418 ldnstn_reg_list type="B", inst="st" index="[1]" rep="" 419 420 ldnstn_reg_list type="B", inst="ld" index="[1]" rep="" 421 ldnstn_reg_list type="B", inst="st" index="[1]" rep="" 422 423 ldnstn_reg_list type="H", inst="ld" index="[1]" rep="" 424 ldnstn_reg_list type="H", inst="st" index="[1]" rep="" 425 426 ldnstn_reg_list type="H", inst="ld" index="[1]" rep="" 427 ldnstn_reg_list type="H", inst="st" index="[1]" rep="" 428 429 ldnstn_reg_list type="S", inst="ld" index="[1]" rep="" 430 ldnstn_reg_list type="S", inst="st" index="[1]" rep="" 431 432 ldnstn_reg_list type="S", inst="ld" index="[1]" rep="" 433 ldnstn_reg_list type="S", inst="st" index="[1]" rep="" 434 435 ldnstn_reg_list type="D", inst="ld" index="[1]" rep="" 436 ldnstn_reg_list type="D", inst="st" index="[1]" rep="" 437 438 ldnstn_reg_list type="8B", inst="ld" index="" rep="r" 439 440 ldnstn_reg_list type="16B", inst="ld" index="" rep="r" 441 442 ldnstn_reg_list type="4H", inst="ld" index="" rep="r" 443 444 ldnstn_reg_list type="8H", inst="ld" index="" rep="r" 445 446 ldnstn_reg_list type="2S", inst="ld" index="" rep="r" 447 448 ldnstn_reg_list type="4S", inst="ld" index="" rep="r" 449 450 ldnstn_reg_list type="1D", inst="ld" index="" rep="r" 451 452 ldnstn_reg_list type="2D", inst="ld" index="" rep="r" 453 454 pmull v0.1q, v1.1d, v2.1d 455 pmull2 v0.1q, v1.2d, v2.2d 456 457 // #<fbits> out of range 458 .irp instr, scvtf, ucvtf 459 \instr d0, w1, 33 460 \instr s0, w0, 33 461 \instr d0, x1, 65 462 \instr s0, x1, 65 463 .endr 464 .irp instr, fcvtzs, fcvtzu 465 \instr w1, d0, 33 466 \instr w0, s0, 33 467 \instr x1, d0, 65 468 \instr x1, s0, 65 469 .endr 470 471 // Invalid instruction. 472 mockup-op 473 474 475 ldrh w0, [x1, x2, lsr #1] 476 477 add w0, w1, w2, ror #1 478 sub w0, w1, w2, asr #32 479 eor w0, w1, w2, ror #32 480 481 add x0, x1, #20, LSL #16 482 add x0, x1, #20, UXTX #12 483 add x0, x1, #20, LSR 484 add x0, x1, #20, LSL 485 486 ldnp h7, h15, [x0, #2] 487 ldnp b15, b31, [x0], #4 488 ldnp h0, h1, [x0, #6]! 489 490 uqrshrn h0, s1, #63 491 sqshl b7, b15, #8 492 493 bfxil w7, w15, #15, #30 494 bfi x3, x7, #31, #48 495 496 str x1,page_table_count 497 498 prfm PLDL3KEEP, [x9, x15, sxtx #2] 499 500 mrs x5, S1_0_C17_C8_0 501 msr S3_1_C13_C15_1, x7 502 msr S3_1_C11_C15_-1, x7 503 msr S3_1_11_15_1, x7 504 505 // MOVI (alias of ORR immediate) is no longer supported. 506 movi w1, #15 507 .set u48, 0xaabbccddeeff 508 509 uxtb x7, x15 510 uxth x7, x15 511 uxtw x7, x15 512 sxtb w15, xzr 513 sxth w15, xzr 514 sxtw w15, xzr 515 516 mov w0, v0.b[0] 517 mov w0, v0.h[0] 518 mov w0, v0.d[0] 519 mov x0, v0.b[0] 520 mov x0, v0.h[0] 521 mov x0, v0.s[0] 522 523 uabdl2 v20.4S, v12.8H, v29.8 524 525 movi d1, 0xffff, lsl #16 526 527 ST3 {v18.D-v20.D}[0],[x28],x 528 ST1 {v7.B}[2],[x4],x 529 ST1 {v22.1D-v25.1D},[x10],x 530 531 ldr w0, [x0]! 532 ldr w0, [x0], {127} 533 534 orr x0, x0, #0xff, lsl #1 535 orr x0. x0, #0xff, lsl #1 536 orr x0, x0, #0xff lsl #1 537 538 mov x0, ##5 539 540 msr daifset, x0 541 msr daifclr, x0 542 543 fmov s0, #0x11 544 fmov s0, #0xC0280000C1400000 545 fmov d0, #0xC02f800000000000 546 547 // No 16-byte relocation 548 ldr q0, =one_label 549 550 ands w0, w24, #0xffeefffffffffffd 551 552 one_label: 553 554 cinc w0, w1, al 555 cinc w0, w1, nv 556 cset w0, al 557 cset w0, nv 558 cinv w0, w1, al 559 cinv w0, w1, nv 560 csetm w0, al 561 csetm w0, nv 562 cneg w0, w1, al 563 cneg w0, w1, nv 564 565 mrs x5, S4_0_C12_C8_0 566 mrs x6, S0_8_C11_C7_5 567 mrs x7, S1_1_C16_C6_6 568 mrs x8, S2_2_C15_C16_7 569 mrs x9, S3_3_C14_C15_8 570
