1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains small standalone helper functions and enum definitions for 11 // the X86 target useful for the compiler back-end and the MC libraries. 12 // As such, it deliberately does not include references to LLVM core 13 // code gen types, passes, etc.. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #ifndef X86BASEINFO_H 18 #define X86BASEINFO_H 19 20 #include "X86MCTargetDesc.h" 21 #include "llvm/Support/DataTypes.h" 22 #include <cassert> 23 24 namespace llvm { 25 26 namespace X86 { 27 // Enums for memory operand decoding. Each memory operand is represented with 28 // a 5 operand sequence in the form: 29 // [BaseReg, ScaleAmt, IndexReg, Disp, Segment] 30 // These enums help decode this. 31 enum { 32 AddrBaseReg = 0, 33 AddrScaleAmt = 1, 34 AddrIndexReg = 2, 35 AddrDisp = 3, 36 37 /// AddrSegmentReg - The operand # of the segment in the memory operand. 38 AddrSegmentReg = 4, 39 40 /// AddrNumOperands - Total number of operands in a memory reference. 41 AddrNumOperands = 5 42 }; 43 } // end namespace X86; 44 45 46 /// X86II - This namespace holds all of the target specific flags that 47 /// instruction info tracks. 48 /// 49 namespace X86II { 50 /// Target Operand Flag enum. 51 enum TOF { 52 //===------------------------------------------------------------------===// 53 // X86 Specific MachineOperand flags. 54 55 MO_NO_FLAG, 56 57 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 58 /// relocation of: 59 /// SYMBOL_LABEL + [. - PICBASELABEL] 60 MO_GOT_ABSOLUTE_ADDRESS, 61 62 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 63 /// immediate should get the value of the symbol minus the PIC base label: 64 /// SYMBOL_LABEL - PICBASELABEL 65 MO_PIC_BASE_OFFSET, 66 67 /// MO_GOT - On a symbol operand this indicates that the immediate is the 68 /// offset to the GOT entry for the symbol name from the base of the GOT. 69 /// 70 /// See the X86-64 ELF ABI supplement for more details. 71 /// SYMBOL_LABEL @GOT 72 MO_GOT, 73 74 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 75 /// the offset to the location of the symbol name from the base of the GOT. 76 /// 77 /// See the X86-64 ELF ABI supplement for more details. 78 /// SYMBOL_LABEL @GOTOFF 79 MO_GOTOFF, 80 81 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 82 /// offset to the GOT entry for the symbol name from the current code 83 /// location. 84 /// 85 /// See the X86-64 ELF ABI supplement for more details. 86 /// SYMBOL_LABEL @GOTPCREL 87 MO_GOTPCREL, 88 89 /// MO_PLT - On a symbol operand this indicates that the immediate is 90 /// offset to the PLT entry of symbol name from the current code location. 91 /// 92 /// See the X86-64 ELF ABI supplement for more details. 93 /// SYMBOL_LABEL @PLT 94 MO_PLT, 95 96 /// MO_TLSGD - On a symbol operand this indicates that the immediate is 97 /// some TLS offset. 98 /// 99 /// See 'ELF Handling for Thread-Local Storage' for more details. 100 /// SYMBOL_LABEL @TLSGD 101 MO_TLSGD, 102 103 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 104 /// some TLS offset. 105 /// 106 /// See 'ELF Handling for Thread-Local Storage' for more details. 107 /// SYMBOL_LABEL @GOTTPOFF 108 MO_GOTTPOFF, 109 110 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 111 /// some TLS offset. 112 /// 113 /// See 'ELF Handling for Thread-Local Storage' for more details. 114 /// SYMBOL_LABEL @INDNTPOFF 115 MO_INDNTPOFF, 116 117 /// MO_TPOFF - On a symbol operand this indicates that the immediate is 118 /// some TLS offset. 119 /// 120 /// See 'ELF Handling for Thread-Local Storage' for more details. 121 /// SYMBOL_LABEL @TPOFF 122 MO_TPOFF, 123 124 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 125 /// some TLS offset. 126 /// 127 /// See 'ELF Handling for Thread-Local Storage' for more details. 128 /// SYMBOL_LABEL @NTPOFF 129 MO_NTPOFF, 130 131 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 132 /// reference is actually to the "__imp_FOO" symbol. This is used for 133 /// dllimport linkage on windows. 134 MO_DLLIMPORT, 135 136 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the 137 /// reference is actually to the "FOO$stub" symbol. This is used for calls 138 /// and jumps to external functions on Tiger and earlier. 139 MO_DARWIN_STUB, 140 141 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the 142 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a 143 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 144 MO_DARWIN_NONLAZY, 145 146 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates 147 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is 148 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 149 MO_DARWIN_NONLAZY_PIC_BASE, 150 151 /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this 152 /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE", 153 /// which is a PIC-base-relative reference to a hidden dyld lazy pointer 154 /// stub. 155 MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE, 156 157 /// MO_TLVP - On a symbol operand this indicates that the immediate is 158 /// some TLS offset. 159 /// 160 /// This is the TLS offset for the Darwin TLS mechanism. 161 MO_TLVP, 162 163 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate 164 /// is some TLS offset from the picbase. 165 /// 166 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode. 167 MO_TLVP_PIC_BASE 168 }; 169 170 enum { 171 //===------------------------------------------------------------------===// 172 // Instruction encodings. These are the standard/most common forms for X86 173 // instructions. 174 // 175 176 // PseudoFrm - This represents an instruction that is a pseudo instruction 177 // or one that has not been implemented yet. It is illegal to code generate 178 // it, but tolerated for intermediate implementation stages. 179 Pseudo = 0, 180 181 /// Raw - This form is for instructions that don't have any operands, so 182 /// they are just a fixed opcode value, like 'leave'. 183 RawFrm = 1, 184 185 /// AddRegFrm - This form is used for instructions like 'push r32' that have 186 /// their one register operand added to their opcode. 187 AddRegFrm = 2, 188 189 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 190 /// to specify a destination, which in this case is a register. 191 /// 192 MRMDestReg = 3, 193 194 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 195 /// to specify a destination, which in this case is memory. 196 /// 197 MRMDestMem = 4, 198 199 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 200 /// to specify a source, which in this case is a register. 201 /// 202 MRMSrcReg = 5, 203 204 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 205 /// to specify a source, which in this case is memory. 206 /// 207 MRMSrcMem = 6, 208 209 /// MRM[0-7][rm] - These forms are used to represent instructions that use 210 /// a Mod/RM byte, and use the middle field to hold extended opcode 211 /// information. In the intel manual these are represented as /0, /1, ... 212 /// 213 214 // First, instructions that operate on a register r/m operand... 215 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 216 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 217 218 // Next, instructions that operate on a memory r/m operand... 219 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 220 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 221 222 // MRMInitReg - This form is used for instructions whose source and 223 // destinations are the same register. 224 MRMInitReg = 32, 225 226 //// MRM_C1 - A mod/rm byte of exactly 0xC1. 227 MRM_C1 = 33, 228 MRM_C2 = 34, 229 MRM_C3 = 35, 230 MRM_C4 = 36, 231 MRM_C8 = 37, 232 MRM_C9 = 38, 233 MRM_E8 = 39, 234 MRM_F0 = 40, 235 MRM_F8 = 41, 236 MRM_F9 = 42, 237 MRM_D0 = 45, 238 MRM_D1 = 46, 239 240 /// RawFrmImm8 - This is used for the ENTER instruction, which has two 241 /// immediates, the first of which is a 16-bit immediate (specified by 242 /// the imm encoding) and the second is a 8-bit fixed value. 243 RawFrmImm8 = 43, 244 245 /// RawFrmImm16 - This is used for CALL FAR instructions, which have two 246 /// immediates, the first of which is a 16 or 32-bit immediate (specified by 247 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD 248 /// manual, this operand is described as pntr16:32 and pntr16:16 249 RawFrmImm16 = 44, 250 251 FormMask = 63, 252 253 //===------------------------------------------------------------------===// 254 // Actual flags... 255 256 // OpSize - Set if this instruction requires an operand size prefix (0x66), 257 // which most often indicates that the instruction operates on 16 bit data 258 // instead of 32 bit data. 259 OpSize = 1 << 6, 260 261 // AsSize - Set if this instruction requires an operand size prefix (0x67), 262 // which most often indicates that the instruction address 16 bit address 263 // instead of 32 bit address (or 32 bit address in 64 bit mode). 264 AdSize = 1 << 7, 265 266 //===------------------------------------------------------------------===// 267 // Op0Mask - There are several prefix bytes that are used to form two byte 268 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 269 // used to obtain the setting of this field. If no bits in this field is 270 // set, there is no prefix byte for obtaining a multibyte opcode. 271 // 272 Op0Shift = 8, 273 Op0Mask = 0x1F << Op0Shift, 274 275 // TB - TwoByte - Set if this instruction has a two byte opcode, which 276 // starts with a 0x0F byte before the real opcode. 277 TB = 1 << Op0Shift, 278 279 // REP - The 0xF3 prefix byte indicating repetition of the following 280 // instruction. 281 REP = 2 << Op0Shift, 282 283 // D8-DF - These escape opcodes are used by the floating point unit. These 284 // values must remain sequential. 285 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 286 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 287 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 288 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 289 290 // XS, XD - These prefix codes are for single and double precision scalar 291 // floating point operations performed in the SSE registers. 292 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 293 294 // T8, TA, A6, A7 - Prefix after the 0x0F prefix. 295 T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 296 A6 = 15 << Op0Shift, A7 = 16 << Op0Shift, 297 298 // TF - Prefix before and after 0x0F 299 TF = 17 << Op0Shift, 300 301 //===------------------------------------------------------------------===// 302 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 303 // They are used to specify GPRs and SSE registers, 64-bit operand size, 304 // etc. We only cares about REX.W and REX.R bits and only the former is 305 // statically determined. 306 // 307 REXShift = Op0Shift + 5, 308 REX_W = 1 << REXShift, 309 310 //===------------------------------------------------------------------===// 311 // This three-bit field describes the size of an immediate operand. Zero is 312 // unused so that we can tell if we forgot to set a value. 313 ImmShift = REXShift + 1, 314 ImmMask = 7 << ImmShift, 315 Imm8 = 1 << ImmShift, 316 Imm8PCRel = 2 << ImmShift, 317 Imm16 = 3 << ImmShift, 318 Imm16PCRel = 4 << ImmShift, 319 Imm32 = 5 << ImmShift, 320 Imm32PCRel = 6 << ImmShift, 321 Imm64 = 7 << ImmShift, 322 323 //===------------------------------------------------------------------===// 324 // FP Instruction Classification... Zero is non-fp instruction. 325 326 // FPTypeMask - Mask for all of the FP types... 327 FPTypeShift = ImmShift + 3, 328 FPTypeMask = 7 << FPTypeShift, 329 330 // NotFP - The default, set for instructions that do not use FP registers. 331 NotFP = 0 << FPTypeShift, 332 333 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 334 ZeroArgFP = 1 << FPTypeShift, 335 336 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 337 OneArgFP = 2 << FPTypeShift, 338 339 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 340 // result back to ST(0). For example, fcos, fsqrt, etc. 341 // 342 OneArgFPRW = 3 << FPTypeShift, 343 344 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 345 // explicit argument, storing the result to either ST(0) or the implicit 346 // argument. For example: fadd, fsub, fmul, etc... 347 TwoArgFP = 4 << FPTypeShift, 348 349 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 350 // explicit argument, but have no destination. Example: fucom, fucomi, ... 351 CompareFP = 5 << FPTypeShift, 352 353 // CondMovFP - "2 operand" floating point conditional move instructions. 354 CondMovFP = 6 << FPTypeShift, 355 356 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 357 SpecialFP = 7 << FPTypeShift, 358 359 // Lock prefix 360 LOCKShift = FPTypeShift + 3, 361 LOCK = 1 << LOCKShift, 362 363 // Segment override prefixes. Currently we just need ability to address 364 // stuff in gs and fs segments. 365 SegOvrShift = LOCKShift + 1, 366 SegOvrMask = 3 << SegOvrShift, 367 FS = 1 << SegOvrShift, 368 GS = 2 << SegOvrShift, 369 370 // Execution domain for SSE instructions in bits 23, 24. 371 // 0 in bits 23-24 means normal, non-SSE instruction. 372 SSEDomainShift = SegOvrShift + 2, 373 374 OpcodeShift = SSEDomainShift + 2, 375 376 //===------------------------------------------------------------------===// 377 /// VEX - The opcode prefix used by AVX instructions 378 VEXShift = OpcodeShift + 8, 379 VEX = 1U << 0, 380 381 /// VEX_W - Has a opcode specific functionality, but is used in the same 382 /// way as REX_W is for regular SSE instructions. 383 VEX_W = 1U << 1, 384 385 /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2 386 /// address instructions in SSE are represented as 3 address ones in AVX 387 /// and the additional register is encoded in VEX_VVVV prefix. 388 VEX_4V = 1U << 2, 389 390 /// VEX_I8IMM - Specifies that the last register used in a AVX instruction, 391 /// must be encoded in the i8 immediate field. This usually happens in 392 /// instructions with 4 operands. 393 VEX_I8IMM = 1U << 3, 394 395 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current 396 /// instruction uses 256-bit wide registers. This is usually auto detected 397 /// if a VR256 register is used, but some AVX instructions also have this 398 /// field marked when using a f256 memory references. 399 VEX_L = 1U << 4, 400 401 // VEX_LIG - Specifies that this instruction ignores the L-bit in the VEX 402 // prefix. Usually used for scalar instructions. Needed by disassembler. 403 VEX_LIG = 1U << 5, 404 405 /// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the 406 /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents 407 /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction 408 /// storing a classifier in the imm8 field. To simplify our implementation, 409 /// we handle this by storeing the classifier in the opcode field and using 410 /// this flag to indicate that the encoder should do the wacky 3DNow! thing. 411 Has3DNow0F0FOpcode = 1U << 6 412 }; 413 414 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 415 // specified machine instruction. 416 // 417 static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { 418 return TSFlags >> X86II::OpcodeShift; 419 } 420 421 static inline bool hasImm(uint64_t TSFlags) { 422 return (TSFlags & X86II::ImmMask) != 0; 423 } 424 425 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field 426 /// of the specified instruction. 427 static inline unsigned getSizeOfImm(uint64_t TSFlags) { 428 switch (TSFlags & X86II::ImmMask) { 429 default: assert(0 && "Unknown immediate size"); 430 case X86II::Imm8: 431 case X86II::Imm8PCRel: return 1; 432 case X86II::Imm16: 433 case X86II::Imm16PCRel: return 2; 434 case X86II::Imm32: 435 case X86II::Imm32PCRel: return 4; 436 case X86II::Imm64: return 8; 437 } 438 } 439 440 /// isImmPCRel - Return true if the immediate of the specified instruction's 441 /// TSFlags indicates that it is pc relative. 442 static inline unsigned isImmPCRel(uint64_t TSFlags) { 443 switch (TSFlags & X86II::ImmMask) { 444 default: assert(0 && "Unknown immediate size"); 445 case X86II::Imm8PCRel: 446 case X86II::Imm16PCRel: 447 case X86II::Imm32PCRel: 448 return true; 449 case X86II::Imm8: 450 case X86II::Imm16: 451 case X86II::Imm32: 452 case X86II::Imm64: 453 return false; 454 } 455 } 456 457 /// getMemoryOperandNo - The function returns the MCInst operand # for the 458 /// first field of the memory operand. If the instruction doesn't have a 459 /// memory operand, this returns -1. 460 /// 461 /// Note that this ignores tied operands. If there is a tied register which 462 /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only 463 /// counted as one operand. 464 /// 465 static inline int getMemoryOperandNo(uint64_t TSFlags) { 466 switch (TSFlags & X86II::FormMask) { 467 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this form"); 468 default: assert(0 && "Unknown FormMask value in getMemoryOperandNo!"); 469 case X86II::Pseudo: 470 case X86II::RawFrm: 471 case X86II::AddRegFrm: 472 case X86II::MRMDestReg: 473 case X86II::MRMSrcReg: 474 case X86II::RawFrmImm8: 475 case X86II::RawFrmImm16: 476 return -1; 477 case X86II::MRMDestMem: 478 return 0; 479 case X86II::MRMSrcMem: { 480 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 481 unsigned FirstMemOp = 1; 482 if (HasVEX_4V) 483 ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV). 484 485 // FIXME: Maybe lea should have its own form? This is a horrible hack. 486 //if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r || 487 // Opcode == X86::LEA16r || Opcode == X86::LEA32r) 488 return FirstMemOp; 489 } 490 case X86II::MRM0r: case X86II::MRM1r: 491 case X86II::MRM2r: case X86II::MRM3r: 492 case X86II::MRM4r: case X86II::MRM5r: 493 case X86II::MRM6r: case X86II::MRM7r: 494 return -1; 495 case X86II::MRM0m: case X86II::MRM1m: 496 case X86II::MRM2m: case X86II::MRM3m: 497 case X86II::MRM4m: case X86II::MRM5m: 498 case X86II::MRM6m: case X86II::MRM7m: 499 return 0; 500 case X86II::MRM_C1: 501 case X86II::MRM_C2: 502 case X86II::MRM_C3: 503 case X86II::MRM_C4: 504 case X86II::MRM_C8: 505 case X86II::MRM_C9: 506 case X86II::MRM_E8: 507 case X86II::MRM_F0: 508 case X86II::MRM_F8: 509 case X86II::MRM_F9: 510 case X86II::MRM_D0: 511 case X86II::MRM_D1: 512 return -1; 513 } 514 } 515 516 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or 517 /// higher) register? e.g. r8, xmm8, xmm13, etc. 518 static inline bool isX86_64ExtendedReg(unsigned RegNo) { 519 switch (RegNo) { 520 default: break; 521 case X86::R8: case X86::R9: case X86::R10: case X86::R11: 522 case X86::R12: case X86::R13: case X86::R14: case X86::R15: 523 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: 524 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: 525 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: 526 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: 527 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: 528 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: 529 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: 530 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15: 531 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11: 532 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15: 533 case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11: 534 case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15: 535 return true; 536 } 537 return false; 538 } 539 540 static inline bool isX86_64NonExtLowByteReg(unsigned reg) { 541 return (reg == X86::SPL || reg == X86::BPL || 542 reg == X86::SIL || reg == X86::DIL); 543 } 544 } 545 546 } // end namespace llvm; 547 548 #endif 549
