1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 15 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 16 17 #include "PPC.h" 18 #include "PPCRegisterInfo.h" 19 #include "llvm/CodeGen/TargetInstrInfo.h" 20 21 #define GET_INSTRINFO_HEADER 22 #include "PPCGenInstrInfo.inc" 23 24 namespace llvm { 25 26 /// PPCII - This namespace holds all of the PowerPC target-specific 27 /// per-instruction flags. These must match the corresponding definitions in 28 /// PPC.td and PPCInstrFormats.td. 29 namespace PPCII { 30 enum { 31 // PPC970 Instruction Flags. These flags describe the characteristics of the 32 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of 33 // raw machine instructions. 34 35 /// PPC970_First - This instruction starts a new dispatch group, so it will 36 /// always be the first one in the group. 37 PPC970_First = 0x1, 38 39 /// PPC970_Single - This instruction starts a new dispatch group and 40 /// terminates it, so it will be the sole instruction in the group. 41 PPC970_Single = 0x2, 42 43 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring 44 /// two dispatch pipes to be available to issue. 45 PPC970_Cracked = 0x4, 46 47 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that 48 /// an instruction is issued to. 49 PPC970_Shift = 3, 50 PPC970_Mask = 0x07 << PPC970_Shift 51 }; 52 enum PPC970_Unit { 53 /// These are the various PPC970 execution unit pipelines. Each instruction 54 /// is one of these. 55 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction 56 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit 57 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit 58 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit 59 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit 60 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU 61 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit 62 PPC970_BRU = 7 << PPC970_Shift // Branch Unit 63 }; 64 65 enum { 66 /// Shift count to bypass PPC970 flags 67 NewDef_Shift = 6, 68 69 /// The VSX instruction that uses VSX register (vs0-vs63), instead of VMX 70 /// register (v0-v31). 71 UseVSXReg = 0x1 << NewDef_Shift, 72 /// This instruction is an X-Form memory operation. 73 XFormMemOp = 0x1 << (NewDef_Shift+1) 74 }; 75 } // end namespace PPCII 76 77 // Instructions that have an immediate form might be convertible to that 78 // form if the correct input is a result of a load immediate. In order to 79 // know whether the transformation is special, we might need to know some 80 // of the details of the two forms. 81 struct ImmInstrInfo { 82 // Is the immediate field in the immediate form signed or unsigned? 83 uint64_t SignedImm : 1; 84 // Does the immediate need to be a multiple of some value? 85 uint64_t ImmMustBeMultipleOf : 5; 86 // Is R0/X0 treated specially by the original r+r instruction? 87 // If so, in which operand? 88 uint64_t ZeroIsSpecialOrig : 3; 89 // Is R0/X0 treated specially by the new r+i instruction? 90 // If so, in which operand? 91 uint64_t ZeroIsSpecialNew : 3; 92 // Is the operation commutative? 93 uint64_t IsCommutative : 1; 94 // The operand number to check for load immediate. 95 uint64_t ConstantOpNo : 3; 96 // The operand number for the immediate. 97 uint64_t ImmOpNo : 3; 98 // The opcode of the new instruction. 99 uint64_t ImmOpcode : 16; 100 // The size of the immediate. 101 uint64_t ImmWidth : 5; 102 // The immediate should be truncated to N bits. 103 uint64_t TruncateImmTo : 5; 104 }; 105 106 // Information required to convert an instruction to just a materialized 107 // immediate. 108 struct LoadImmediateInfo { 109 unsigned Imm : 16; 110 unsigned Is64Bit : 1; 111 unsigned SetCR : 1; 112 }; 113 114 class PPCSubtarget; 115 class PPCInstrInfo : public PPCGenInstrInfo { 116 PPCSubtarget &Subtarget; 117 const PPCRegisterInfo RI; 118 119 void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, 120 int FrameIdx, const TargetRegisterClass *RC, 121 SmallVectorImpl<MachineInstr *> &NewMIs) const; 122 void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, 123 unsigned DestReg, int FrameIdx, 124 const TargetRegisterClass *RC, 125 SmallVectorImpl<MachineInstr *> &NewMIs) const; 126 bool transformToImmForm(MachineInstr &MI, const ImmInstrInfo &III, 127 unsigned ConstantOpNo, int64_t Imm) const; 128 MachineInstr *getConstantDefMI(MachineInstr &MI, unsigned &ConstOp, 129 bool &SeenIntermediateUse) const; 130 const unsigned *getStoreOpcodesForSpillArray() const; 131 const unsigned *getLoadOpcodesForSpillArray() const; 132 virtual void anchor(); 133 134 protected: 135 /// Commutes the operands in the given instruction. 136 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2. 137 /// 138 /// Do not call this method for a non-commutable instruction or for 139 /// non-commutable pair of operand indices OpIdx1 and OpIdx2. 140 /// Even though the instruction is commutable, the method may still 141 /// fail to commute the operands, null pointer is returned in such cases. 142 /// 143 /// For example, we can commute rlwimi instructions, but only if the 144 /// rotate amt is zero. We also have to munge the immediates a bit. 145 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 146 unsigned OpIdx1, 147 unsigned OpIdx2) const override; 148 149 public: 150 explicit PPCInstrInfo(PPCSubtarget &STI); 151 152 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 153 /// such, whenever a client has an instance of instruction info, it should 154 /// always be able to get register info as well (through this method). 155 /// 156 const PPCRegisterInfo &getRegisterInfo() const { return RI; } 157 158 bool isXFormMemOp(unsigned Opcode) const { 159 return get(Opcode).TSFlags & PPCII::XFormMemOp; 160 } 161 162 ScheduleHazardRecognizer * 163 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 164 const ScheduleDAG *DAG) const override; 165 ScheduleHazardRecognizer * 166 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 167 const ScheduleDAG *DAG) const override; 168 169 unsigned getInstrLatency(const InstrItineraryData *ItinData, 170 const MachineInstr &MI, 171 unsigned *PredCost = nullptr) const override; 172 173 int getOperandLatency(const InstrItineraryData *ItinData, 174 const MachineInstr &DefMI, unsigned DefIdx, 175 const MachineInstr &UseMI, 176 unsigned UseIdx) const override; 177 int getOperandLatency(const InstrItineraryData *ItinData, 178 SDNode *DefNode, unsigned DefIdx, 179 SDNode *UseNode, unsigned UseIdx) const override { 180 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, 181 UseNode, UseIdx); 182 } 183 184 bool hasLowDefLatency(const TargetSchedModel &SchedModel, 185 const MachineInstr &DefMI, 186 unsigned DefIdx) const override { 187 // Machine LICM should hoist all instructions in low-register-pressure 188 // situations; none are sufficiently free to justify leaving in a loop 189 // body. 190 return false; 191 } 192 193 bool useMachineCombiner() const override { 194 return true; 195 } 196 197 /// Return true when there is potentially a faster code sequence 198 /// for an instruction chain ending in <Root>. All potential patterns are 199 /// output in the <Pattern> array. 200 bool getMachineCombinerPatterns( 201 MachineInstr &Root, 202 SmallVectorImpl<MachineCombinerPattern> &P) const override; 203 204 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override; 205 206 bool isCoalescableExtInstr(const MachineInstr &MI, 207 unsigned &SrcReg, unsigned &DstReg, 208 unsigned &SubIdx) const override; 209 unsigned isLoadFromStackSlot(const MachineInstr &MI, 210 int &FrameIndex) const override; 211 bool isReallyTriviallyReMaterializable(const MachineInstr &MI, 212 AliasAnalysis *AA) const override; 213 unsigned isStoreToStackSlot(const MachineInstr &MI, 214 int &FrameIndex) const override; 215 216 bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, 217 unsigned &SrcOpIdx2) const override; 218 219 void insertNoop(MachineBasicBlock &MBB, 220 MachineBasicBlock::iterator MI) const override; 221 222 223 // Branch analysis. 224 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 225 MachineBasicBlock *&FBB, 226 SmallVectorImpl<MachineOperand> &Cond, 227 bool AllowModify) const override; 228 unsigned removeBranch(MachineBasicBlock &MBB, 229 int *BytesRemoved = nullptr) const override; 230 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 231 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 232 const DebugLoc &DL, 233 int *BytesAdded = nullptr) const override; 234 235 // Select analysis. 236 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 237 unsigned, unsigned, int &, int &, int &) const override; 238 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 239 const DebugLoc &DL, unsigned DstReg, 240 ArrayRef<MachineOperand> Cond, unsigned TrueReg, 241 unsigned FalseReg) const override; 242 243 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 244 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, 245 bool KillSrc) const override; 246 247 void storeRegToStackSlot(MachineBasicBlock &MBB, 248 MachineBasicBlock::iterator MBBI, 249 unsigned SrcReg, bool isKill, int FrameIndex, 250 const TargetRegisterClass *RC, 251 const TargetRegisterInfo *TRI) const override; 252 253 void loadRegFromStackSlot(MachineBasicBlock &MBB, 254 MachineBasicBlock::iterator MBBI, 255 unsigned DestReg, int FrameIndex, 256 const TargetRegisterClass *RC, 257 const TargetRegisterInfo *TRI) const override; 258 259 unsigned getStoreOpcodeForSpill(unsigned Reg, 260 const TargetRegisterClass *RC = nullptr) const; 261 262 unsigned getLoadOpcodeForSpill(unsigned Reg, 263 const TargetRegisterClass *RC = nullptr) const; 264 265 bool 266 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 267 268 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, 269 MachineRegisterInfo *MRI) const override; 270 271 // If conversion by predication (only supported by some branch instructions). 272 // All of the profitability checks always return true; it is always 273 // profitable to use the predicated branches. 274 bool isProfitableToIfCvt(MachineBasicBlock &MBB, 275 unsigned NumCycles, unsigned ExtraPredCycles, 276 BranchProbability Probability) const override { 277 return true; 278 } 279 280 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 281 unsigned NumT, unsigned ExtraT, 282 MachineBasicBlock &FMBB, 283 unsigned NumF, unsigned ExtraF, 284 BranchProbability Probability) const override; 285 286 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 287 BranchProbability Probability) const override { 288 return true; 289 } 290 291 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 292 MachineBasicBlock &FMBB) const override { 293 return false; 294 } 295 296 // Predication support. 297 bool isPredicated(const MachineInstr &MI) const override; 298 299 bool isUnpredicatedTerminator(const MachineInstr &MI) const override; 300 301 bool PredicateInstruction(MachineInstr &MI, 302 ArrayRef<MachineOperand> Pred) const override; 303 304 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 305 ArrayRef<MachineOperand> Pred2) const override; 306 307 bool DefinesPredicate(MachineInstr &MI, 308 std::vector<MachineOperand> &Pred) const override; 309 310 bool isPredicable(const MachineInstr &MI) const override; 311 312 // Comparison optimization. 313 314 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, 315 unsigned &SrcReg2, int &Mask, int &Value) const override; 316 317 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, 318 unsigned SrcReg2, int Mask, int Value, 319 const MachineRegisterInfo *MRI) const override; 320 321 /// GetInstSize - Return the number of bytes of code the specified 322 /// instruction may be. This returns the maximum number of bytes. 323 /// 324 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 325 326 void getNoop(MCInst &NopInst) const override; 327 328 std::pair<unsigned, unsigned> 329 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 330 331 ArrayRef<std::pair<unsigned, const char *>> 332 getSerializableDirectMachineOperandTargetFlags() const override; 333 334 ArrayRef<std::pair<unsigned, const char *>> 335 getSerializableBitmaskMachineOperandTargetFlags() const override; 336 337 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction. 338 bool expandVSXMemPseudo(MachineInstr &MI) const; 339 340 // Lower pseudo instructions after register allocation. 341 bool expandPostRAPseudo(MachineInstr &MI) const override; 342 343 static bool isVFRegister(unsigned Reg) { 344 return Reg >= PPC::VF0 && Reg <= PPC::VF31; 345 } 346 static bool isVRRegister(unsigned Reg) { 347 return Reg >= PPC::V0 && Reg <= PPC::V31; 348 } 349 const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const; 350 static int getRecordFormOpcode(unsigned Opcode); 351 352 bool isTOCSaveMI(const MachineInstr &MI) const; 353 354 bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, 355 const unsigned PhiDepth) const; 356 357 /// Return true if the output of the instruction is always a sign-extended, 358 /// i.e. 0 to 31-th bits are same as 32-th bit. 359 bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const { 360 return isSignOrZeroExtended(MI, true, depth); 361 } 362 363 /// Return true if the output of the instruction is always zero-extended, 364 /// i.e. 0 to 31-th bits are all zeros 365 bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const { 366 return isSignOrZeroExtended(MI, false, depth); 367 } 368 369 bool convertToImmediateForm(MachineInstr &MI, 370 MachineInstr **KilledDef = nullptr) const; 371 void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const; 372 373 bool instrHasImmForm(const MachineInstr &MI, ImmInstrInfo &III) const; 374 }; 375 376 } 377 378 #endif 379
