1 //===- ARMAddressingModes.h - ARM Addressing Modes --------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the ARM addressing mode implementation stuff. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_TARGET_ARM_ARMADDRESSINGMODES_H 15 #define LLVM_TARGET_ARM_ARMADDRESSINGMODES_H 16 17 #include "llvm/ADT/APFloat.h" 18 #include "llvm/ADT/APInt.h" 19 #include "llvm/Support/MathExtras.h" 20 #include <cassert> 21 22 namespace llvm { 23 24 /// ARM_AM - ARM Addressing Mode Stuff 25 namespace ARM_AM { 26 enum ShiftOpc { 27 no_shift = 0, 28 asr, 29 lsl, 30 lsr, 31 ror, 32 rrx 33 }; 34 35 enum AddrOpc { 36 sub = 0, 37 add 38 }; 39 40 static inline const char *getAddrOpcStr(AddrOpc Op) { 41 return Op == sub ? "-" : ""; 42 } 43 44 static inline const char *getShiftOpcStr(ShiftOpc Op) { 45 switch (Op) { 46 default: assert(0 && "Unknown shift opc!"); 47 case ARM_AM::asr: return "asr"; 48 case ARM_AM::lsl: return "lsl"; 49 case ARM_AM::lsr: return "lsr"; 50 case ARM_AM::ror: return "ror"; 51 case ARM_AM::rrx: return "rrx"; 52 } 53 } 54 55 static inline unsigned getShiftOpcEncoding(ShiftOpc Op) { 56 switch (Op) { 57 default: assert(0 && "Unknown shift opc!"); 58 case ARM_AM::asr: return 2; 59 case ARM_AM::lsl: return 0; 60 case ARM_AM::lsr: return 1; 61 case ARM_AM::ror: return 3; 62 } 63 } 64 65 enum AMSubMode { 66 bad_am_submode = 0, 67 ia, 68 ib, 69 da, 70 db 71 }; 72 73 static inline const char *getAMSubModeStr(AMSubMode Mode) { 74 switch (Mode) { 75 default: assert(0 && "Unknown addressing sub-mode!"); 76 case ARM_AM::ia: return "ia"; 77 case ARM_AM::ib: return "ib"; 78 case ARM_AM::da: return "da"; 79 case ARM_AM::db: return "db"; 80 } 81 } 82 83 /// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits. 84 /// 85 static inline unsigned rotr32(unsigned Val, unsigned Amt) { 86 assert(Amt < 32 && "Invalid rotate amount"); 87 return (Val >> Amt) | (Val << ((32-Amt)&31)); 88 } 89 90 /// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits. 91 /// 92 static inline unsigned rotl32(unsigned Val, unsigned Amt) { 93 assert(Amt < 32 && "Invalid rotate amount"); 94 return (Val << Amt) | (Val >> ((32-Amt)&31)); 95 } 96 97 //===--------------------------------------------------------------------===// 98 // Addressing Mode #1: shift_operand with registers 99 //===--------------------------------------------------------------------===// 100 // 101 // This 'addressing mode' is used for arithmetic instructions. It can 102 // represent things like: 103 // reg 104 // reg [asr|lsl|lsr|ror|rrx] reg 105 // reg [asr|lsl|lsr|ror|rrx] imm 106 // 107 // This is stored three operands [rega, regb, opc]. The first is the base 108 // reg, the second is the shift amount (or reg0 if not present or imm). The 109 // third operand encodes the shift opcode and the imm if a reg isn't present. 110 // 111 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { 112 return ShOp | (Imm << 3); 113 } 114 static inline unsigned getSORegOffset(unsigned Op) { 115 return Op >> 3; 116 } 117 static inline ShiftOpc getSORegShOp(unsigned Op) { 118 return (ShiftOpc)(Op & 7); 119 } 120 121 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return 122 /// the 8-bit imm value. 123 static inline unsigned getSOImmValImm(unsigned Imm) { 124 return Imm & 0xFF; 125 } 126 /// getSOImmValRot - Given an encoded imm field for the reg/imm form, return 127 /// the rotate amount. 128 static inline unsigned getSOImmValRot(unsigned Imm) { 129 return (Imm >> 8) * 2; 130 } 131 132 /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand, 133 /// computing the rotate amount to use. If this immediate value cannot be 134 /// handled with a single shifter-op, determine a good rotate amount that will 135 /// take a maximal chunk of bits out of the immediate. 136 static inline unsigned getSOImmValRotate(unsigned Imm) { 137 // 8-bit (or less) immediates are trivially shifter_operands with a rotate 138 // of zero. 139 if ((Imm & ~255U) == 0) return 0; 140 141 // Use CTZ to compute the rotate amount. 142 unsigned TZ = CountTrailingZeros_32(Imm); 143 144 // Rotate amount must be even. Something like 0x200 must be rotated 8 bits, 145 // not 9. 146 unsigned RotAmt = TZ & ~1; 147 148 // If we can handle this spread, return it. 149 if ((rotr32(Imm, RotAmt) & ~255U) == 0) 150 return (32-RotAmt)&31; // HW rotates right, not left. 151 152 // For values like 0xF000000F, we should ignore the low 6 bits, then 153 // retry the hunt. 154 if (Imm & 63U) { 155 unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U); 156 unsigned RotAmt2 = TZ2 & ~1; 157 if ((rotr32(Imm, RotAmt2) & ~255U) == 0) 158 return (32-RotAmt2)&31; // HW rotates right, not left. 159 } 160 161 // Otherwise, we have no way to cover this span of bits with a single 162 // shifter_op immediate. Return a chunk of bits that will be useful to 163 // handle. 164 return (32-RotAmt)&31; // HW rotates right, not left. 165 } 166 167 /// getSOImmVal - Given a 32-bit immediate, if it is something that can fit 168 /// into an shifter_operand immediate operand, return the 12-bit encoding for 169 /// it. If not, return -1. 170 static inline int getSOImmVal(unsigned Arg) { 171 // 8-bit (or less) immediates are trivially shifter_operands with a rotate 172 // of zero. 173 if ((Arg & ~255U) == 0) return Arg; 174 175 unsigned RotAmt = getSOImmValRotate(Arg); 176 177 // If this cannot be handled with a single shifter_op, bail out. 178 if (rotr32(~255U, RotAmt) & Arg) 179 return -1; 180 181 // Encode this correctly. 182 return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8); 183 } 184 185 /// isSOImmTwoPartVal - Return true if the specified value can be obtained by 186 /// or'ing together two SOImmVal's. 187 static inline bool isSOImmTwoPartVal(unsigned V) { 188 // If this can be handled with a single shifter_op, bail out. 189 V = rotr32(~255U, getSOImmValRotate(V)) & V; 190 if (V == 0) 191 return false; 192 193 // If this can be handled with two shifter_op's, accept. 194 V = rotr32(~255U, getSOImmValRotate(V)) & V; 195 return V == 0; 196 } 197 198 /// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, 199 /// return the first chunk of it. 200 static inline unsigned getSOImmTwoPartFirst(unsigned V) { 201 return rotr32(255U, getSOImmValRotate(V)) & V; 202 } 203 204 /// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, 205 /// return the second chunk of it. 206 static inline unsigned getSOImmTwoPartSecond(unsigned V) { 207 // Mask out the first hunk. 208 V = rotr32(~255U, getSOImmValRotate(V)) & V; 209 210 // Take what's left. 211 assert(V == (rotr32(255U, getSOImmValRotate(V)) & V)); 212 return V; 213 } 214 215 /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed 216 /// by a left shift. Returns the shift amount to use. 217 static inline unsigned getThumbImmValShift(unsigned Imm) { 218 // 8-bit (or less) immediates are trivially immediate operand with a shift 219 // of zero. 220 if ((Imm & ~255U) == 0) return 0; 221 222 // Use CTZ to compute the shift amount. 223 return CountTrailingZeros_32(Imm); 224 } 225 226 /// isThumbImmShiftedVal - Return true if the specified value can be obtained 227 /// by left shifting a 8-bit immediate. 228 static inline bool isThumbImmShiftedVal(unsigned V) { 229 // If this can be handled with 230 V = (~255U << getThumbImmValShift(V)) & V; 231 return V == 0; 232 } 233 234 /// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed 235 /// by a left shift. Returns the shift amount to use. 236 static inline unsigned getThumbImm16ValShift(unsigned Imm) { 237 // 16-bit (or less) immediates are trivially immediate operand with a shift 238 // of zero. 239 if ((Imm & ~65535U) == 0) return 0; 240 241 // Use CTZ to compute the shift amount. 242 return CountTrailingZeros_32(Imm); 243 } 244 245 /// isThumbImm16ShiftedVal - Return true if the specified value can be 246 /// obtained by left shifting a 16-bit immediate. 247 static inline bool isThumbImm16ShiftedVal(unsigned V) { 248 // If this can be handled with 249 V = (~65535U << getThumbImm16ValShift(V)) & V; 250 return V == 0; 251 } 252 253 /// getThumbImmNonShiftedVal - If V is a value that satisfies 254 /// isThumbImmShiftedVal, return the non-shiftd value. 255 static inline unsigned getThumbImmNonShiftedVal(unsigned V) { 256 return V >> getThumbImmValShift(V); 257 } 258 259 260 /// getT2SOImmValSplat - Return the 12-bit encoded representation 261 /// if the specified value can be obtained by splatting the low 8 bits 262 /// into every other byte or every byte of a 32-bit value. i.e., 263 /// 00000000 00000000 00000000 abcdefgh control = 0 264 /// 00000000 abcdefgh 00000000 abcdefgh control = 1 265 /// abcdefgh 00000000 abcdefgh 00000000 control = 2 266 /// abcdefgh abcdefgh abcdefgh abcdefgh control = 3 267 /// Return -1 if none of the above apply. 268 /// See ARM Reference Manual A6.3.2. 269 static inline int getT2SOImmValSplatVal(unsigned V) { 270 unsigned u, Vs, Imm; 271 // control = 0 272 if ((V & 0xffffff00) == 0) 273 return V; 274 275 // If the value is zeroes in the first byte, just shift those off 276 Vs = ((V & 0xff) == 0) ? V >> 8 : V; 277 // Any passing value only has 8 bits of payload, splatted across the word 278 Imm = Vs & 0xff; 279 // Likewise, any passing values have the payload splatted into the 3rd byte 280 u = Imm | (Imm << 16); 281 282 // control = 1 or 2 283 if (Vs == u) 284 return (((Vs == V) ? 1 : 2) << 8) | Imm; 285 286 // control = 3 287 if (Vs == (u | (u << 8))) 288 return (3 << 8) | Imm; 289 290 return -1; 291 } 292 293 /// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the 294 /// specified value is a rotated 8-bit value. Return -1 if no rotation 295 /// encoding is possible. 296 /// See ARM Reference Manual A6.3.2. 297 static inline int getT2SOImmValRotateVal(unsigned V) { 298 unsigned RotAmt = CountLeadingZeros_32(V); 299 if (RotAmt >= 24) 300 return -1; 301 302 // If 'Arg' can be handled with a single shifter_op return the value. 303 if ((rotr32(0xff000000U, RotAmt) & V) == V) 304 return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7); 305 306 return -1; 307 } 308 309 /// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit 310 /// into a Thumb-2 shifter_operand immediate operand, return the 12-bit 311 /// encoding for it. If not, return -1. 312 /// See ARM Reference Manual A6.3.2. 313 static inline int getT2SOImmVal(unsigned Arg) { 314 // If 'Arg' is an 8-bit splat, then get the encoded value. 315 int Splat = getT2SOImmValSplatVal(Arg); 316 if (Splat != -1) 317 return Splat; 318 319 // If 'Arg' can be handled with a single shifter_op return the value. 320 int Rot = getT2SOImmValRotateVal(Arg); 321 if (Rot != -1) 322 return Rot; 323 324 return -1; 325 } 326 327 static inline unsigned getT2SOImmValRotate(unsigned V) { 328 if ((V & ~255U) == 0) return 0; 329 // Use CTZ to compute the rotate amount. 330 unsigned RotAmt = CountTrailingZeros_32(V); 331 return (32 - RotAmt) & 31; 332 } 333 334 static inline bool isT2SOImmTwoPartVal (unsigned Imm) { 335 unsigned V = Imm; 336 // Passing values can be any combination of splat values and shifter 337 // values. If this can be handled with a single shifter or splat, bail 338 // out. Those should be handled directly, not with a two-part val. 339 if (getT2SOImmValSplatVal(V) != -1) 340 return false; 341 V = rotr32 (~255U, getT2SOImmValRotate(V)) & V; 342 if (V == 0) 343 return false; 344 345 // If this can be handled as an immediate, accept. 346 if (getT2SOImmVal(V) != -1) return true; 347 348 // Likewise, try masking out a splat value first. 349 V = Imm; 350 if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1) 351 V &= ~0xff00ff00U; 352 else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1) 353 V &= ~0x00ff00ffU; 354 // If what's left can be handled as an immediate, accept. 355 if (getT2SOImmVal(V) != -1) return true; 356 357 // Otherwise, do not accept. 358 return false; 359 } 360 361 static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) { 362 assert (isT2SOImmTwoPartVal(Imm) && 363 "Immedate cannot be encoded as two part immediate!"); 364 // Try a shifter operand as one part 365 unsigned V = rotr32 (~255, getT2SOImmValRotate(Imm)) & Imm; 366 // If the rest is encodable as an immediate, then return it. 367 if (getT2SOImmVal(V) != -1) return V; 368 369 // Try masking out a splat value first. 370 if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1) 371 return Imm & 0xff00ff00U; 372 373 // The other splat is all that's left as an option. 374 assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1); 375 return Imm & 0x00ff00ffU; 376 } 377 378 static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) { 379 // Mask out the first hunk 380 Imm ^= getT2SOImmTwoPartFirst(Imm); 381 // Return what's left 382 assert (getT2SOImmVal(Imm) != -1 && 383 "Unable to encode second part of T2 two part SO immediate"); 384 return Imm; 385 } 386 387 388 //===--------------------------------------------------------------------===// 389 // Addressing Mode #2 390 //===--------------------------------------------------------------------===// 391 // 392 // This is used for most simple load/store instructions. 393 // 394 // addrmode2 := reg +/- reg shop imm 395 // addrmode2 := reg +/- imm12 396 // 397 // The first operand is always a Reg. The second operand is a reg if in 398 // reg/reg form, otherwise it's reg#0. The third field encodes the operation 399 // in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The 400 // fourth operand 16-17 encodes the index mode. 401 // 402 // If this addressing mode is a frame index (before prolog/epilog insertion 403 // and code rewriting), this operand will have the form: FI#, reg0, <offs> 404 // with no shift amount for the frame offset. 405 // 406 static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, 407 unsigned IdxMode = 0) { 408 assert(Imm12 < (1 << 12) && "Imm too large!"); 409 bool isSub = Opc == sub; 410 return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ; 411 } 412 static inline unsigned getAM2Offset(unsigned AM2Opc) { 413 return AM2Opc & ((1 << 12)-1); 414 } 415 static inline AddrOpc getAM2Op(unsigned AM2Opc) { 416 return ((AM2Opc >> 12) & 1) ? sub : add; 417 } 418 static inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) { 419 return (ShiftOpc)((AM2Opc >> 13) & 7); 420 } 421 static inline unsigned getAM2IdxMode(unsigned AM2Opc) { 422 return (AM2Opc >> 16); 423 } 424 425 426 //===--------------------------------------------------------------------===// 427 // Addressing Mode #3 428 //===--------------------------------------------------------------------===// 429 // 430 // This is used for sign-extending loads, and load/store-pair instructions. 431 // 432 // addrmode3 := reg +/- reg 433 // addrmode3 := reg +/- imm8 434 // 435 // The first operand is always a Reg. The second operand is a reg if in 436 // reg/reg form, otherwise it's reg#0. The third field encodes the operation 437 // in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the 438 // index mode. 439 440 /// getAM3Opc - This function encodes the addrmode3 opc field. 441 static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset, 442 unsigned IdxMode = 0) { 443 bool isSub = Opc == sub; 444 return ((int)isSub << 8) | Offset | (IdxMode << 9); 445 } 446 static inline unsigned char getAM3Offset(unsigned AM3Opc) { 447 return AM3Opc & 0xFF; 448 } 449 static inline AddrOpc getAM3Op(unsigned AM3Opc) { 450 return ((AM3Opc >> 8) & 1) ? sub : add; 451 } 452 static inline unsigned getAM3IdxMode(unsigned AM3Opc) { 453 return (AM3Opc >> 9); 454 } 455 456 //===--------------------------------------------------------------------===// 457 // Addressing Mode #4 458 //===--------------------------------------------------------------------===// 459 // 460 // This is used for load / store multiple instructions. 461 // 462 // addrmode4 := reg, <mode> 463 // 464 // The four modes are: 465 // IA - Increment after 466 // IB - Increment before 467 // DA - Decrement after 468 // DB - Decrement before 469 // For VFP instructions, only the IA and DB modes are valid. 470 471 static inline AMSubMode getAM4SubMode(unsigned Mode) { 472 return (AMSubMode)(Mode & 0x7); 473 } 474 475 static inline unsigned getAM4ModeImm(AMSubMode SubMode) { 476 return (int)SubMode; 477 } 478 479 //===--------------------------------------------------------------------===// 480 // Addressing Mode #5 481 //===--------------------------------------------------------------------===// 482 // 483 // This is used for coprocessor instructions, such as FP load/stores. 484 // 485 // addrmode5 := reg +/- imm8*4 486 // 487 // The first operand is always a Reg. The second operand encodes the 488 // operation in bit 8 and the immediate in bits 0-7. 489 490 /// getAM5Opc - This function encodes the addrmode5 opc field. 491 static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) { 492 bool isSub = Opc == sub; 493 return ((int)isSub << 8) | Offset; 494 } 495 static inline unsigned char getAM5Offset(unsigned AM5Opc) { 496 return AM5Opc & 0xFF; 497 } 498 static inline AddrOpc getAM5Op(unsigned AM5Opc) { 499 return ((AM5Opc >> 8) & 1) ? sub : add; 500 } 501 502 //===--------------------------------------------------------------------===// 503 // Addressing Mode #6 504 //===--------------------------------------------------------------------===// 505 // 506 // This is used for NEON load / store instructions. 507 // 508 // addrmode6 := reg with optional alignment 509 // 510 // This is stored in two operands [regaddr, align]. The first is the 511 // address register. The second operand is the value of the alignment 512 // specifier in bytes or zero if no explicit alignment. 513 // Valid alignments depend on the specific instruction. 514 515 //===--------------------------------------------------------------------===// 516 // NEON Modified Immediates 517 //===--------------------------------------------------------------------===// 518 // 519 // Several NEON instructions (e.g., VMOV) take a "modified immediate" 520 // vector operand, where a small immediate encoded in the instruction 521 // specifies a full NEON vector value. These modified immediates are 522 // represented here as encoded integers. The low 8 bits hold the immediate 523 // value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold 524 // the "Cmode" field of the instruction. The interfaces below treat the 525 // Op and Cmode values as a single 5-bit value. 526 527 static inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val) { 528 return (OpCmode << 8) | Val; 529 } 530 static inline unsigned getNEONModImmOpCmode(unsigned ModImm) { 531 return (ModImm >> 8) & 0x1f; 532 } 533 static inline unsigned getNEONModImmVal(unsigned ModImm) { 534 return ModImm & 0xff; 535 } 536 537 /// decodeNEONModImm - Decode a NEON modified immediate value into the 538 /// element value and the element size in bits. (If the element size is 539 /// smaller than the vector, it is splatted into all the elements.) 540 static inline uint64_t decodeNEONModImm(unsigned ModImm, unsigned &EltBits) { 541 unsigned OpCmode = getNEONModImmOpCmode(ModImm); 542 unsigned Imm8 = getNEONModImmVal(ModImm); 543 uint64_t Val = 0; 544 545 if (OpCmode == 0xe) { 546 // 8-bit vector elements 547 Val = Imm8; 548 EltBits = 8; 549 } else if ((OpCmode & 0xc) == 0x8) { 550 // 16-bit vector elements 551 unsigned ByteNum = (OpCmode & 0x6) >> 1; 552 Val = Imm8 << (8 * ByteNum); 553 EltBits = 16; 554 } else if ((OpCmode & 0x8) == 0) { 555 // 32-bit vector elements, zero with one byte set 556 unsigned ByteNum = (OpCmode & 0x6) >> 1; 557 Val = Imm8 << (8 * ByteNum); 558 EltBits = 32; 559 } else if ((OpCmode & 0xe) == 0xc) { 560 // 32-bit vector elements, one byte with low bits set 561 unsigned ByteNum = 1 + (OpCmode & 0x1); 562 Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum))); 563 EltBits = 32; 564 } else if (OpCmode == 0x1e) { 565 // 64-bit vector elements 566 for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) { 567 if ((ModImm >> ByteNum) & 1) 568 Val |= (uint64_t)0xff << (8 * ByteNum); 569 } 570 EltBits = 64; 571 } else { 572 assert(false && "Unsupported NEON immediate"); 573 } 574 return Val; 575 } 576 577 AMSubMode getLoadStoreMultipleSubMode(int Opcode); 578 579 //===--------------------------------------------------------------------===// 580 // Floating-point Immediates 581 // 582 static inline float getFPImmFloat(unsigned Imm) { 583 // We expect an 8-bit binary encoding of a floating-point number here. 584 union { 585 uint32_t I; 586 float F; 587 } FPUnion; 588 589 uint8_t Sign = (Imm >> 7) & 0x1; 590 uint8_t Exp = (Imm >> 4) & 0x7; 591 uint8_t Mantissa = Imm & 0xf; 592 593 // 8-bit FP iEEEE Float Encoding 594 // abcd efgh aBbbbbbc defgh000 00000000 00000000 595 // 596 // where B = NOT(b); 597 598 FPUnion.I = 0; 599 FPUnion.I |= Sign << 31; 600 FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; 601 FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; 602 FPUnion.I |= (Exp & 0x3) << 23; 603 FPUnion.I |= Mantissa << 19; 604 return FPUnion.F; 605 } 606 607 /// getFP32Imm - Return an 8-bit floating-point version of the 32-bit 608 /// floating-point value. If the value cannot be represented as an 8-bit 609 /// floating-point value, then return -1. 610 static inline int getFP32Imm(const APInt &Imm) { 611 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1; 612 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127 613 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits 614 615 // We can handle 4 bits of mantissa. 616 // mantissa = (16+UInt(e:f:g:h))/16. 617 if (Mantissa & 0x7ffff) 618 return -1; 619 Mantissa >>= 19; 620 if ((Mantissa & 0xf) != Mantissa) 621 return -1; 622 623 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3 624 if (Exp < -3 || Exp > 4) 625 return -1; 626 Exp = ((Exp+3) & 0x7) ^ 4; 627 628 return ((int)Sign << 7) | (Exp << 4) | Mantissa; 629 } 630 631 static inline int getFP32Imm(const APFloat &FPImm) { 632 return getFP32Imm(FPImm.bitcastToAPInt()); 633 } 634 635 /// getFP64Imm - Return an 8-bit floating-point version of the 64-bit 636 /// floating-point value. If the value cannot be represented as an 8-bit 637 /// floating-point value, then return -1. 638 static inline int getFP64Imm(const APInt &Imm) { 639 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1; 640 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023 641 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffULL; 642 643 // We can handle 4 bits of mantissa. 644 // mantissa = (16+UInt(e:f:g:h))/16. 645 if (Mantissa & 0xffffffffffffULL) 646 return -1; 647 Mantissa >>= 48; 648 if ((Mantissa & 0xf) != Mantissa) 649 return -1; 650 651 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3 652 if (Exp < -3 || Exp > 4) 653 return -1; 654 Exp = ((Exp+3) & 0x7) ^ 4; 655 656 return ((int)Sign << 7) | (Exp << 4) | Mantissa; 657 } 658 659 static inline int getFP64Imm(const APFloat &FPImm) { 660 return getFP64Imm(FPImm.bitcastToAPInt()); 661 } 662 663 } // end namespace ARM_AM 664 } // end namespace llvm 665 666 #endif 667 668
