1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that ARM uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "arm-isel" 16 #include "ARM.h" 17 #include "ARMCallingConv.h" 18 #include "ARMConstantPoolValue.h" 19 #include "ARMISelLowering.h" 20 #include "ARMMachineFunctionInfo.h" 21 #include "ARMPerfectShuffle.h" 22 #include "ARMRegisterInfo.h" 23 #include "ARMSubtarget.h" 24 #include "ARMTargetMachine.h" 25 #include "ARMTargetObjectFile.h" 26 #include "MCTargetDesc/ARMAddressingModes.h" 27 #include "llvm/CallingConv.h" 28 #include "llvm/Constants.h" 29 #include "llvm/Function.h" 30 #include "llvm/GlobalValue.h" 31 #include "llvm/Instruction.h" 32 #include "llvm/Instructions.h" 33 #include "llvm/Intrinsics.h" 34 #include "llvm/Type.h" 35 #include "llvm/CodeGen/CallingConvLower.h" 36 #include "llvm/CodeGen/IntrinsicLowering.h" 37 #include "llvm/CodeGen/MachineBasicBlock.h" 38 #include "llvm/CodeGen/MachineFrameInfo.h" 39 #include "llvm/CodeGen/MachineFunction.h" 40 #include "llvm/CodeGen/MachineInstrBuilder.h" 41 #include "llvm/CodeGen/MachineModuleInfo.h" 42 #include "llvm/CodeGen/MachineRegisterInfo.h" 43 #include "llvm/CodeGen/PseudoSourceValue.h" 44 #include "llvm/CodeGen/SelectionDAG.h" 45 #include "llvm/MC/MCSectionMachO.h" 46 #include "llvm/Target/TargetOptions.h" 47 #include "llvm/ADT/VectorExtras.h" 48 #include "llvm/ADT/StringExtras.h" 49 #include "llvm/ADT/Statistic.h" 50 #include "llvm/Support/CommandLine.h" 51 #include "llvm/Support/ErrorHandling.h" 52 #include "llvm/Support/MathExtras.h" 53 #include "llvm/Support/raw_ostream.h" 54 #include <sstream> 55 using namespace llvm; 56 57 STATISTIC(NumTailCalls, "Number of tail calls"); 58 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt"); 59 60 // This option should go away when tail calls fully work. 61 static cl::opt<bool> 62 EnableARMTailCalls("arm-tail-calls", cl::Hidden, 63 cl::desc("Generate tail calls (TEMPORARY OPTION)."), 64 cl::init(false)); 65 66 cl::opt<bool> 67 EnableARMLongCalls("arm-long-calls", cl::Hidden, 68 cl::desc("Generate calls via indirect call instructions"), 69 cl::init(false)); 70 71 static cl::opt<bool> 72 ARMInterworking("arm-interworking", cl::Hidden, 73 cl::desc("Enable / disable ARM interworking (for debugging only)"), 74 cl::init(true)); 75 76 namespace llvm { 77 class ARMCCState : public CCState { 78 public: 79 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF, 80 const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs, 81 LLVMContext &C, ParmContext PC) 82 : CCState(CC, isVarArg, MF, TM, locs, C) { 83 assert(((PC == Call) || (PC == Prologue)) && 84 "ARMCCState users must specify whether their context is call" 85 "or prologue generation."); 86 CallOrPrologue = PC; 87 } 88 }; 89 } 90 91 // The APCS parameter registers. 92 static const unsigned GPRArgRegs[] = { 93 ARM::R0, ARM::R1, ARM::R2, ARM::R3 94 }; 95 96 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT, 97 EVT PromotedBitwiseVT) { 98 if (VT != PromotedLdStVT) { 99 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote); 100 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(), 101 PromotedLdStVT.getSimpleVT()); 102 103 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote); 104 AddPromotedToType (ISD::STORE, VT.getSimpleVT(), 105 PromotedLdStVT.getSimpleVT()); 106 } 107 108 EVT ElemTy = VT.getVectorElementType(); 109 if (ElemTy != MVT::i64 && ElemTy != MVT::f64) 110 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom); 111 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); 112 if (ElemTy != MVT::i32) { 113 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand); 114 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand); 115 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand); 116 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand); 117 } 118 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom); 119 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom); 120 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal); 121 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal); 122 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand); 123 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand); 124 if (VT.isInteger()) { 125 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom); 126 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom); 127 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom); 128 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand); 129 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand); 130 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 131 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 132 setTruncStoreAction(VT.getSimpleVT(), 133 (MVT::SimpleValueType)InnerVT, Expand); 134 } 135 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand); 136 137 // Promote all bit-wise operations. 138 if (VT.isInteger() && VT != PromotedBitwiseVT) { 139 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote); 140 AddPromotedToType (ISD::AND, VT.getSimpleVT(), 141 PromotedBitwiseVT.getSimpleVT()); 142 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote); 143 AddPromotedToType (ISD::OR, VT.getSimpleVT(), 144 PromotedBitwiseVT.getSimpleVT()); 145 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote); 146 AddPromotedToType (ISD::XOR, VT.getSimpleVT(), 147 PromotedBitwiseVT.getSimpleVT()); 148 } 149 150 // Neon does not support vector divide/remainder operations. 151 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand); 152 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand); 153 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand); 154 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand); 155 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand); 156 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand); 157 } 158 159 void ARMTargetLowering::addDRTypeForNEON(EVT VT) { 160 addRegisterClass(VT, ARM::DPRRegisterClass); 161 addTypeForNEON(VT, MVT::f64, MVT::v2i32); 162 } 163 164 void ARMTargetLowering::addQRTypeForNEON(EVT VT) { 165 addRegisterClass(VT, ARM::QPRRegisterClass); 166 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); 167 } 168 169 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) { 170 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin()) 171 return new TargetLoweringObjectFileMachO(); 172 173 return new ARMElfTargetObjectFile(); 174 } 175 176 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 177 : TargetLowering(TM, createTLOF(TM)) { 178 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 179 RegInfo = TM.getRegisterInfo(); 180 Itins = TM.getInstrItineraryData(); 181 182 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 183 184 if (Subtarget->isTargetDarwin()) { 185 // Uses VFP for Thumb libfuncs if available. 186 if (Subtarget->isThumb() && Subtarget->hasVFP2()) { 187 // Single-precision floating-point arithmetic. 188 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); 189 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); 190 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp"); 191 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp"); 192 193 // Double-precision floating-point arithmetic. 194 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp"); 195 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp"); 196 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp"); 197 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp"); 198 199 // Single-precision comparisons. 200 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp"); 201 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp"); 202 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp"); 203 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp"); 204 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); 205 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); 206 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); 207 setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); 208 209 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 210 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); 211 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 212 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 213 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 214 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 215 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 216 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 217 218 // Double-precision comparisons. 219 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); 220 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp"); 221 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp"); 222 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp"); 223 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); 224 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); 225 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); 226 setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); 227 228 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 229 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); 230 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 231 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 232 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 233 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 234 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 235 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 236 237 // Floating-point to integer conversions. 238 // i64 conversions are done via library routines even when generating VFP 239 // instructions, so use the same ones. 240 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp"); 241 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp"); 242 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp"); 243 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp"); 244 245 // Conversions between floating types. 246 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp"); 247 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp"); 248 249 // Integer to floating-point conversions. 250 // i64 conversions are done via library routines even when generating VFP 251 // instructions, so use the same ones. 252 // FIXME: There appears to be some naming inconsistency in ARM libgcc: 253 // e.g., __floatunsidf vs. __floatunssidfvfp. 254 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp"); 255 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp"); 256 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp"); 257 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp"); 258 } 259 } 260 261 // These libcalls are not available in 32-bit. 262 setLibcallName(RTLIB::SHL_I128, 0); 263 setLibcallName(RTLIB::SRL_I128, 0); 264 setLibcallName(RTLIB::SRA_I128, 0); 265 266 if (Subtarget->isAAPCS_ABI()) { 267 // Double-precision floating-point arithmetic helper functions 268 // RTABI chapter 4.1.2, Table 2 269 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd"); 270 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv"); 271 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul"); 272 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub"); 273 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS); 274 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS); 275 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS); 276 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS); 277 278 // Double-precision floating-point comparison helper functions 279 // RTABI chapter 4.1.2, Table 3 280 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq"); 281 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 282 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq"); 283 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ); 284 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt"); 285 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 286 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple"); 287 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 288 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge"); 289 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 290 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt"); 291 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 292 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun"); 293 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 294 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun"); 295 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 296 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS); 297 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS); 298 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS); 299 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS); 300 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS); 301 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS); 302 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS); 303 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS); 304 305 // Single-precision floating-point arithmetic helper functions 306 // RTABI chapter 4.1.2, Table 4 307 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd"); 308 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv"); 309 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul"); 310 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub"); 311 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS); 312 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS); 313 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS); 314 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS); 315 316 // Single-precision floating-point comparison helper functions 317 // RTABI chapter 4.1.2, Table 5 318 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq"); 319 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 320 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq"); 321 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ); 322 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt"); 323 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 324 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple"); 325 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 326 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge"); 327 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 328 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt"); 329 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 330 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun"); 331 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 332 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun"); 333 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 334 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS); 335 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS); 336 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS); 337 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS); 338 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS); 339 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS); 340 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS); 341 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS); 342 343 // Floating-point to integer conversions. 344 // RTABI chapter 4.1.2, Table 6 345 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz"); 346 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz"); 347 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz"); 348 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz"); 349 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz"); 350 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz"); 351 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz"); 352 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz"); 353 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS); 354 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS); 355 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS); 356 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS); 357 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS); 358 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS); 359 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS); 360 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS); 361 362 // Conversions between floating types. 363 // RTABI chapter 4.1.2, Table 7 364 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f"); 365 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d"); 366 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS); 367 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS); 368 369 // Integer to floating-point conversions. 370 // RTABI chapter 4.1.2, Table 8 371 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d"); 372 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d"); 373 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d"); 374 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d"); 375 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f"); 376 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f"); 377 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f"); 378 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f"); 379 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS); 380 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS); 381 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS); 382 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS); 383 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS); 384 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS); 385 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS); 386 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS); 387 388 // Long long helper functions 389 // RTABI chapter 4.2, Table 9 390 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul"); 391 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod"); 392 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod"); 393 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl"); 394 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr"); 395 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr"); 396 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS); 397 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS); 398 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS); 399 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS); 400 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS); 401 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS); 402 403 // Integer division functions 404 // RTABI chapter 4.3.1 405 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv"); 406 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv"); 407 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv"); 408 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv"); 409 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv"); 410 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv"); 411 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS); 412 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS); 413 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS); 414 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS); 415 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS); 416 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS); 417 418 // Memory operations 419 // RTABI chapter 4.3.4 420 setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy"); 421 setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove"); 422 setLibcallName(RTLIB::MEMSET, "__aeabi_memset"); 423 } 424 425 // Use divmod compiler-rt calls for iOS 5.0 and later. 426 if (Subtarget->getTargetTriple().getOS() == Triple::IOS && 427 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) { 428 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4"); 429 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4"); 430 } 431 432 if (Subtarget->isThumb1Only()) 433 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass); 434 else 435 addRegisterClass(MVT::i32, ARM::GPRRegisterClass); 436 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 437 addRegisterClass(MVT::f32, ARM::SPRRegisterClass); 438 if (!Subtarget->isFPOnlySP()) 439 addRegisterClass(MVT::f64, ARM::DPRRegisterClass); 440 441 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 442 } 443 444 if (Subtarget->hasNEON()) { 445 addDRTypeForNEON(MVT::v2f32); 446 addDRTypeForNEON(MVT::v8i8); 447 addDRTypeForNEON(MVT::v4i16); 448 addDRTypeForNEON(MVT::v2i32); 449 addDRTypeForNEON(MVT::v1i64); 450 451 addQRTypeForNEON(MVT::v4f32); 452 addQRTypeForNEON(MVT::v2f64); 453 addQRTypeForNEON(MVT::v16i8); 454 addQRTypeForNEON(MVT::v8i16); 455 addQRTypeForNEON(MVT::v4i32); 456 addQRTypeForNEON(MVT::v2i64); 457 458 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but 459 // neither Neon nor VFP support any arithmetic operations on it. 460 setOperationAction(ISD::FADD, MVT::v2f64, Expand); 461 setOperationAction(ISD::FSUB, MVT::v2f64, Expand); 462 setOperationAction(ISD::FMUL, MVT::v2f64, Expand); 463 setOperationAction(ISD::FDIV, MVT::v2f64, Expand); 464 setOperationAction(ISD::FREM, MVT::v2f64, Expand); 465 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand); 466 setOperationAction(ISD::SETCC, MVT::v2f64, Expand); 467 setOperationAction(ISD::FNEG, MVT::v2f64, Expand); 468 setOperationAction(ISD::FABS, MVT::v2f64, Expand); 469 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand); 470 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); 471 setOperationAction(ISD::FCOS, MVT::v2f64, Expand); 472 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand); 473 setOperationAction(ISD::FPOW, MVT::v2f64, Expand); 474 setOperationAction(ISD::FLOG, MVT::v2f64, Expand); 475 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand); 476 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand); 477 setOperationAction(ISD::FEXP, MVT::v2f64, Expand); 478 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); 479 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); 480 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand); 481 setOperationAction(ISD::FRINT, MVT::v2f64, Expand); 482 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); 483 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand); 484 485 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand); 486 487 // Neon does not support some operations on v1i64 and v2i64 types. 488 setOperationAction(ISD::MUL, MVT::v1i64, Expand); 489 // Custom handling for some quad-vector types to detect VMULL. 490 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 491 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 492 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 493 // Custom handling for some vector types to avoid expensive expansions 494 setOperationAction(ISD::SDIV, MVT::v4i16, Custom); 495 setOperationAction(ISD::SDIV, MVT::v8i8, Custom); 496 setOperationAction(ISD::UDIV, MVT::v4i16, Custom); 497 setOperationAction(ISD::UDIV, MVT::v8i8, Custom); 498 setOperationAction(ISD::SETCC, MVT::v1i64, Expand); 499 setOperationAction(ISD::SETCC, MVT::v2i64, Expand); 500 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with 501 // a destination type that is wider than the source. 502 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); 503 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); 504 505 setTargetDAGCombine(ISD::INTRINSIC_VOID); 506 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); 507 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); 508 setTargetDAGCombine(ISD::SHL); 509 setTargetDAGCombine(ISD::SRL); 510 setTargetDAGCombine(ISD::SRA); 511 setTargetDAGCombine(ISD::SIGN_EXTEND); 512 setTargetDAGCombine(ISD::ZERO_EXTEND); 513 setTargetDAGCombine(ISD::ANY_EXTEND); 514 setTargetDAGCombine(ISD::SELECT_CC); 515 setTargetDAGCombine(ISD::BUILD_VECTOR); 516 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 517 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); 518 setTargetDAGCombine(ISD::STORE); 519 setTargetDAGCombine(ISD::FP_TO_SINT); 520 setTargetDAGCombine(ISD::FP_TO_UINT); 521 setTargetDAGCombine(ISD::FDIV); 522 523 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand); 524 } 525 526 computeRegisterProperties(); 527 528 // ARM does not have f32 extending load. 529 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 530 531 // ARM does not have i1 sign extending load. 532 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 533 534 // ARM supports all 4 flavors of integer indexed load / store. 535 if (!Subtarget->isThumb1Only()) { 536 for (unsigned im = (unsigned)ISD::PRE_INC; 537 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 538 setIndexedLoadAction(im, MVT::i1, Legal); 539 setIndexedLoadAction(im, MVT::i8, Legal); 540 setIndexedLoadAction(im, MVT::i16, Legal); 541 setIndexedLoadAction(im, MVT::i32, Legal); 542 setIndexedStoreAction(im, MVT::i1, Legal); 543 setIndexedStoreAction(im, MVT::i8, Legal); 544 setIndexedStoreAction(im, MVT::i16, Legal); 545 setIndexedStoreAction(im, MVT::i32, Legal); 546 } 547 } 548 549 // i64 operation support. 550 setOperationAction(ISD::MUL, MVT::i64, Expand); 551 setOperationAction(ISD::MULHU, MVT::i32, Expand); 552 if (Subtarget->isThumb1Only()) { 553 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 554 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 555 } 556 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops() 557 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP())) 558 setOperationAction(ISD::MULHS, MVT::i32, Expand); 559 560 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 561 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 562 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 563 setOperationAction(ISD::SRL, MVT::i64, Custom); 564 setOperationAction(ISD::SRA, MVT::i64, Custom); 565 566 if (!Subtarget->isThumb1Only()) { 567 // FIXME: We should do this for Thumb1 as well. 568 setOperationAction(ISD::ADDC, MVT::i32, Custom); 569 setOperationAction(ISD::ADDE, MVT::i32, Custom); 570 setOperationAction(ISD::SUBC, MVT::i32, Custom); 571 setOperationAction(ISD::SUBE, MVT::i32, Custom); 572 } 573 574 // ARM does not have ROTL. 575 setOperationAction(ISD::ROTL, MVT::i32, Expand); 576 setOperationAction(ISD::CTTZ, MVT::i32, Custom); 577 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 578 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) 579 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 580 581 // Only ARMv6 has BSWAP. 582 if (!Subtarget->hasV6Ops()) 583 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 584 585 // These are expanded into libcalls. 586 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) { 587 // v7M has a hardware divider 588 setOperationAction(ISD::SDIV, MVT::i32, Expand); 589 setOperationAction(ISD::UDIV, MVT::i32, Expand); 590 } 591 setOperationAction(ISD::SREM, MVT::i32, Expand); 592 setOperationAction(ISD::UREM, MVT::i32, Expand); 593 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 594 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 595 596 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 597 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 598 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); 599 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 600 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 601 602 setOperationAction(ISD::TRAP, MVT::Other, Legal); 603 604 // Use the default implementation. 605 setOperationAction(ISD::VASTART, MVT::Other, Custom); 606 setOperationAction(ISD::VAARG, MVT::Other, Expand); 607 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 608 setOperationAction(ISD::VAEND, MVT::Other, Expand); 609 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 610 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 611 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 612 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 613 setExceptionPointerRegister(ARM::R0); 614 setExceptionSelectorRegister(ARM::R1); 615 616 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 617 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use 618 // the default expansion. 619 // FIXME: This should be checking for v6k, not just v6. 620 if (Subtarget->hasDataBarrier() || 621 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) { 622 // membarrier needs custom lowering; the rest are legal and handled 623 // normally. 624 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 625 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 626 // Custom lowering for 64-bit ops 627 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 628 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 629 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 630 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 631 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 632 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 633 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 634 // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc. 635 setInsertFencesForAtomic(true); 636 } else { 637 // Set them all for expansion, which will force libcalls. 638 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 639 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 640 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); 641 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); 642 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); 643 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); 644 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); 645 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); 646 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); 647 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); 648 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand); 649 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand); 650 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand); 651 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand); 652 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the 653 // Unordered/Monotonic case. 654 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom); 655 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom); 656 // Since the libcalls include locking, fold in the fences 657 setShouldFoldAtomicFences(true); 658 } 659 660 setOperationAction(ISD::PREFETCH, MVT::Other, Custom); 661 662 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes. 663 if (!Subtarget->hasV6Ops()) { 664 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 665 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 666 } 667 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 668 669 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 670 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR 671 // iff target supports vfp2. 672 setOperationAction(ISD::BITCAST, MVT::i64, Custom); 673 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 674 } 675 676 // We want to custom lower some of our intrinsics. 677 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 678 if (Subtarget->isTargetDarwin()) { 679 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); 680 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); 681 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom); 682 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume"); 683 } 684 685 setOperationAction(ISD::SETCC, MVT::i32, Expand); 686 setOperationAction(ISD::SETCC, MVT::f32, Expand); 687 setOperationAction(ISD::SETCC, MVT::f64, Expand); 688 setOperationAction(ISD::SELECT, MVT::i32, Custom); 689 setOperationAction(ISD::SELECT, MVT::f32, Custom); 690 setOperationAction(ISD::SELECT, MVT::f64, Custom); 691 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 692 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 693 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 694 695 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 696 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 697 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 698 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 699 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 700 701 // We don't support sin/cos/fmod/copysign/pow 702 setOperationAction(ISD::FSIN, MVT::f64, Expand); 703 setOperationAction(ISD::FSIN, MVT::f32, Expand); 704 setOperationAction(ISD::FCOS, MVT::f32, Expand); 705 setOperationAction(ISD::FCOS, MVT::f64, Expand); 706 setOperationAction(ISD::FREM, MVT::f64, Expand); 707 setOperationAction(ISD::FREM, MVT::f32, Expand); 708 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 709 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 710 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 711 } 712 setOperationAction(ISD::FPOW, MVT::f64, Expand); 713 setOperationAction(ISD::FPOW, MVT::f32, Expand); 714 715 setOperationAction(ISD::FMA, MVT::f64, Expand); 716 setOperationAction(ISD::FMA, MVT::f32, Expand); 717 718 // Various VFP goodness 719 if (!UseSoftFloat && !Subtarget->isThumb1Only()) { 720 // int <-> fp are custom expanded into bit_convert + ARMISD ops. 721 if (Subtarget->hasVFP2()) { 722 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 723 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 724 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 725 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 726 } 727 // Special handling for half-precision FP. 728 if (!Subtarget->hasFP16()) { 729 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand); 730 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand); 731 } 732 } 733 734 // We have target-specific dag combine patterns for the following nodes: 735 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine 736 setTargetDAGCombine(ISD::ADD); 737 setTargetDAGCombine(ISD::SUB); 738 setTargetDAGCombine(ISD::MUL); 739 740 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON()) 741 setTargetDAGCombine(ISD::OR); 742 if (Subtarget->hasNEON()) 743 setTargetDAGCombine(ISD::AND); 744 745 setStackPointerRegisterToSaveRestore(ARM::SP); 746 747 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2()) 748 setSchedulingPreference(Sched::RegPressure); 749 else 750 setSchedulingPreference(Sched::Hybrid); 751 752 //// temporary - rewrite interface to use type 753 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1; 754 755 // On ARM arguments smaller than 4 bytes are extended, so all arguments 756 // are at least 4 bytes aligned. 757 setMinStackArgumentAlignment(4); 758 759 benefitFromCodePlacementOpt = true; 760 761 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2); 762 } 763 764 // FIXME: It might make sense to define the representative register class as the 765 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is 766 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently, 767 // SPR's representative would be DPR_VFP2. This should work well if register 768 // pressure tracking were modified such that a register use would increment the 769 // pressure of the register class's representative and all of it's super 770 // classes' representatives transitively. We have not implemented this because 771 // of the difficulty prior to coalescing of modeling operand register classes 772 // due to the common occurrence of cross class copies and subregister insertions 773 // and extractions. 774 std::pair<const TargetRegisterClass*, uint8_t> 775 ARMTargetLowering::findRepresentativeClass(EVT VT) const{ 776 const TargetRegisterClass *RRC = 0; 777 uint8_t Cost = 1; 778 switch (VT.getSimpleVT().SimpleTy) { 779 default: 780 return TargetLowering::findRepresentativeClass(VT); 781 // Use DPR as representative register class for all floating point 782 // and vector types. Since there are 32 SPR registers and 32 DPR registers so 783 // the cost is 1 for both f32 and f64. 784 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16: 785 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32: 786 RRC = ARM::DPRRegisterClass; 787 // When NEON is used for SP, only half of the register file is available 788 // because operations that define both SP and DP results will be constrained 789 // to the VFP2 class (D0-D15). We currently model this constraint prior to 790 // coalescing by double-counting the SP regs. See the FIXME above. 791 if (Subtarget->useNEONForSinglePrecisionFP()) 792 Cost = 2; 793 break; 794 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 795 case MVT::v4f32: case MVT::v2f64: 796 RRC = ARM::DPRRegisterClass; 797 Cost = 2; 798 break; 799 case MVT::v4i64: 800 RRC = ARM::DPRRegisterClass; 801 Cost = 4; 802 break; 803 case MVT::v8i64: 804 RRC = ARM::DPRRegisterClass; 805 Cost = 8; 806 break; 807 } 808 return std::make_pair(RRC, Cost); 809 } 810 811 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 812 switch (Opcode) { 813 default: return 0; 814 case ARMISD::Wrapper: return "ARMISD::Wrapper"; 815 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN"; 816 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC"; 817 case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; 818 case ARMISD::CALL: return "ARMISD::CALL"; 819 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED"; 820 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; 821 case ARMISD::tCALL: return "ARMISD::tCALL"; 822 case ARMISD::BRCOND: return "ARMISD::BRCOND"; 823 case ARMISD::BR_JT: return "ARMISD::BR_JT"; 824 case ARMISD::BR2_JT: return "ARMISD::BR2_JT"; 825 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 826 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; 827 case ARMISD::CMP: return "ARMISD::CMP"; 828 case ARMISD::CMPZ: return "ARMISD::CMPZ"; 829 case ARMISD::CMPFP: return "ARMISD::CMPFP"; 830 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; 831 case ARMISD::BCC_i64: return "ARMISD::BCC_i64"; 832 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 833 case ARMISD::CMOV: return "ARMISD::CMOV"; 834 835 case ARMISD::RBIT: return "ARMISD::RBIT"; 836 837 case ARMISD::FTOSI: return "ARMISD::FTOSI"; 838 case ARMISD::FTOUI: return "ARMISD::FTOUI"; 839 case ARMISD::SITOF: return "ARMISD::SITOF"; 840 case ARMISD::UITOF: return "ARMISD::UITOF"; 841 842 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; 843 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; 844 case ARMISD::RRX: return "ARMISD::RRX"; 845 846 case ARMISD::ADDC: return "ARMISD::ADDC"; 847 case ARMISD::ADDE: return "ARMISD::ADDE"; 848 case ARMISD::SUBC: return "ARMISD::SUBC"; 849 case ARMISD::SUBE: return "ARMISD::SUBE"; 850 851 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; 852 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR"; 853 854 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP"; 855 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP"; 856 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP"; 857 858 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN"; 859 860 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; 861 862 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC"; 863 864 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER"; 865 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR"; 866 867 case ARMISD::PRELOAD: return "ARMISD::PRELOAD"; 868 869 case ARMISD::VCEQ: return "ARMISD::VCEQ"; 870 case ARMISD::VCEQZ: return "ARMISD::VCEQZ"; 871 case ARMISD::VCGE: return "ARMISD::VCGE"; 872 case ARMISD::VCGEZ: return "ARMISD::VCGEZ"; 873 case ARMISD::VCLEZ: return "ARMISD::VCLEZ"; 874 case ARMISD::VCGEU: return "ARMISD::VCGEU"; 875 case ARMISD::VCGT: return "ARMISD::VCGT"; 876 case ARMISD::VCGTZ: return "ARMISD::VCGTZ"; 877 case ARMISD::VCLTZ: return "ARMISD::VCLTZ"; 878 case ARMISD::VCGTU: return "ARMISD::VCGTU"; 879 case ARMISD::VTST: return "ARMISD::VTST"; 880 881 case ARMISD::VSHL: return "ARMISD::VSHL"; 882 case ARMISD::VSHRs: return "ARMISD::VSHRs"; 883 case ARMISD::VSHRu: return "ARMISD::VSHRu"; 884 case ARMISD::VSHLLs: return "ARMISD::VSHLLs"; 885 case ARMISD::VSHLLu: return "ARMISD::VSHLLu"; 886 case ARMISD::VSHLLi: return "ARMISD::VSHLLi"; 887 case ARMISD::VSHRN: return "ARMISD::VSHRN"; 888 case ARMISD::VRSHRs: return "ARMISD::VRSHRs"; 889 case ARMISD::VRSHRu: return "ARMISD::VRSHRu"; 890 case ARMISD::VRSHRN: return "ARMISD::VRSHRN"; 891 case ARMISD::VQSHLs: return "ARMISD::VQSHLs"; 892 case ARMISD::VQSHLu: return "ARMISD::VQSHLu"; 893 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu"; 894 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs"; 895 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu"; 896 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu"; 897 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs"; 898 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu"; 899 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu"; 900 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu"; 901 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs"; 902 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM"; 903 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM"; 904 case ARMISD::VDUP: return "ARMISD::VDUP"; 905 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; 906 case ARMISD::VEXT: return "ARMISD::VEXT"; 907 case ARMISD::VREV64: return "ARMISD::VREV64"; 908 case ARMISD::VREV32: return "ARMISD::VREV32"; 909 case ARMISD::VREV16: return "ARMISD::VREV16"; 910 case ARMISD::VZIP: return "ARMISD::VZIP"; 911 case ARMISD::VUZP: return "ARMISD::VUZP"; 912 case ARMISD::VTRN: return "ARMISD::VTRN"; 913 case ARMISD::VTBL1: return "ARMISD::VTBL1"; 914 case ARMISD::VTBL2: return "ARMISD::VTBL2"; 915 case ARMISD::VMULLs: return "ARMISD::VMULLs"; 916 case ARMISD::VMULLu: return "ARMISD::VMULLu"; 917 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR"; 918 case ARMISD::FMAX: return "ARMISD::FMAX"; 919 case ARMISD::FMIN: return "ARMISD::FMIN"; 920 case ARMISD::BFI: return "ARMISD::BFI"; 921 case ARMISD::VORRIMM: return "ARMISD::VORRIMM"; 922 case ARMISD::VBICIMM: return "ARMISD::VBICIMM"; 923 case ARMISD::VBSL: return "ARMISD::VBSL"; 924 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP"; 925 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP"; 926 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP"; 927 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD"; 928 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD"; 929 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD"; 930 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD"; 931 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD"; 932 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD"; 933 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD"; 934 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD"; 935 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD"; 936 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD"; 937 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD"; 938 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD"; 939 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD"; 940 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD"; 941 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD"; 942 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD"; 943 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD"; 944 } 945 } 946 947 EVT ARMTargetLowering::getSetCCResultType(EVT VT) const { 948 if (!VT.isVector()) return getPointerTy(); 949 return VT.changeVectorElementTypeToInteger(); 950 } 951 952 /// getRegClassFor - Return the register class that should be used for the 953 /// specified value type. 954 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const { 955 // Map v4i64 to QQ registers but do not make the type legal. Similarly map 956 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to 957 // load / store 4 to 8 consecutive D registers. 958 if (Subtarget->hasNEON()) { 959 if (VT == MVT::v4i64) 960 return ARM::QQPRRegisterClass; 961 else if (VT == MVT::v8i64) 962 return ARM::QQQQPRRegisterClass; 963 } 964 return TargetLowering::getRegClassFor(VT); 965 } 966 967 // Create a fast isel object. 968 FastISel * 969 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 970 return ARM::createFastISel(funcInfo); 971 } 972 973 /// getMaximalGlobalOffset - Returns the maximal possible offset which can 974 /// be used for loads / stores from the global. 975 unsigned ARMTargetLowering::getMaximalGlobalOffset() const { 976 return (Subtarget->isThumb1Only() ? 127 : 4095); 977 } 978 979 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const { 980 unsigned NumVals = N->getNumValues(); 981 if (!NumVals) 982 return Sched::RegPressure; 983 984 for (unsigned i = 0; i != NumVals; ++i) { 985 EVT VT = N->getValueType(i); 986 if (VT == MVT::Glue || VT == MVT::Other) 987 continue; 988 if (VT.isFloatingPoint() || VT.isVector()) 989 return Sched::Latency; 990 } 991 992 if (!N->isMachineOpcode()) 993 return Sched::RegPressure; 994 995 // Load are scheduled for latency even if there instruction itinerary 996 // is not available. 997 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 998 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); 999 1000 if (MCID.getNumDefs() == 0) 1001 return Sched::RegPressure; 1002 if (!Itins->isEmpty() && 1003 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2) 1004 return Sched::Latency; 1005 1006 return Sched::RegPressure; 1007 } 1008 1009 //===----------------------------------------------------------------------===// 1010 // Lowering Code 1011 //===----------------------------------------------------------------------===// 1012 1013 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 1014 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 1015 switch (CC) { 1016 default: llvm_unreachable("Unknown condition code!"); 1017 case ISD::SETNE: return ARMCC::NE; 1018 case ISD::SETEQ: return ARMCC::EQ; 1019 case ISD::SETGT: return ARMCC::GT; 1020 case ISD::SETGE: return ARMCC::GE; 1021 case ISD::SETLT: return ARMCC::LT; 1022 case ISD::SETLE: return ARMCC::LE; 1023 case ISD::SETUGT: return ARMCC::HI; 1024 case ISD::SETUGE: return ARMCC::HS; 1025 case ISD::SETULT: return ARMCC::LO; 1026 case ISD::SETULE: return ARMCC::LS; 1027 } 1028 } 1029 1030 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. 1031 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, 1032 ARMCC::CondCodes &CondCode2) { 1033 CondCode2 = ARMCC::AL; 1034 switch (CC) { 1035 default: llvm_unreachable("Unknown FP condition!"); 1036 case ISD::SETEQ: 1037 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 1038 case ISD::SETGT: 1039 case ISD::SETOGT: CondCode = ARMCC::GT; break; 1040 case ISD::SETGE: 1041 case ISD::SETOGE: CondCode = ARMCC::GE; break; 1042 case ISD::SETOLT: CondCode = ARMCC::MI; break; 1043 case ISD::SETOLE: CondCode = ARMCC::LS; break; 1044 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; 1045 case ISD::SETO: CondCode = ARMCC::VC; break; 1046 case ISD::SETUO: CondCode = ARMCC::VS; break; 1047 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; 1048 case ISD::SETUGT: CondCode = ARMCC::HI; break; 1049 case ISD::SETUGE: CondCode = ARMCC::PL; break; 1050 case ISD::SETLT: 1051 case ISD::SETULT: CondCode = ARMCC::LT; break; 1052 case ISD::SETLE: 1053 case ISD::SETULE: CondCode = ARMCC::LE; break; 1054 case ISD::SETNE: 1055 case ISD::SETUNE: CondCode = ARMCC::NE; break; 1056 } 1057 } 1058 1059 //===----------------------------------------------------------------------===// 1060 // Calling Convention Implementation 1061 //===----------------------------------------------------------------------===// 1062 1063 #include "ARMGenCallingConv.inc" 1064 1065 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the 1066 /// given CallingConvention value. 1067 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC, 1068 bool Return, 1069 bool isVarArg) const { 1070 switch (CC) { 1071 default: 1072 llvm_unreachable("Unsupported calling convention"); 1073 case CallingConv::Fast: 1074 if (Subtarget->hasVFP2() && !isVarArg) { 1075 if (!Subtarget->isAAPCS_ABI()) 1076 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS); 1077 // For AAPCS ABI targets, just use VFP variant of the calling convention. 1078 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1079 } 1080 // Fallthrough 1081 case CallingConv::C: { 1082 // Use target triple & subtarget features to do actual dispatch. 1083 if (!Subtarget->isAAPCS_ABI()) 1084 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS); 1085 else if (Subtarget->hasVFP2() && 1086 FloatABIType == FloatABI::Hard && !isVarArg) 1087 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1088 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS); 1089 } 1090 case CallingConv::ARM_AAPCS_VFP: 1091 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1092 case CallingConv::ARM_AAPCS: 1093 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS); 1094 case CallingConv::ARM_APCS: 1095 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS); 1096 } 1097 } 1098 1099 /// LowerCallResult - Lower the result values of a call into the 1100 /// appropriate copies out of appropriate physical registers. 1101 SDValue 1102 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1103 CallingConv::ID CallConv, bool isVarArg, 1104 const SmallVectorImpl<ISD::InputArg> &Ins, 1105 DebugLoc dl, SelectionDAG &DAG, 1106 SmallVectorImpl<SDValue> &InVals) const { 1107 1108 // Assign locations to each value returned by this call. 1109 SmallVector<CCValAssign, 16> RVLocs; 1110 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1111 getTargetMachine(), RVLocs, *DAG.getContext(), Call); 1112 CCInfo.AnalyzeCallResult(Ins, 1113 CCAssignFnForNode(CallConv, /* Return*/ true, 1114 isVarArg)); 1115 1116 // Copy all of the result registers out of their specified physreg. 1117 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1118 CCValAssign VA = RVLocs[i]; 1119 1120 SDValue Val; 1121 if (VA.needsCustom()) { 1122 // Handle f64 or half of a v2f64. 1123 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1124 InFlag); 1125 Chain = Lo.getValue(1); 1126 InFlag = Lo.getValue(2); 1127 VA = RVLocs[++i]; // skip ahead to next loc 1128 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1129 InFlag); 1130 Chain = Hi.getValue(1); 1131 InFlag = Hi.getValue(2); 1132 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 1133 1134 if (VA.getLocVT() == MVT::v2f64) { 1135 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 1136 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 1137 DAG.getConstant(0, MVT::i32)); 1138 1139 VA = RVLocs[++i]; // skip ahead to next loc 1140 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 1141 Chain = Lo.getValue(1); 1142 InFlag = Lo.getValue(2); 1143 VA = RVLocs[++i]; // skip ahead to next loc 1144 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 1145 Chain = Hi.getValue(1); 1146 InFlag = Hi.getValue(2); 1147 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 1148 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 1149 DAG.getConstant(1, MVT::i32)); 1150 } 1151 } else { 1152 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), 1153 InFlag); 1154 Chain = Val.getValue(1); 1155 InFlag = Val.getValue(2); 1156 } 1157 1158 switch (VA.getLocInfo()) { 1159 default: llvm_unreachable("Unknown loc info!"); 1160 case CCValAssign::Full: break; 1161 case CCValAssign::BCvt: 1162 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); 1163 break; 1164 } 1165 1166 InVals.push_back(Val); 1167 } 1168 1169 return Chain; 1170 } 1171 1172 /// LowerMemOpCallTo - Store the argument to the stack. 1173 SDValue 1174 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, 1175 SDValue StackPtr, SDValue Arg, 1176 DebugLoc dl, SelectionDAG &DAG, 1177 const CCValAssign &VA, 1178 ISD::ArgFlagsTy Flags) const { 1179 unsigned LocMemOffset = VA.getLocMemOffset(); 1180 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1181 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1182 return DAG.getStore(Chain, dl, Arg, PtrOff, 1183 MachinePointerInfo::getStack(LocMemOffset), 1184 false, false, 0); 1185 } 1186 1187 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 1188 SDValue Chain, SDValue &Arg, 1189 RegsToPassVector &RegsToPass, 1190 CCValAssign &VA, CCValAssign &NextVA, 1191 SDValue &StackPtr, 1192 SmallVector<SDValue, 8> &MemOpChains, 1193 ISD::ArgFlagsTy Flags) const { 1194 1195 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, 1196 DAG.getVTList(MVT::i32, MVT::i32), Arg); 1197 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd)); 1198 1199 if (NextVA.isRegLoc()) 1200 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1))); 1201 else { 1202 assert(NextVA.isMemLoc()); 1203 if (StackPtr.getNode() == 0) 1204 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 1205 1206 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1), 1207 dl, DAG, NextVA, 1208 Flags)); 1209 } 1210 } 1211 1212 /// LowerCall - Lowering a call into a callseq_start <- 1213 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter 1214 /// nodes. 1215 SDValue 1216 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1217 CallingConv::ID CallConv, bool isVarArg, 1218 bool &isTailCall, 1219 const SmallVectorImpl<ISD::OutputArg> &Outs, 1220 const SmallVectorImpl<SDValue> &OutVals, 1221 const SmallVectorImpl<ISD::InputArg> &Ins, 1222 DebugLoc dl, SelectionDAG &DAG, 1223 SmallVectorImpl<SDValue> &InVals) const { 1224 MachineFunction &MF = DAG.getMachineFunction(); 1225 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); 1226 bool IsSibCall = false; 1227 // Disable tail calls if they're not supported. 1228 if (!EnableARMTailCalls && !Subtarget->supportsTailCall()) 1229 isTailCall = false; 1230 if (isTailCall) { 1231 // Check if it's really possible to do a tail call. 1232 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 1233 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 1234 Outs, OutVals, Ins, DAG); 1235 // We don't support GuaranteedTailCallOpt for ARM, only automatically 1236 // detected sibcalls. 1237 if (isTailCall) { 1238 ++NumTailCalls; 1239 IsSibCall = true; 1240 } 1241 } 1242 1243 // Analyze operands of the call, assigning locations to each operand. 1244 SmallVector<CCValAssign, 16> ArgLocs; 1245 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1246 getTargetMachine(), ArgLocs, *DAG.getContext(), Call); 1247 CCInfo.AnalyzeCallOperands(Outs, 1248 CCAssignFnForNode(CallConv, /* Return*/ false, 1249 isVarArg)); 1250 1251 // Get a count of how many bytes are to be pushed on the stack. 1252 unsigned NumBytes = CCInfo.getNextStackOffset(); 1253 1254 // For tail calls, memory operands are available in our caller's stack. 1255 if (IsSibCall) 1256 NumBytes = 0; 1257 1258 // Adjust the stack pointer for the new arguments... 1259 // These operations are automatically eliminated by the prolog/epilog pass 1260 if (!IsSibCall) 1261 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1262 1263 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 1264 1265 RegsToPassVector RegsToPass; 1266 SmallVector<SDValue, 8> MemOpChains; 1267 1268 // Walk the register/memloc assignments, inserting copies/loads. In the case 1269 // of tail call optimization, arguments are handled later. 1270 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1271 i != e; 1272 ++i, ++realArgIdx) { 1273 CCValAssign &VA = ArgLocs[i]; 1274 SDValue Arg = OutVals[realArgIdx]; 1275 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1276 bool isByVal = Flags.isByVal(); 1277 1278 // Promote the value if needed. 1279 switch (VA.getLocInfo()) { 1280 default: llvm_unreachable("Unknown loc info!"); 1281 case CCValAssign::Full: break; 1282 case CCValAssign::SExt: 1283 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 1284 break; 1285 case CCValAssign::ZExt: 1286 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 1287 break; 1288 case CCValAssign::AExt: 1289 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 1290 break; 1291 case CCValAssign::BCvt: 1292 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 1293 break; 1294 } 1295 1296 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces 1297 if (VA.needsCustom()) { 1298 if (VA.getLocVT() == MVT::v2f64) { 1299 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1300 DAG.getConstant(0, MVT::i32)); 1301 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1302 DAG.getConstant(1, MVT::i32)); 1303 1304 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, 1305 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1306 1307 VA = ArgLocs[++i]; // skip ahead to next loc 1308 if (VA.isRegLoc()) { 1309 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, 1310 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1311 } else { 1312 assert(VA.isMemLoc()); 1313 1314 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1, 1315 dl, DAG, VA, Flags)); 1316 } 1317 } else { 1318 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i], 1319 StackPtr, MemOpChains, Flags); 1320 } 1321 } else if (VA.isRegLoc()) { 1322 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1323 } else if (isByVal) { 1324 assert(VA.isMemLoc()); 1325 unsigned offset = 0; 1326 1327 // True if this byval aggregate will be split between registers 1328 // and memory. 1329 if (CCInfo.isFirstByValRegValid()) { 1330 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1331 unsigned int i, j; 1332 for (i = 0, j = CCInfo.getFirstByValReg(); j < ARM::R4; i++, j++) { 1333 SDValue Const = DAG.getConstant(4*i, MVT::i32); 1334 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 1335 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 1336 MachinePointerInfo(), 1337 false, false, 0); 1338 MemOpChains.push_back(Load.getValue(1)); 1339 RegsToPass.push_back(std::make_pair(j, Load)); 1340 } 1341 offset = ARM::R4 - CCInfo.getFirstByValReg(); 1342 CCInfo.clearFirstByValReg(); 1343 } 1344 1345 unsigned LocMemOffset = VA.getLocMemOffset(); 1346 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset); 1347 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, 1348 StkPtrOff); 1349 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset); 1350 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset); 1351 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, 1352 MVT::i32); 1353 // TODO: Disable AlwaysInline when it becomes possible 1354 // to emit a nested call sequence. 1355 MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, 1356 Flags.getByValAlign(), 1357 /*isVolatile=*/false, 1358 /*AlwaysInline=*/true, 1359 MachinePointerInfo(0), 1360 MachinePointerInfo(0))); 1361 1362 } else if (!IsSibCall) { 1363 assert(VA.isMemLoc()); 1364 1365 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 1366 dl, DAG, VA, Flags)); 1367 } 1368 } 1369 1370 if (!MemOpChains.empty()) 1371 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1372 &MemOpChains[0], MemOpChains.size()); 1373 1374 // Build a sequence of copy-to-reg nodes chained together with token chain 1375 // and flag operands which copy the outgoing args into the appropriate regs. 1376 SDValue InFlag; 1377 // Tail call byval lowering might overwrite argument registers so in case of 1378 // tail call optimization the copies to registers are lowered later. 1379 if (!isTailCall) 1380 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1381 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1382 RegsToPass[i].second, InFlag); 1383 InFlag = Chain.getValue(1); 1384 } 1385 1386 // For tail calls lower the arguments to the 'real' stack slot. 1387 if (isTailCall) { 1388 // Force all the incoming stack arguments to be loaded from the stack 1389 // before any new outgoing arguments are stored to the stack, because the 1390 // outgoing stack slots may alias the incoming argument stack slots, and 1391 // the alias isn't otherwise explicit. This is slightly more conservative 1392 // than necessary, because it means that each store effectively depends 1393 // on every argument instead of just those arguments it would clobber. 1394 1395 // Do not flag preceding copytoreg stuff together with the following stuff. 1396 InFlag = SDValue(); 1397 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1398 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1399 RegsToPass[i].second, InFlag); 1400 InFlag = Chain.getValue(1); 1401 } 1402 InFlag =SDValue(); 1403 } 1404 1405 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1406 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1407 // node so that legalize doesn't hack it. 1408 bool isDirect = false; 1409 bool isARMFunc = false; 1410 bool isLocalARMFunc = false; 1411 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1412 1413 if (EnableARMLongCalls) { 1414 assert (getTargetMachine().getRelocationModel() == Reloc::Static 1415 && "long-calls with non-static relocation model!"); 1416 // Handle a global address or an external symbol. If it's not one of 1417 // those, the target's already in a register, so we don't need to do 1418 // anything extra. 1419 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1420 const GlobalValue *GV = G->getGlobal(); 1421 // Create a constant pool entry for the callee address 1422 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1423 ARMConstantPoolValue *CPV = 1424 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0); 1425 1426 // Get the address of the callee into a register 1427 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1428 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1429 Callee = DAG.getLoad(getPointerTy(), dl, 1430 DAG.getEntryNode(), CPAddr, 1431 MachinePointerInfo::getConstantPool(), 1432 false, false, 0); 1433 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) { 1434 const char *Sym = S->getSymbol(); 1435 1436 // Create a constant pool entry for the callee address 1437 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1438 ARMConstantPoolValue *CPV = 1439 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym, 1440 ARMPCLabelIndex, 0); 1441 // Get the address of the callee into a register 1442 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1443 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1444 Callee = DAG.getLoad(getPointerTy(), dl, 1445 DAG.getEntryNode(), CPAddr, 1446 MachinePointerInfo::getConstantPool(), 1447 false, false, 0); 1448 } 1449 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1450 const GlobalValue *GV = G->getGlobal(); 1451 isDirect = true; 1452 bool isExt = GV->isDeclaration() || GV->isWeakForLinker(); 1453 bool isStub = (isExt && Subtarget->isTargetDarwin()) && 1454 getTargetMachine().getRelocationModel() != Reloc::Static; 1455 isARMFunc = !Subtarget->isThumb() || isStub; 1456 // ARM call to a local ARM function is predicable. 1457 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking); 1458 // tBX takes a register source operand. 1459 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1460 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1461 ARMConstantPoolValue *CPV = 1462 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 4); 1463 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1464 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1465 Callee = DAG.getLoad(getPointerTy(), dl, 1466 DAG.getEntryNode(), CPAddr, 1467 MachinePointerInfo::getConstantPool(), 1468 false, false, 0); 1469 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1470 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1471 getPointerTy(), Callee, PICLabel); 1472 } else { 1473 // On ELF targets for PIC code, direct calls should go through the PLT 1474 unsigned OpFlags = 0; 1475 if (Subtarget->isTargetELF() && 1476 getTargetMachine().getRelocationModel() == Reloc::PIC_) 1477 OpFlags = ARMII::MO_PLT; 1478 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 1479 } 1480 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1481 isDirect = true; 1482 bool isStub = Subtarget->isTargetDarwin() && 1483 getTargetMachine().getRelocationModel() != Reloc::Static; 1484 isARMFunc = !Subtarget->isThumb() || isStub; 1485 // tBX takes a register source operand. 1486 const char *Sym = S->getSymbol(); 1487 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1488 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1489 ARMConstantPoolValue *CPV = 1490 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym, 1491 ARMPCLabelIndex, 4); 1492 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1493 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1494 Callee = DAG.getLoad(getPointerTy(), dl, 1495 DAG.getEntryNode(), CPAddr, 1496 MachinePointerInfo::getConstantPool(), 1497 false, false, 0); 1498 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1499 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1500 getPointerTy(), Callee, PICLabel); 1501 } else { 1502 unsigned OpFlags = 0; 1503 // On ELF targets for PIC code, direct calls should go through the PLT 1504 if (Subtarget->isTargetELF() && 1505 getTargetMachine().getRelocationModel() == Reloc::PIC_) 1506 OpFlags = ARMII::MO_PLT; 1507 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags); 1508 } 1509 } 1510 1511 // FIXME: handle tail calls differently. 1512 unsigned CallOpc; 1513 if (Subtarget->isThumb()) { 1514 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps()) 1515 CallOpc = ARMISD::CALL_NOLINK; 1516 else 1517 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; 1518 } else { 1519 CallOpc = (isDirect || Subtarget->hasV5TOps()) 1520 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL) 1521 : ARMISD::CALL_NOLINK; 1522 } 1523 1524 std::vector<SDValue> Ops; 1525 Ops.push_back(Chain); 1526 Ops.push_back(Callee); 1527 1528 // Add argument registers to the end of the list so that they are known live 1529 // into the call. 1530 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1531 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1532 RegsToPass[i].second.getValueType())); 1533 1534 if (InFlag.getNode()) 1535 Ops.push_back(InFlag); 1536 1537 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1538 if (isTailCall) 1539 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size()); 1540 1541 // Returns a chain and a flag for retval copy to use. 1542 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 1543 InFlag = Chain.getValue(1); 1544 1545 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 1546 DAG.getIntPtrConstant(0, true), InFlag); 1547 if (!Ins.empty()) 1548 InFlag = Chain.getValue(1); 1549 1550 // Handle result values, copying them out of physregs into vregs that we 1551 // return. 1552 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, 1553 dl, DAG, InVals); 1554 } 1555 1556 /// HandleByVal - Every parameter *after* a byval parameter is passed 1557 /// on the stack. Remember the next parameter register to allocate, 1558 /// and then confiscate the rest of the parameter registers to insure 1559 /// this. 1560 void 1561 llvm::ARMTargetLowering::HandleByVal(CCState *State, unsigned &size) const { 1562 unsigned reg = State->AllocateReg(GPRArgRegs, 4); 1563 assert((State->getCallOrPrologue() == Prologue || 1564 State->getCallOrPrologue() == Call) && 1565 "unhandled ParmContext"); 1566 if ((!State->isFirstByValRegValid()) && 1567 (ARM::R0 <= reg) && (reg <= ARM::R3)) { 1568 State->setFirstByValReg(reg); 1569 // At a call site, a byval parameter that is split between 1570 // registers and memory needs its size truncated here. In a 1571 // function prologue, such byval parameters are reassembled in 1572 // memory, and are not truncated. 1573 if (State->getCallOrPrologue() == Call) { 1574 unsigned excess = 4 * (ARM::R4 - reg); 1575 assert(size >= excess && "expected larger existing stack allocation"); 1576 size -= excess; 1577 } 1578 } 1579 // Confiscate any remaining parameter registers to preclude their 1580 // assignment to subsequent parameters. 1581 while (State->AllocateReg(GPRArgRegs, 4)) 1582 ; 1583 } 1584 1585 /// MatchingStackOffset - Return true if the given stack call argument is 1586 /// already available in the same position (relatively) of the caller's 1587 /// incoming argument stack. 1588 static 1589 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 1590 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 1591 const ARMInstrInfo *TII) { 1592 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 1593 int FI = INT_MAX; 1594 if (Arg.getOpcode() == ISD::CopyFromReg) { 1595 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 1596 if (!TargetRegisterInfo::isVirtualRegister(VR)) 1597 return false; 1598 MachineInstr *Def = MRI->getVRegDef(VR); 1599 if (!Def) 1600 return false; 1601 if (!Flags.isByVal()) { 1602 if (!TII->isLoadFromStackSlot(Def, FI)) 1603 return false; 1604 } else { 1605 return false; 1606 } 1607 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 1608 if (Flags.isByVal()) 1609 // ByVal argument is passed in as a pointer but it's now being 1610 // dereferenced. e.g. 1611 // define @foo(%struct.X* %A) { 1612 // tail call @bar(%struct.X* byval %A) 1613 // } 1614 return false; 1615 SDValue Ptr = Ld->getBasePtr(); 1616 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 1617 if (!FINode) 1618 return false; 1619 FI = FINode->getIndex(); 1620 } else 1621 return false; 1622 1623 assert(FI != INT_MAX); 1624 if (!MFI->isFixedObjectIndex(FI)) 1625 return false; 1626 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 1627 } 1628 1629 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 1630 /// for tail call optimization. Targets which want to do tail call 1631 /// optimization should implement this function. 1632 bool 1633 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 1634 CallingConv::ID CalleeCC, 1635 bool isVarArg, 1636 bool isCalleeStructRet, 1637 bool isCallerStructRet, 1638 const SmallVectorImpl<ISD::OutputArg> &Outs, 1639 const SmallVectorImpl<SDValue> &OutVals, 1640 const SmallVectorImpl<ISD::InputArg> &Ins, 1641 SelectionDAG& DAG) const { 1642 const Function *CallerF = DAG.getMachineFunction().getFunction(); 1643 CallingConv::ID CallerCC = CallerF->getCallingConv(); 1644 bool CCMatch = CallerCC == CalleeCC; 1645 1646 // Look for obvious safe cases to perform tail call optimization that do not 1647 // require ABI changes. This is what gcc calls sibcall. 1648 1649 // Do not sibcall optimize vararg calls unless the call site is not passing 1650 // any arguments. 1651 if (isVarArg && !Outs.empty()) 1652 return false; 1653 1654 // Also avoid sibcall optimization if either caller or callee uses struct 1655 // return semantics. 1656 if (isCalleeStructRet || isCallerStructRet) 1657 return false; 1658 1659 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo:: 1660 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as 1661 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation 1662 // support in the assembler and linker to be used. This would need to be 1663 // fixed to fully support tail calls in Thumb1. 1664 // 1665 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take 1666 // LR. This means if we need to reload LR, it takes an extra instructions, 1667 // which outweighs the value of the tail call; but here we don't know yet 1668 // whether LR is going to be used. Probably the right approach is to 1669 // generate the tail call here and turn it back into CALL/RET in 1670 // emitEpilogue if LR is used. 1671 1672 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls, 1673 // but we need to make sure there are enough registers; the only valid 1674 // registers are the 4 used for parameters. We don't currently do this 1675 // case. 1676 if (Subtarget->isThumb1Only()) 1677 return false; 1678 1679 // If the calling conventions do not match, then we'd better make sure the 1680 // results are returned in the same way as what the caller expects. 1681 if (!CCMatch) { 1682 SmallVector<CCValAssign, 16> RVLocs1; 1683 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 1684 getTargetMachine(), RVLocs1, *DAG.getContext(), Call); 1685 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg)); 1686 1687 SmallVector<CCValAssign, 16> RVLocs2; 1688 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 1689 getTargetMachine(), RVLocs2, *DAG.getContext(), Call); 1690 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg)); 1691 1692 if (RVLocs1.size() != RVLocs2.size()) 1693 return false; 1694 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 1695 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 1696 return false; 1697 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 1698 return false; 1699 if (RVLocs1[i].isRegLoc()) { 1700 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 1701 return false; 1702 } else { 1703 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 1704 return false; 1705 } 1706 } 1707 } 1708 1709 // If the callee takes no arguments then go on to check the results of the 1710 // call. 1711 if (!Outs.empty()) { 1712 // Check if stack adjustment is needed. For now, do not do this if any 1713 // argument is passed on the stack. 1714 SmallVector<CCValAssign, 16> ArgLocs; 1715 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 1716 getTargetMachine(), ArgLocs, *DAG.getContext(), Call); 1717 CCInfo.AnalyzeCallOperands(Outs, 1718 CCAssignFnForNode(CalleeCC, false, isVarArg)); 1719 if (CCInfo.getNextStackOffset()) { 1720 MachineFunction &MF = DAG.getMachineFunction(); 1721 1722 // Check if the arguments are already laid out in the right way as 1723 // the caller's fixed stack objects. 1724 MachineFrameInfo *MFI = MF.getFrameInfo(); 1725 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 1726 const ARMInstrInfo *TII = 1727 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo(); 1728 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1729 i != e; 1730 ++i, ++realArgIdx) { 1731 CCValAssign &VA = ArgLocs[i]; 1732 EVT RegVT = VA.getLocVT(); 1733 SDValue Arg = OutVals[realArgIdx]; 1734 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1735 if (VA.getLocInfo() == CCValAssign::Indirect) 1736 return false; 1737 if (VA.needsCustom()) { 1738 // f64 and vector types are split into multiple registers or 1739 // register/stack-slot combinations. The types will not match 1740 // the registers; give up on memory f64 refs until we figure 1741 // out what to do about this. 1742 if (!VA.isRegLoc()) 1743 return false; 1744 if (!ArgLocs[++i].isRegLoc()) 1745 return false; 1746 if (RegVT == MVT::v2f64) { 1747 if (!ArgLocs[++i].isRegLoc()) 1748 return false; 1749 if (!ArgLocs[++i].isRegLoc()) 1750 return false; 1751 } 1752 } else if (!VA.isRegLoc()) { 1753 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 1754 MFI, MRI, TII)) 1755 return false; 1756 } 1757 } 1758 } 1759 } 1760 1761 return true; 1762 } 1763 1764 SDValue 1765 ARMTargetLowering::LowerReturn(SDValue Chain, 1766 CallingConv::ID CallConv, bool isVarArg, 1767 const SmallVectorImpl<ISD::OutputArg> &Outs, 1768 const SmallVectorImpl<SDValue> &OutVals, 1769 DebugLoc dl, SelectionDAG &DAG) const { 1770 1771 // CCValAssign - represent the assignment of the return value to a location. 1772 SmallVector<CCValAssign, 16> RVLocs; 1773 1774 // CCState - Info about the registers and stack slots. 1775 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1776 getTargetMachine(), RVLocs, *DAG.getContext(), Call); 1777 1778 // Analyze outgoing return values. 1779 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true, 1780 isVarArg)); 1781 1782 // If this is the first return lowered for this function, add 1783 // the regs to the liveout set for the function. 1784 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 1785 for (unsigned i = 0; i != RVLocs.size(); ++i) 1786 if (RVLocs[i].isRegLoc()) 1787 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 1788 } 1789 1790 SDValue Flag; 1791 1792 // Copy the result values into the output registers. 1793 for (unsigned i = 0, realRVLocIdx = 0; 1794 i != RVLocs.size(); 1795 ++i, ++realRVLocIdx) { 1796 CCValAssign &VA = RVLocs[i]; 1797 assert(VA.isRegLoc() && "Can only return in registers!"); 1798 1799 SDValue Arg = OutVals[realRVLocIdx]; 1800 1801 switch (VA.getLocInfo()) { 1802 default: llvm_unreachable("Unknown loc info!"); 1803 case CCValAssign::Full: break; 1804 case CCValAssign::BCvt: 1805 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 1806 break; 1807 } 1808 1809 if (VA.needsCustom()) { 1810 if (VA.getLocVT() == MVT::v2f64) { 1811 // Extract the first half and return it in two registers. 1812 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1813 DAG.getConstant(0, MVT::i32)); 1814 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, 1815 DAG.getVTList(MVT::i32, MVT::i32), Half); 1816 1817 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag); 1818 Flag = Chain.getValue(1); 1819 VA = RVLocs[++i]; // skip ahead to next loc 1820 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 1821 HalfGPRs.getValue(1), Flag); 1822 Flag = Chain.getValue(1); 1823 VA = RVLocs[++i]; // skip ahead to next loc 1824 1825 // Extract the 2nd half and fall through to handle it as an f64 value. 1826 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1827 DAG.getConstant(1, MVT::i32)); 1828 } 1829 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is 1830 // available. 1831 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, 1832 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); 1833 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag); 1834 Flag = Chain.getValue(1); 1835 VA = RVLocs[++i]; // skip ahead to next loc 1836 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1), 1837 Flag); 1838 } else 1839 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); 1840 1841 // Guarantee that all emitted copies are 1842 // stuck together, avoiding something bad. 1843 Flag = Chain.getValue(1); 1844 } 1845 1846 SDValue result; 1847 if (Flag.getNode()) 1848 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 1849 else // Return Void 1850 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain); 1851 1852 return result; 1853 } 1854 1855 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const { 1856 if (N->getNumValues() != 1) 1857 return false; 1858 if (!N->hasNUsesOfValue(1, 0)) 1859 return false; 1860 1861 unsigned NumCopies = 0; 1862 SDNode* Copies[2]; 1863 SDNode *Use = *N->use_begin(); 1864 if (Use->getOpcode() == ISD::CopyToReg) { 1865 Copies[NumCopies++] = Use; 1866 } else if (Use->getOpcode() == ARMISD::VMOVRRD) { 1867 // f64 returned in a pair of GPRs. 1868 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end(); 1869 UI != UE; ++UI) { 1870 if (UI->getOpcode() != ISD::CopyToReg) 1871 return false; 1872 Copies[UI.getUse().getResNo()] = *UI; 1873 ++NumCopies; 1874 } 1875 } else if (Use->getOpcode() == ISD::BITCAST) { 1876 // f32 returned in a single GPR. 1877 if (!Use->hasNUsesOfValue(1, 0)) 1878 return false; 1879 Use = *Use->use_begin(); 1880 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0)) 1881 return false; 1882 Copies[NumCopies++] = Use; 1883 } else { 1884 return false; 1885 } 1886 1887 if (NumCopies != 1 && NumCopies != 2) 1888 return false; 1889 1890 bool HasRet = false; 1891 for (unsigned i = 0; i < NumCopies; ++i) { 1892 SDNode *Copy = Copies[i]; 1893 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1894 UI != UE; ++UI) { 1895 if (UI->getOpcode() == ISD::CopyToReg) { 1896 SDNode *Use = *UI; 1897 if (Use == Copies[0] || Use == Copies[1]) 1898 continue; 1899 return false; 1900 } 1901 if (UI->getOpcode() != ARMISD::RET_FLAG) 1902 return false; 1903 HasRet = true; 1904 } 1905 } 1906 1907 return HasRet; 1908 } 1909 1910 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1911 if (!EnableARMTailCalls) 1912 return false; 1913 1914 if (!CI->isTailCall()) 1915 return false; 1916 1917 return !Subtarget->isThumb1Only(); 1918 } 1919 1920 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 1921 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is 1922 // one of the above mentioned nodes. It has to be wrapped because otherwise 1923 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 1924 // be used to form addressing mode. These wrapped nodes will be selected 1925 // into MOVi. 1926 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 1927 EVT PtrVT = Op.getValueType(); 1928 // FIXME there is no actual debug info here 1929 DebugLoc dl = Op.getDebugLoc(); 1930 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1931 SDValue Res; 1932 if (CP->isMachineConstantPoolEntry()) 1933 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 1934 CP->getAlignment()); 1935 else 1936 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 1937 CP->getAlignment()); 1938 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res); 1939 } 1940 1941 unsigned ARMTargetLowering::getJumpTableEncoding() const { 1942 return MachineJumpTableInfo::EK_Inline; 1943 } 1944 1945 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op, 1946 SelectionDAG &DAG) const { 1947 MachineFunction &MF = DAG.getMachineFunction(); 1948 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1949 unsigned ARMPCLabelIndex = 0; 1950 DebugLoc DL = Op.getDebugLoc(); 1951 EVT PtrVT = getPointerTy(); 1952 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1953 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1954 SDValue CPAddr; 1955 if (RelocM == Reloc::Static) { 1956 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4); 1957 } else { 1958 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 1959 ARMPCLabelIndex = AFI->createPICLabelUId(); 1960 ARMConstantPoolValue *CPV = 1961 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex, 1962 ARMCP::CPBlockAddress, PCAdj); 1963 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1964 } 1965 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr); 1966 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr, 1967 MachinePointerInfo::getConstantPool(), 1968 false, false, 0); 1969 if (RelocM == Reloc::Static) 1970 return Result; 1971 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1972 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel); 1973 } 1974 1975 // Lower ISD::GlobalTLSAddress using the "general dynamic" model 1976 SDValue 1977 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 1978 SelectionDAG &DAG) const { 1979 DebugLoc dl = GA->getDebugLoc(); 1980 EVT PtrVT = getPointerTy(); 1981 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 1982 MachineFunction &MF = DAG.getMachineFunction(); 1983 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1984 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1985 ARMConstantPoolValue *CPV = 1986 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex, 1987 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true); 1988 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1989 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument); 1990 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, 1991 MachinePointerInfo::getConstantPool(), 1992 false, false, 0); 1993 SDValue Chain = Argument.getValue(1); 1994 1995 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1996 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel); 1997 1998 // call __tls_get_addr. 1999 ArgListTy Args; 2000 ArgListEntry Entry; 2001 Entry.Node = Argument; 2002 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext()); 2003 Args.push_back(Entry); 2004 // FIXME: is there useful debug info available here? 2005 std::pair<SDValue, SDValue> CallResult = 2006 LowerCallTo(Chain, (Type *) Type::getInt32Ty(*DAG.getContext()), 2007 false, false, false, false, 2008 0, CallingConv::C, false, /*isReturnValueUsed=*/true, 2009 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl); 2010 return CallResult.first; 2011 } 2012 2013 // Lower ISD::GlobalTLSAddress using the "initial exec" or 2014 // "local exec" model. 2015 SDValue 2016 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, 2017 SelectionDAG &DAG) const { 2018 const GlobalValue *GV = GA->getGlobal(); 2019 DebugLoc dl = GA->getDebugLoc(); 2020 SDValue Offset; 2021 SDValue Chain = DAG.getEntryNode(); 2022 EVT PtrVT = getPointerTy(); 2023 // Get the Thread Pointer 2024 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 2025 2026 if (GV->isDeclaration()) { 2027 MachineFunction &MF = DAG.getMachineFunction(); 2028 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2029 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2030 // Initial exec model. 2031 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 2032 ARMConstantPoolValue *CPV = 2033 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex, 2034 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, 2035 true); 2036 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2037 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 2038 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2039 MachinePointerInfo::getConstantPool(), 2040 false, false, 0); 2041 Chain = Offset.getValue(1); 2042 2043 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2044 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel); 2045 2046 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2047 MachinePointerInfo::getConstantPool(), 2048 false, false, 0); 2049 } else { 2050 // local exec model 2051 ARMConstantPoolValue *CPV = 2052 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF); 2053 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2054 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 2055 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2056 MachinePointerInfo::getConstantPool(), 2057 false, false, 0); 2058 } 2059 2060 // The address of the thread local variable is the add of the thread 2061 // pointer with the offset of the variable. 2062 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 2063 } 2064 2065 SDValue 2066 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 2067 // TODO: implement the "local dynamic" model 2068 assert(Subtarget->isTargetELF() && 2069 "TLS not implemented for non-ELF targets"); 2070 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2071 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 2072 // otherwise use the "Local Exec" TLS Model 2073 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 2074 return LowerToTLSGeneralDynamicModel(GA, DAG); 2075 else 2076 return LowerToTLSExecModels(GA, DAG); 2077 } 2078 2079 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, 2080 SelectionDAG &DAG) const { 2081 EVT PtrVT = getPointerTy(); 2082 DebugLoc dl = Op.getDebugLoc(); 2083 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 2084 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2085 if (RelocM == Reloc::PIC_) { 2086 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility(); 2087 ARMConstantPoolValue *CPV = 2088 ARMConstantPoolConstant::Create(GV, 2089 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT); 2090 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2091 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2092 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 2093 CPAddr, 2094 MachinePointerInfo::getConstantPool(), 2095 false, false, 0); 2096 SDValue Chain = Result.getValue(1); 2097 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT); 2098 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT); 2099 if (!UseGOTOFF) 2100 Result = DAG.getLoad(PtrVT, dl, Chain, Result, 2101 MachinePointerInfo::getGOT(), false, false, 0); 2102 return Result; 2103 } 2104 2105 // If we have T2 ops, we can materialize the address directly via movt/movw 2106 // pair. This is always cheaper in terms of performance, but uses at least 2 2107 // extra bytes. 2108 if (Subtarget->useMovt() && 2109 !DAG.getMachineFunction().getFunction()->hasFnAttr(Attribute::OptimizeForSize)) { 2110 ++NumMovwMovt; 2111 // FIXME: Once remat is capable of dealing with instructions with register 2112 // operands, expand this into two nodes. 2113 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, 2114 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2115 } else { 2116 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 2117 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2118 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2119 MachinePointerInfo::getConstantPool(), 2120 false, false, 0); 2121 } 2122 } 2123 2124 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, 2125 SelectionDAG &DAG) const { 2126 EVT PtrVT = getPointerTy(); 2127 DebugLoc dl = Op.getDebugLoc(); 2128 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 2129 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2130 MachineFunction &MF = DAG.getMachineFunction(); 2131 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2132 2133 // FIXME: Enable this for static codegen when tool issues are fixed. 2134 if (Subtarget->useMovt() && RelocM != Reloc::Static && 2135 !DAG.getMachineFunction().getFunction()->hasFnAttr(Attribute::OptimizeForSize)) { 2136 ++NumMovwMovt; 2137 // FIXME: Once remat is capable of dealing with instructions with register 2138 // operands, expand this into two nodes. 2139 if (RelocM == Reloc::Static) 2140 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, 2141 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2142 2143 unsigned Wrapper = (RelocM == Reloc::PIC_) 2144 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN; 2145 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, 2146 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2147 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) 2148 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result, 2149 MachinePointerInfo::getGOT(), false, false, 0); 2150 return Result; 2151 } 2152 2153 unsigned ARMPCLabelIndex = 0; 2154 SDValue CPAddr; 2155 if (RelocM == Reloc::Static) { 2156 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 2157 } else { 2158 ARMPCLabelIndex = AFI->createPICLabelUId(); 2159 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8); 2160 ARMConstantPoolValue *CPV = 2161 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 2162 PCAdj); 2163 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2164 } 2165 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2166 2167 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2168 MachinePointerInfo::getConstantPool(), 2169 false, false, 0); 2170 SDValue Chain = Result.getValue(1); 2171 2172 if (RelocM == Reloc::PIC_) { 2173 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2174 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2175 } 2176 2177 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) 2178 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(), 2179 false, false, 0); 2180 2181 return Result; 2182 } 2183 2184 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, 2185 SelectionDAG &DAG) const { 2186 assert(Subtarget->isTargetELF() && 2187 "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); 2188 MachineFunction &MF = DAG.getMachineFunction(); 2189 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2190 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2191 EVT PtrVT = getPointerTy(); 2192 DebugLoc dl = Op.getDebugLoc(); 2193 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 2194 ARMConstantPoolValue *CPV = 2195 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_", 2196 ARMPCLabelIndex, PCAdj); 2197 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2198 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2199 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2200 MachinePointerInfo::getConstantPool(), 2201 false, false, 0); 2202 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2203 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2204 } 2205 2206 SDValue 2207 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG) 2208 const { 2209 DebugLoc dl = Op.getDebugLoc(); 2210 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other, 2211 Op.getOperand(0), Op.getOperand(1)); 2212 } 2213 2214 SDValue 2215 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const { 2216 DebugLoc dl = Op.getDebugLoc(); 2217 SDValue Val = DAG.getConstant(0, MVT::i32); 2218 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, 2219 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0), 2220 Op.getOperand(1), Val); 2221 } 2222 2223 SDValue 2224 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const { 2225 DebugLoc dl = Op.getDebugLoc(); 2226 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0), 2227 Op.getOperand(1), DAG.getConstant(0, MVT::i32)); 2228 } 2229 2230 SDValue 2231 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 2232 const ARMSubtarget *Subtarget) const { 2233 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 2234 DebugLoc dl = Op.getDebugLoc(); 2235 switch (IntNo) { 2236 default: return SDValue(); // Don't custom lower most intrinsics. 2237 case Intrinsic::arm_thread_pointer: { 2238 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2239 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 2240 } 2241 case Intrinsic::eh_sjlj_lsda: { 2242 MachineFunction &MF = DAG.getMachineFunction(); 2243 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2244 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2245 EVT PtrVT = getPointerTy(); 2246 DebugLoc dl = Op.getDebugLoc(); 2247 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2248 SDValue CPAddr; 2249 unsigned PCAdj = (RelocM != Reloc::PIC_) 2250 ? 0 : (Subtarget->isThumb() ? 4 : 8); 2251 ARMConstantPoolValue *CPV = 2252 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex, 2253 ARMCP::CPLSDA, PCAdj); 2254 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2255 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2256 SDValue Result = 2257 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2258 MachinePointerInfo::getConstantPool(), 2259 false, false, 0); 2260 2261 if (RelocM == Reloc::PIC_) { 2262 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2263 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2264 } 2265 return Result; 2266 } 2267 case Intrinsic::arm_neon_vmulls: 2268 case Intrinsic::arm_neon_vmullu: { 2269 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) 2270 ? ARMISD::VMULLs : ARMISD::VMULLu; 2271 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(), 2272 Op.getOperand(1), Op.getOperand(2)); 2273 } 2274 } 2275 } 2276 2277 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG, 2278 const ARMSubtarget *Subtarget) { 2279 DebugLoc dl = Op.getDebugLoc(); 2280 if (!Subtarget->hasDataBarrier()) { 2281 // Some ARMv6 cpus can support data barriers with an mcr instruction. 2282 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get 2283 // here. 2284 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && 2285 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!"); 2286 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0), 2287 DAG.getConstant(0, MVT::i32)); 2288 } 2289 2290 SDValue Op5 = Op.getOperand(5); 2291 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0; 2292 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 2293 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 2294 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0); 2295 2296 ARM_MB::MemBOpt DMBOpt; 2297 if (isDeviceBarrier) 2298 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY; 2299 else 2300 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH; 2301 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), 2302 DAG.getConstant(DMBOpt, MVT::i32)); 2303 } 2304 2305 2306 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, 2307 const ARMSubtarget *Subtarget) { 2308 // FIXME: handle "fence singlethread" more efficiently. 2309 DebugLoc dl = Op.getDebugLoc(); 2310 if (!Subtarget->hasDataBarrier()) { 2311 // Some ARMv6 cpus can support data barriers with an mcr instruction. 2312 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get 2313 // here. 2314 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && 2315 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!"); 2316 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0), 2317 DAG.getConstant(0, MVT::i32)); 2318 } 2319 2320 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), 2321 DAG.getConstant(ARM_MB::ISH, MVT::i32)); 2322 } 2323 2324 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG, 2325 const ARMSubtarget *Subtarget) { 2326 // ARM pre v5TE and Thumb1 does not have preload instructions. 2327 if (!(Subtarget->isThumb2() || 2328 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps()))) 2329 // Just preserve the chain. 2330 return Op.getOperand(0); 2331 2332 DebugLoc dl = Op.getDebugLoc(); 2333 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1; 2334 if (!isRead && 2335 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension())) 2336 // ARMv7 with MP extension has PLDW. 2337 return Op.getOperand(0); 2338 2339 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 2340 if (Subtarget->isThumb()) { 2341 // Invert the bits. 2342 isRead = ~isRead & 1; 2343 isData = ~isData & 1; 2344 } 2345 2346 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0), 2347 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32), 2348 DAG.getConstant(isData, MVT::i32)); 2349 } 2350 2351 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) { 2352 MachineFunction &MF = DAG.getMachineFunction(); 2353 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>(); 2354 2355 // vastart just stores the address of the VarArgsFrameIndex slot into the 2356 // memory location argument. 2357 DebugLoc dl = Op.getDebugLoc(); 2358 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2359 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2360 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2361 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), 2362 MachinePointerInfo(SV), false, false, 0); 2363 } 2364 2365 SDValue 2366 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 2367 SDValue &Root, SelectionDAG &DAG, 2368 DebugLoc dl) const { 2369 MachineFunction &MF = DAG.getMachineFunction(); 2370 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2371 2372 TargetRegisterClass *RC; 2373 if (AFI->isThumb1OnlyFunction()) 2374 RC = ARM::tGPRRegisterClass; 2375 else 2376 RC = ARM::GPRRegisterClass; 2377 2378 // Transform the arguments stored in physical registers into virtual ones. 2379 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2380 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2381 2382 SDValue ArgValue2; 2383 if (NextVA.isMemLoc()) { 2384 MachineFrameInfo *MFI = MF.getFrameInfo(); 2385 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true); 2386 2387 // Create load node to retrieve arguments from the stack. 2388 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2389 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, 2390 MachinePointerInfo::getFixedStack(FI), 2391 false, false, 0); 2392 } else { 2393 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); 2394 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2395 } 2396 2397 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); 2398 } 2399 2400 void 2401 ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF, 2402 unsigned &VARegSize, unsigned &VARegSaveSize) 2403 const { 2404 unsigned NumGPRs; 2405 if (CCInfo.isFirstByValRegValid()) 2406 NumGPRs = ARM::R4 - CCInfo.getFirstByValReg(); 2407 else { 2408 unsigned int firstUnalloced; 2409 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs, 2410 sizeof(GPRArgRegs) / 2411 sizeof(GPRArgRegs[0])); 2412 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0; 2413 } 2414 2415 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment(); 2416 VARegSize = NumGPRs * 4; 2417 VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); 2418 } 2419 2420 // The remaining GPRs hold either the beginning of variable-argument 2421 // data, or the beginning of an aggregate passed by value (usuall 2422 // byval). Either way, we allocate stack slots adjacent to the data 2423 // provided by our caller, and store the unallocated registers there. 2424 // If this is a variadic function, the va_list pointer will begin with 2425 // these values; otherwise, this reassembles a (byval) structure that 2426 // was split between registers and memory. 2427 void 2428 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 2429 DebugLoc dl, SDValue &Chain, 2430 unsigned ArgOffset) const { 2431 MachineFunction &MF = DAG.getMachineFunction(); 2432 MachineFrameInfo *MFI = MF.getFrameInfo(); 2433 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2434 unsigned firstRegToSaveIndex; 2435 if (CCInfo.isFirstByValRegValid()) 2436 firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0; 2437 else { 2438 firstRegToSaveIndex = CCInfo.getFirstUnallocated 2439 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0])); 2440 } 2441 2442 unsigned VARegSize, VARegSaveSize; 2443 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize); 2444 if (VARegSaveSize) { 2445 // If this function is vararg, store any remaining integer argument regs 2446 // to their spots on the stack so that they may be loaded by deferencing 2447 // the result of va_next. 2448 AFI->setVarArgsRegSaveSize(VARegSaveSize); 2449 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(VARegSaveSize, 2450 ArgOffset + VARegSaveSize 2451 - VARegSize, 2452 false)); 2453 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), 2454 getPointerTy()); 2455 2456 SmallVector<SDValue, 4> MemOps; 2457 for (; firstRegToSaveIndex < 4; ++firstRegToSaveIndex) { 2458 TargetRegisterClass *RC; 2459 if (AFI->isThumb1OnlyFunction()) 2460 RC = ARM::tGPRRegisterClass; 2461 else 2462 RC = ARM::GPRRegisterClass; 2463 2464 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC); 2465 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 2466 SDValue Store = 2467 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2468 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()), 2469 false, false, 0); 2470 MemOps.push_back(Store); 2471 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, 2472 DAG.getConstant(4, getPointerTy())); 2473 } 2474 if (!MemOps.empty()) 2475 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2476 &MemOps[0], MemOps.size()); 2477 } else 2478 // This will point to the next argument passed via stack. 2479 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true)); 2480 } 2481 2482 SDValue 2483 ARMTargetLowering::LowerFormalArguments(SDValue Chain, 2484 CallingConv::ID CallConv, bool isVarArg, 2485 const SmallVectorImpl<ISD::InputArg> 2486 &Ins, 2487 DebugLoc dl, SelectionDAG &DAG, 2488 SmallVectorImpl<SDValue> &InVals) 2489 const { 2490 MachineFunction &MF = DAG.getMachineFunction(); 2491 MachineFrameInfo *MFI = MF.getFrameInfo(); 2492 2493 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2494 2495 // Assign locations to all of the incoming arguments. 2496 SmallVector<CCValAssign, 16> ArgLocs; 2497 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2498 getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue); 2499 CCInfo.AnalyzeFormalArguments(Ins, 2500 CCAssignFnForNode(CallConv, /* Return*/ false, 2501 isVarArg)); 2502 2503 SmallVector<SDValue, 16> ArgValues; 2504 int lastInsIndex = -1; 2505 2506 SDValue ArgValue; 2507 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2508 CCValAssign &VA = ArgLocs[i]; 2509 2510 // Arguments stored in registers. 2511 if (VA.isRegLoc()) { 2512 EVT RegVT = VA.getLocVT(); 2513 2514 if (VA.needsCustom()) { 2515 // f64 and vector types are split up into multiple registers or 2516 // combinations of registers and stack slots. 2517 if (VA.getLocVT() == MVT::v2f64) { 2518 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i], 2519 Chain, DAG, dl); 2520 VA = ArgLocs[++i]; // skip ahead to next loc 2521 SDValue ArgValue2; 2522 if (VA.isMemLoc()) { 2523 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true); 2524 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2525 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN, 2526 MachinePointerInfo::getFixedStack(FI), 2527 false, false, 0); 2528 } else { 2529 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], 2530 Chain, DAG, dl); 2531 } 2532 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 2533 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2534 ArgValue, ArgValue1, DAG.getIntPtrConstant(0)); 2535 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2536 ArgValue, ArgValue2, DAG.getIntPtrConstant(1)); 2537 } else 2538 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); 2539 2540 } else { 2541 TargetRegisterClass *RC; 2542 2543 if (RegVT == MVT::f32) 2544 RC = ARM::SPRRegisterClass; 2545 else if (RegVT == MVT::f64) 2546 RC = ARM::DPRRegisterClass; 2547 else if (RegVT == MVT::v2f64) 2548 RC = ARM::QPRRegisterClass; 2549 else if (RegVT == MVT::i32) 2550 RC = (AFI->isThumb1OnlyFunction() ? 2551 ARM::tGPRRegisterClass : ARM::GPRRegisterClass); 2552 else 2553 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering"); 2554 2555 // Transform the arguments in physical registers into virtual ones. 2556 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2557 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2558 } 2559 2560 // If this is an 8 or 16-bit value, it is really passed promoted 2561 // to 32 bits. Insert an assert[sz]ext to capture this, then 2562 // truncate to the right size. 2563 switch (VA.getLocInfo()) { 2564 default: llvm_unreachable("Unknown loc info!"); 2565 case CCValAssign::Full: break; 2566 case CCValAssign::BCvt: 2567 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 2568 break; 2569 case CCValAssign::SExt: 2570 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 2571 DAG.getValueType(VA.getValVT())); 2572 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2573 break; 2574 case CCValAssign::ZExt: 2575 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 2576 DAG.getValueType(VA.getValVT())); 2577 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2578 break; 2579 } 2580 2581 InVals.push_back(ArgValue); 2582 2583 } else { // VA.isRegLoc() 2584 2585 // sanity check 2586 assert(VA.isMemLoc()); 2587 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered"); 2588 2589 int index = ArgLocs[i].getValNo(); 2590 2591 // Some Ins[] entries become multiple ArgLoc[] entries. 2592 // Process them only once. 2593 if (index != lastInsIndex) 2594 { 2595 ISD::ArgFlagsTy Flags = Ins[index].Flags; 2596 // FIXME: For now, all byval parameter objects are marked mutable. 2597 // This can be changed with more analysis. 2598 // In case of tail call optimization mark all arguments mutable. 2599 // Since they could be overwritten by lowering of arguments in case of 2600 // a tail call. 2601 if (Flags.isByVal()) { 2602 unsigned VARegSize, VARegSaveSize; 2603 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize); 2604 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, 0); 2605 unsigned Bytes = Flags.getByValSize() - VARegSize; 2606 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 2607 int FI = MFI->CreateFixedObject(Bytes, 2608 VA.getLocMemOffset(), false); 2609 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy())); 2610 } else { 2611 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8, 2612 VA.getLocMemOffset(), true); 2613 2614 // Create load nodes to retrieve arguments from the stack. 2615 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2616 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 2617 MachinePointerInfo::getFixedStack(FI), 2618 false, false, 0)); 2619 } 2620 lastInsIndex = index; 2621 } 2622 } 2623 } 2624 2625 // varargs 2626 if (isVarArg) 2627 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset()); 2628 2629 return Chain; 2630 } 2631 2632 /// isFloatingPointZero - Return true if this is +0.0. 2633 static bool isFloatingPointZero(SDValue Op) { 2634 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 2635 return CFP->getValueAPF().isPosZero(); 2636 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 2637 // Maybe this has already been legalized into the constant pool? 2638 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { 2639 SDValue WrapperOp = Op.getOperand(1).getOperand(0); 2640 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) 2641 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 2642 return CFP->getValueAPF().isPosZero(); 2643 } 2644 } 2645 return false; 2646 } 2647 2648 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for 2649 /// the given operands. 2650 SDValue 2651 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 2652 SDValue &ARMcc, SelectionDAG &DAG, 2653 DebugLoc dl) const { 2654 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { 2655 unsigned C = RHSC->getZExtValue(); 2656 if (!isLegalICmpImmediate(C)) { 2657 // Constant does not fit, try adjusting it by one? 2658 switch (CC) { 2659 default: break; 2660 case ISD::SETLT: 2661 case ISD::SETGE: 2662 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) { 2663 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 2664 RHS = DAG.getConstant(C-1, MVT::i32); 2665 } 2666 break; 2667 case ISD::SETULT: 2668 case ISD::SETUGE: 2669 if (C != 0 && isLegalICmpImmediate(C-1)) { 2670 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 2671 RHS = DAG.getConstant(C-1, MVT::i32); 2672 } 2673 break; 2674 case ISD::SETLE: 2675 case ISD::SETGT: 2676 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) { 2677 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 2678 RHS = DAG.getConstant(C+1, MVT::i32); 2679 } 2680 break; 2681 case ISD::SETULE: 2682 case ISD::SETUGT: 2683 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) { 2684 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 2685 RHS = DAG.getConstant(C+1, MVT::i32); 2686 } 2687 break; 2688 } 2689 } 2690 } 2691 2692 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 2693 ARMISD::NodeType CompareType; 2694 switch (CondCode) { 2695 default: 2696 CompareType = ARMISD::CMP; 2697 break; 2698 case ARMCC::EQ: 2699 case ARMCC::NE: 2700 // Uses only Z Flag 2701 CompareType = ARMISD::CMPZ; 2702 break; 2703 } 2704 ARMcc = DAG.getConstant(CondCode, MVT::i32); 2705 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS); 2706 } 2707 2708 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. 2709 SDValue 2710 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, 2711 DebugLoc dl) const { 2712 SDValue Cmp; 2713 if (!isFloatingPointZero(RHS)) 2714 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS); 2715 else 2716 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS); 2717 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp); 2718 } 2719 2720 /// duplicateCmp - Glue values can have only one use, so this function 2721 /// duplicates a comparison node. 2722 SDValue 2723 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const { 2724 unsigned Opc = Cmp.getOpcode(); 2725 DebugLoc DL = Cmp.getDebugLoc(); 2726 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ) 2727 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1)); 2728 2729 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation"); 2730 Cmp = Cmp.getOperand(0); 2731 Opc = Cmp.getOpcode(); 2732 if (Opc == ARMISD::CMPFP) 2733 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1)); 2734 else { 2735 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"); 2736 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0)); 2737 } 2738 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp); 2739 } 2740 2741 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 2742 SDValue Cond = Op.getOperand(0); 2743 SDValue SelectTrue = Op.getOperand(1); 2744 SDValue SelectFalse = Op.getOperand(2); 2745 DebugLoc dl = Op.getDebugLoc(); 2746 2747 // Convert: 2748 // 2749 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond) 2750 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond) 2751 // 2752 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) { 2753 const ConstantSDNode *CMOVTrue = 2754 dyn_cast<ConstantSDNode>(Cond.getOperand(0)); 2755 const ConstantSDNode *CMOVFalse = 2756 dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 2757 2758 if (CMOVTrue && CMOVFalse) { 2759 unsigned CMOVTrueVal = CMOVTrue->getZExtValue(); 2760 unsigned CMOVFalseVal = CMOVFalse->getZExtValue(); 2761 2762 SDValue True; 2763 SDValue False; 2764 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) { 2765 True = SelectTrue; 2766 False = SelectFalse; 2767 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) { 2768 True = SelectFalse; 2769 False = SelectTrue; 2770 } 2771 2772 if (True.getNode() && False.getNode()) { 2773 EVT VT = Op.getValueType(); 2774 SDValue ARMcc = Cond.getOperand(2); 2775 SDValue CCR = Cond.getOperand(3); 2776 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG); 2777 assert(True.getValueType() == VT); 2778 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp); 2779 } 2780 } 2781 } 2782 2783 return DAG.getSelectCC(dl, Cond, 2784 DAG.getConstant(0, Cond.getValueType()), 2785 SelectTrue, SelectFalse, ISD::SETNE); 2786 } 2787 2788 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 2789 EVT VT = Op.getValueType(); 2790 SDValue LHS = Op.getOperand(0); 2791 SDValue RHS = Op.getOperand(1); 2792 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 2793 SDValue TrueVal = Op.getOperand(2); 2794 SDValue FalseVal = Op.getOperand(3); 2795 DebugLoc dl = Op.getDebugLoc(); 2796 2797 if (LHS.getValueType() == MVT::i32) { 2798 SDValue ARMcc; 2799 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2800 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2801 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp); 2802 } 2803 2804 ARMCC::CondCodes CondCode, CondCode2; 2805 FPCCToARMCC(CC, CondCode, CondCode2); 2806 2807 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32); 2808 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 2809 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2810 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, 2811 ARMcc, CCR, Cmp); 2812 if (CondCode2 != ARMCC::AL) { 2813 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32); 2814 // FIXME: Needs another CMP because flag can have but one use. 2815 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl); 2816 Result = DAG.getNode(ARMISD::CMOV, dl, VT, 2817 Result, TrueVal, ARMcc2, CCR, Cmp2); 2818 } 2819 return Result; 2820 } 2821 2822 /// canChangeToInt - Given the fp compare operand, return true if it is suitable 2823 /// to morph to an integer compare sequence. 2824 static bool canChangeToInt(SDValue Op, bool &SeenZero, 2825 const ARMSubtarget *Subtarget) { 2826 SDNode *N = Op.getNode(); 2827 if (!N->hasOneUse()) 2828 // Otherwise it requires moving the value from fp to integer registers. 2829 return false; 2830 if (!N->getNumValues()) 2831 return false; 2832 EVT VT = Op.getValueType(); 2833 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow()) 2834 // f32 case is generally profitable. f64 case only makes sense when vcmpe + 2835 // vmrs are very slow, e.g. cortex-a8. 2836 return false; 2837 2838 if (isFloatingPointZero(Op)) { 2839 SeenZero = true; 2840 return true; 2841 } 2842 return ISD::isNormalLoad(N); 2843 } 2844 2845 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) { 2846 if (isFloatingPointZero(Op)) 2847 return DAG.getConstant(0, MVT::i32); 2848 2849 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) 2850 return DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2851 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(), 2852 Ld->isVolatile(), Ld->isNonTemporal(), 2853 Ld->getAlignment()); 2854 2855 llvm_unreachable("Unknown VFP cmp argument!"); 2856 } 2857 2858 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG, 2859 SDValue &RetVal1, SDValue &RetVal2) { 2860 if (isFloatingPointZero(Op)) { 2861 RetVal1 = DAG.getConstant(0, MVT::i32); 2862 RetVal2 = DAG.getConstant(0, MVT::i32); 2863 return; 2864 } 2865 2866 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) { 2867 SDValue Ptr = Ld->getBasePtr(); 2868 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2869 Ld->getChain(), Ptr, 2870 Ld->getPointerInfo(), 2871 Ld->isVolatile(), Ld->isNonTemporal(), 2872 Ld->getAlignment()); 2873 2874 EVT PtrType = Ptr.getValueType(); 2875 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4); 2876 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(), 2877 PtrType, Ptr, DAG.getConstant(4, PtrType)); 2878 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2879 Ld->getChain(), NewPtr, 2880 Ld->getPointerInfo().getWithOffset(4), 2881 Ld->isVolatile(), Ld->isNonTemporal(), 2882 NewAlign); 2883 return; 2884 } 2885 2886 llvm_unreachable("Unknown VFP cmp argument!"); 2887 } 2888 2889 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some 2890 /// f32 and even f64 comparisons to integer ones. 2891 SDValue 2892 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const { 2893 SDValue Chain = Op.getOperand(0); 2894 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 2895 SDValue LHS = Op.getOperand(2); 2896 SDValue RHS = Op.getOperand(3); 2897 SDValue Dest = Op.getOperand(4); 2898 DebugLoc dl = Op.getDebugLoc(); 2899 2900 bool SeenZero = false; 2901 if (canChangeToInt(LHS, SeenZero, Subtarget) && 2902 canChangeToInt(RHS, SeenZero, Subtarget) && 2903 // If one of the operand is zero, it's safe to ignore the NaN case since 2904 // we only care about equality comparisons. 2905 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) { 2906 // If unsafe fp math optimization is enabled and there are no other uses of 2907 // the CMP operands, and the condition code is EQ or NE, we can optimize it 2908 // to an integer comparison. 2909 if (CC == ISD::SETOEQ) 2910 CC = ISD::SETEQ; 2911 else if (CC == ISD::SETUNE) 2912 CC = ISD::SETNE; 2913 2914 SDValue ARMcc; 2915 if (LHS.getValueType() == MVT::f32) { 2916 LHS = bitcastf32Toi32(LHS, DAG); 2917 RHS = bitcastf32Toi32(RHS, DAG); 2918 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2919 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2920 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 2921 Chain, Dest, ARMcc, CCR, Cmp); 2922 } 2923 2924 SDValue LHS1, LHS2; 2925 SDValue RHS1, RHS2; 2926 expandf64Toi32(LHS, DAG, LHS1, LHS2); 2927 expandf64Toi32(RHS, DAG, RHS1, RHS2); 2928 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 2929 ARMcc = DAG.getConstant(CondCode, MVT::i32); 2930 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); 2931 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; 2932 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7); 2933 } 2934 2935 return SDValue(); 2936 } 2937 2938 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 2939 SDValue Chain = Op.getOperand(0); 2940 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 2941 SDValue LHS = Op.getOperand(2); 2942 SDValue RHS = Op.getOperand(3); 2943 SDValue Dest = Op.getOperand(4); 2944 DebugLoc dl = Op.getDebugLoc(); 2945 2946 if (LHS.getValueType() == MVT::i32) { 2947 SDValue ARMcc; 2948 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2949 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2950 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 2951 Chain, Dest, ARMcc, CCR, Cmp); 2952 } 2953 2954 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 2955 2956 if (UnsafeFPMath && 2957 (CC == ISD::SETEQ || CC == ISD::SETOEQ || 2958 CC == ISD::SETNE || CC == ISD::SETUNE)) { 2959 SDValue Result = OptimizeVFPBrcond(Op, DAG); 2960 if (Result.getNode()) 2961 return Result; 2962 } 2963 2964 ARMCC::CondCodes CondCode, CondCode2; 2965 FPCCToARMCC(CC, CondCode, CondCode2); 2966 2967 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32); 2968 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 2969 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2970 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); 2971 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp }; 2972 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 2973 if (CondCode2 != ARMCC::AL) { 2974 ARMcc = DAG.getConstant(CondCode2, MVT::i32); 2975 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) }; 2976 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 2977 } 2978 return Res; 2979 } 2980 2981 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 2982 SDValue Chain = Op.getOperand(0); 2983 SDValue Table = Op.getOperand(1); 2984 SDValue Index = Op.getOperand(2); 2985 DebugLoc dl = Op.getDebugLoc(); 2986 2987 EVT PTy = getPointerTy(); 2988 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 2989 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); 2990 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); 2991 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); 2992 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId); 2993 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy)); 2994 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 2995 if (Subtarget->isThumb2()) { 2996 // Thumb2 uses a two-level jump. That is, it jumps into the jump table 2997 // which does another jump to the destination. This also makes it easier 2998 // to translate it to TBB / TBH later. 2999 // FIXME: This might not work if the function is extremely large. 3000 return DAG.getNode(ARMISD::BR2_J