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      1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the base ARM implementation of TargetRegisterInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "ARMBaseRegisterInfo.h"
     15 #include "ARM.h"
     16 #include "ARMBaseInstrInfo.h"
     17 #include "ARMFrameLowering.h"
     18 #include "ARMMachineFunctionInfo.h"
     19 #include "ARMSubtarget.h"
     20 #include "MCTargetDesc/ARMAddressingModes.h"
     21 #include "llvm/Constants.h"
     22 #include "llvm/DerivedTypes.h"
     23 #include "llvm/Function.h"
     24 #include "llvm/LLVMContext.h"
     25 #include "llvm/CodeGen/MachineConstantPool.h"
     26 #include "llvm/CodeGen/MachineFrameInfo.h"
     27 #include "llvm/CodeGen/MachineFunction.h"
     28 #include "llvm/CodeGen/MachineInstrBuilder.h"
     29 #include "llvm/CodeGen/MachineRegisterInfo.h"
     30 #include "llvm/CodeGen/RegisterScavenging.h"
     31 #include "llvm/Support/Debug.h"
     32 #include "llvm/Support/ErrorHandling.h"
     33 #include "llvm/Support/raw_ostream.h"
     34 #include "llvm/Target/TargetFrameLowering.h"
     35 #include "llvm/Target/TargetMachine.h"
     36 #include "llvm/Target/TargetOptions.h"
     37 #include "llvm/ADT/BitVector.h"
     38 #include "llvm/ADT/SmallVector.h"
     39 #include "llvm/Support/CommandLine.h"
     40 
     41 #define GET_REGINFO_TARGET_DESC
     42 #include "ARMGenRegisterInfo.inc"
     43 
     44 using namespace llvm;
     45 
     46 static cl::opt<bool>
     47 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
     48           cl::desc("Force use of virtual base registers for stack load/store"));
     49 static cl::opt<bool>
     50 EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
     51           cl::desc("Enable pre-regalloc stack frame index allocation"));
     52 static cl::opt<bool>
     53 EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
     54           cl::desc("Enable use of a base pointer for complex stack frames"));
     55 
     56 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
     57                                          const ARMSubtarget &sti)
     58   : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti),
     59     FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
     60     BasePtr(ARM::R6) {
     61 }
     62 
     63 const uint16_t*
     64 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
     65   return (STI.isTargetIOS()) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
     66 }
     67 
     68 const uint32_t*
     69 ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
     70   return (STI.isTargetIOS()) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
     71 }
     72 
     73 BitVector ARMBaseRegisterInfo::
     74 getReservedRegs(const MachineFunction &MF) const {
     75   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
     76 
     77   // FIXME: avoid re-calculating this every time.
     78   BitVector Reserved(getNumRegs());
     79   Reserved.set(ARM::SP);
     80   Reserved.set(ARM::PC);
     81   Reserved.set(ARM::FPSCR);
     82   if (TFI->hasFP(MF))
     83     Reserved.set(FramePtr);
     84   if (hasBasePointer(MF))
     85     Reserved.set(BasePtr);
     86   // Some targets reserve R9.
     87   if (STI.isR9Reserved())
     88     Reserved.set(ARM::R9);
     89   // Reserve D16-D31 if the subtarget doesn't support them.
     90   if (!STI.hasVFP3() || STI.hasD16()) {
     91     assert(ARM::D31 == ARM::D16 + 15);
     92     for (unsigned i = 0; i != 16; ++i)
     93       Reserved.set(ARM::D16 + i);
     94   }
     95   return Reserved;
     96 }
     97 
     98 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
     99                                         unsigned Reg) const {
    100   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    101 
    102   switch (Reg) {
    103   default: break;
    104   case ARM::SP:
    105   case ARM::PC:
    106     return true;
    107   case ARM::R6:
    108     if (hasBasePointer(MF))
    109       return true;
    110     break;
    111   case ARM::R7:
    112   case ARM::R11:
    113     if (FramePtr == Reg && TFI->hasFP(MF))
    114       return true;
    115     break;
    116   case ARM::R9:
    117     return STI.isR9Reserved();
    118   }
    119 
    120   return false;
    121 }
    122 
    123 bool
    124 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
    125                                           SmallVectorImpl<unsigned> &SubIndices,
    126                                           unsigned &NewSubIdx) const {
    127 
    128   unsigned Size = RC->getSize() * 8;
    129   if (Size < 6)
    130     return 0;
    131 
    132   NewSubIdx = 0;  // Whole register.
    133   unsigned NumRegs = SubIndices.size();
    134   if (NumRegs == 8) {
    135     // 8 D registers -> 1 QQQQ register.
    136     return (Size == 512 &&
    137             SubIndices[0] == ARM::dsub_0 &&
    138             SubIndices[1] == ARM::dsub_1 &&
    139             SubIndices[2] == ARM::dsub_2 &&
    140             SubIndices[3] == ARM::dsub_3 &&
    141             SubIndices[4] == ARM::dsub_4 &&
    142             SubIndices[5] == ARM::dsub_5 &&
    143             SubIndices[6] == ARM::dsub_6 &&
    144             SubIndices[7] == ARM::dsub_7);
    145   } else if (NumRegs == 4) {
    146     if (SubIndices[0] == ARM::qsub_0) {
    147       // 4 Q registers -> 1 QQQQ register.
    148       return (Size == 512 &&
    149               SubIndices[1] == ARM::qsub_1 &&
    150               SubIndices[2] == ARM::qsub_2 &&
    151               SubIndices[3] == ARM::qsub_3);
    152     } else if (SubIndices[0] == ARM::dsub_0) {
    153       // 4 D registers -> 1 QQ register.
    154       if (Size >= 256 &&
    155           SubIndices[1] == ARM::dsub_1 &&
    156           SubIndices[2] == ARM::dsub_2 &&
    157           SubIndices[3] == ARM::dsub_3) {
    158         if (Size == 512)
    159           NewSubIdx = ARM::qqsub_0;
    160         return true;
    161       }
    162     } else if (SubIndices[0] == ARM::dsub_4) {
    163       // 4 D registers -> 1 QQ register (2nd).
    164       if (Size == 512 &&
    165           SubIndices[1] == ARM::dsub_5 &&
    166           SubIndices[2] == ARM::dsub_6 &&
    167           SubIndices[3] == ARM::dsub_7) {
    168         NewSubIdx = ARM::qqsub_1;
    169         return true;
    170       }
    171     } else if (SubIndices[0] == ARM::ssub_0) {
    172       // 4 S registers -> 1 Q register.
    173       if (Size >= 128 &&
    174           SubIndices[1] == ARM::ssub_1 &&
    175           SubIndices[2] == ARM::ssub_2 &&
    176           SubIndices[3] == ARM::ssub_3) {
    177         if (Size >= 256)
    178           NewSubIdx = ARM::qsub_0;
    179         return true;
    180       }
    181     }
    182   } else if (NumRegs == 2) {
    183     if (SubIndices[0] == ARM::qsub_0) {
    184       // 2 Q registers -> 1 QQ register.
    185       if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
    186         if (Size == 512)
    187           NewSubIdx = ARM::qqsub_0;
    188         return true;
    189       }
    190     } else if (SubIndices[0] == ARM::qsub_2) {
    191       // 2 Q registers -> 1 QQ register (2nd).
    192       if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
    193         NewSubIdx = ARM::qqsub_1;
    194         return true;
    195       }
    196     } else if (SubIndices[0] == ARM::dsub_0) {
    197       // 2 D registers -> 1 Q register.
    198       if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
    199         if (Size >= 256)
    200           NewSubIdx = ARM::qsub_0;
    201         return true;
    202       }
    203     } else if (SubIndices[0] == ARM::dsub_2) {
    204       // 2 D registers -> 1 Q register (2nd).
    205       if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
    206         NewSubIdx = ARM::qsub_1;
    207         return true;
    208       }
    209     } else if (SubIndices[0] == ARM::dsub_4) {
    210       // 2 D registers -> 1 Q register (3rd).
    211       if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
    212         NewSubIdx = ARM::qsub_2;
    213         return true;
    214       }
    215     } else if (SubIndices[0] == ARM::dsub_6) {
    216       // 2 D registers -> 1 Q register (3rd).
    217       if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
    218         NewSubIdx = ARM::qsub_3;
    219         return true;
    220       }
    221     } else if (SubIndices[0] == ARM::ssub_0) {
    222       // 2 S registers -> 1 D register.
    223       if (SubIndices[1] == ARM::ssub_1) {
    224         if (Size >= 128)
    225           NewSubIdx = ARM::dsub_0;
    226         return true;
    227       }
    228     } else if (SubIndices[0] == ARM::ssub_2) {
    229       // 2 S registers -> 1 D register (2nd).
    230       if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
    231         NewSubIdx = ARM::dsub_1;
    232         return true;
    233       }
    234     }
    235   }
    236   return false;
    237 }
    238 
    239 const TargetRegisterClass*
    240 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
    241                                                                          const {
    242   const TargetRegisterClass *Super = RC;
    243   TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
    244   do {
    245     switch (Super->getID()) {
    246     case ARM::GPRRegClassID:
    247     case ARM::SPRRegClassID:
    248     case ARM::DPRRegClassID:
    249     case ARM::QPRRegClassID:
    250     case ARM::QQPRRegClassID:
    251     case ARM::QQQQPRRegClassID:
    252       return Super;
    253     }
    254     Super = *I++;
    255   } while (Super);
    256   return RC;
    257 }
    258 
    259 const TargetRegisterClass *
    260 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
    261   return ARM::GPRRegisterClass;
    262 }
    263 
    264 const TargetRegisterClass *
    265 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
    266   if (RC == &ARM::CCRRegClass)
    267     return 0;  // Can't copy CCR registers.
    268   return RC;
    269 }
    270 
    271 unsigned
    272 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
    273                                          MachineFunction &MF) const {
    274   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    275 
    276   switch (RC->getID()) {
    277   default:
    278     return 0;
    279   case ARM::tGPRRegClassID:
    280     return TFI->hasFP(MF) ? 4 : 5;
    281   case ARM::GPRRegClassID: {
    282     unsigned FP = TFI->hasFP(MF) ? 1 : 0;
    283     return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
    284   }
    285   case ARM::SPRRegClassID:  // Currently not used as 'rep' register class.
    286   case ARM::DPRRegClassID:
    287     return 32 - 10;
    288   }
    289 }
    290 
    291 /// getRawAllocationOrder - Returns the register allocation order for a
    292 /// specified register class with a target-dependent hint.
    293 ArrayRef<uint16_t>
    294 ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC,
    295                                            unsigned HintType, unsigned HintReg,
    296                                            const MachineFunction &MF) const {
    297   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    298   // Alternative register allocation orders when favoring even / odd registers
    299   // of register pairs.
    300 
    301   // No FP, R9 is available.
    302   static const uint16_t GPREven1[] = {
    303     ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
    304     ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
    305     ARM::R9, ARM::R11
    306   };
    307   static const uint16_t GPROdd1[] = {
    308     ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
    309     ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
    310     ARM::R8, ARM::R10
    311   };
    312 
    313   // FP is R7, R9 is available.
    314   static const uint16_t GPREven2[] = {
    315     ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
    316     ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
    317     ARM::R9, ARM::R11
    318   };
    319   static const uint16_t GPROdd2[] = {
    320     ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
    321     ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
    322     ARM::R8, ARM::R10
    323   };
    324 
    325   // FP is R11, R9 is available.
    326   static const uint16_t GPREven3[] = {
    327     ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
    328     ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
    329     ARM::R9
    330   };
    331   static const uint16_t GPROdd3[] = {
    332     ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
    333     ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
    334     ARM::R8
    335   };
    336 
    337   // No FP, R9 is not available.
    338   static const uint16_t GPREven4[] = {
    339     ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
    340     ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
    341     ARM::R11
    342   };
    343   static const uint16_t GPROdd4[] = {
    344     ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
    345     ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
    346     ARM::R10
    347   };
    348 
    349   // FP is R7, R9 is not available.
    350   static const uint16_t GPREven5[] = {
    351     ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
    352     ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
    353     ARM::R11
    354   };
    355   static const uint16_t GPROdd5[] = {
    356     ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
    357     ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
    358     ARM::R10
    359   };
    360 
    361   // FP is R11, R9 is not available.
    362   static const uint16_t GPREven6[] = {
    363     ARM::R0, ARM::R2, ARM::R4, ARM::R6,
    364     ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
    365   };
    366   static const uint16_t GPROdd6[] = {
    367     ARM::R1, ARM::R3, ARM::R5, ARM::R7,
    368     ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
    369   };
    370 
    371   // We only support even/odd hints for GPR and rGPR.
    372   if (RC != ARM::GPRRegisterClass && RC != ARM::rGPRRegisterClass)
    373     return RC->getRawAllocationOrder(MF);
    374 
    375   if (HintType == ARMRI::RegPairEven) {
    376     if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
    377       // It's no longer possible to fulfill this hint. Return the default
    378       // allocation order.
    379       return RC->getRawAllocationOrder(MF);
    380 
    381     if (!TFI->hasFP(MF)) {
    382       if (!STI.isR9Reserved())
    383         return makeArrayRef(GPREven1);
    384       else
    385         return makeArrayRef(GPREven4);
    386     } else if (FramePtr == ARM::R7) {
    387       if (!STI.isR9Reserved())
    388         return makeArrayRef(GPREven2);
    389       else
    390         return makeArrayRef(GPREven5);
    391     } else { // FramePtr == ARM::R11
    392       if (!STI.isR9Reserved())
    393         return makeArrayRef(GPREven3);
    394       else
    395         return makeArrayRef(GPREven6);
    396     }
    397   } else if (HintType == ARMRI::RegPairOdd) {
    398     if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
    399       // It's no longer possible to fulfill this hint. Return the default
    400       // allocation order.
    401       return RC->getRawAllocationOrder(MF);
    402 
    403     if (!TFI->hasFP(MF)) {
    404       if (!STI.isR9Reserved())
    405         return makeArrayRef(GPROdd1);
    406       else
    407         return makeArrayRef(GPROdd4);
    408     } else if (FramePtr == ARM::R7) {
    409       if (!STI.isR9Reserved())
    410         return makeArrayRef(GPROdd2);
    411       else
    412         return makeArrayRef(GPROdd5);
    413     } else { // FramePtr == ARM::R11
    414       if (!STI.isR9Reserved())
    415         return makeArrayRef(GPROdd3);
    416       else
    417         return makeArrayRef(GPROdd6);
    418     }
    419   }
    420   return RC->getRawAllocationOrder(MF);
    421 }
    422 
    423 /// ResolveRegAllocHint - Resolves the specified register allocation hint
    424 /// to a physical register. Returns the physical register if it is successful.
    425 unsigned
    426 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
    427                                          const MachineFunction &MF) const {
    428   if (Reg == 0 || !isPhysicalRegister(Reg))
    429     return 0;
    430   if (Type == 0)
    431     return Reg;
    432   else if (Type == (unsigned)ARMRI::RegPairOdd)
    433     // Odd register.
    434     return getRegisterPairOdd(Reg, MF);
    435   else if (Type == (unsigned)ARMRI::RegPairEven)
    436     // Even register.
    437     return getRegisterPairEven(Reg, MF);
    438   return 0;
    439 }
    440 
    441 void
    442 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
    443                                         MachineFunction &MF) const {
    444   MachineRegisterInfo *MRI = &MF.getRegInfo();
    445   std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
    446   if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
    447        Hint.first == (unsigned)ARMRI::RegPairEven) &&
    448       TargetRegisterInfo::isVirtualRegister(Hint.second)) {
    449     // If 'Reg' is one of the even / odd register pair and it's now changed
    450     // (e.g. coalesced) into a different register. The other register of the
    451     // pair allocation hint must be updated to reflect the relationship
    452     // change.
    453     unsigned OtherReg = Hint.second;
    454     Hint = MRI->getRegAllocationHint(OtherReg);
    455     if (Hint.second == Reg)
    456       // Make sure the pair has not already divorced.
    457       MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
    458   }
    459 }
    460 
    461 bool
    462 ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
    463   // CortexA9 has a Write-after-write hazard for NEON registers.
    464   if (!STI.isCortexA9())
    465     return false;
    466 
    467   switch (RC->getID()) {
    468   case ARM::DPRRegClassID:
    469   case ARM::DPR_8RegClassID:
    470   case ARM::DPR_VFP2RegClassID:
    471   case ARM::QPRRegClassID:
    472   case ARM::QPR_8RegClassID:
    473   case ARM::QPR_VFP2RegClassID:
    474   case ARM::SPRRegClassID:
    475   case ARM::SPR_8RegClassID:
    476     // Avoid reusing S, D, and Q registers.
    477     // Don't increase register pressure for QQ and QQQQ.
    478     return true;
    479   default:
    480     return false;
    481   }
    482 }
    483 
    484 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
    485   const MachineFrameInfo *MFI = MF.getFrameInfo();
    486   const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
    487   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    488 
    489   if (!EnableBasePointer)
    490     return false;
    491 
    492   // When outgoing call frames are so large that we adjust the stack pointer
    493   // around the call, we can no longer use the stack pointer to reach the
    494   // emergency spill slot.
    495   if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
    496     return true;
    497 
    498   // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
    499   // negative range for ldr/str (255), and thumb1 is positive offsets only.
    500   // It's going to be better to use the SP or Base Pointer instead. When there
    501   // are variable sized objects, we can't reference off of the SP, so we
    502   // reserve a Base Pointer.
    503   if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
    504     // Conservatively estimate whether the negative offset from the frame
    505     // pointer will be sufficient to reach. If a function has a smallish
    506     // frame, it's less likely to have lots of spills and callee saved
    507     // space, so it's all more likely to be within range of the frame pointer.
    508     // If it's wrong, the scavenger will still enable access to work, it just
    509     // won't be optimal.
    510     if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
    511       return false;
    512     return true;
    513   }
    514 
    515   return false;
    516 }
    517 
    518 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
    519   const MachineRegisterInfo *MRI = &MF.getRegInfo();
    520   const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
    521   // We can't realign the stack if:
    522   // 1. Dynamic stack realignment is explicitly disabled,
    523   // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
    524   // 3. There are VLAs in the function and the base pointer is disabled.
    525   if (!MF.getTarget().Options.RealignStack)
    526     return false;
    527   if (AFI->isThumb1OnlyFunction())
    528     return false;
    529   // Stack realignment requires a frame pointer.  If we already started
    530   // register allocation with frame pointer elimination, it is too late now.
    531   if (!MRI->canReserveReg(FramePtr))
    532     return false;
    533   // We may also need a base pointer if there are dynamic allocas or stack
    534   // pointer adjustments around calls.
    535   if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF))
    536     return true;
    537   if (!EnableBasePointer)
    538     return false;
    539   // A base pointer is required and allowed.  Check that it isn't too late to
    540   // reserve it.
    541   return MRI->canReserveReg(BasePtr);
    542 }
    543 
    544 bool ARMBaseRegisterInfo::
    545 needsStackRealignment(const MachineFunction &MF) const {
    546   const MachineFrameInfo *MFI = MF.getFrameInfo();
    547   const Function *F = MF.getFunction();
    548   unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
    549   bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
    550                                F->hasFnAttr(Attribute::StackAlignment));
    551 
    552   return requiresRealignment && canRealignStack(MF);
    553 }
    554 
    555 bool ARMBaseRegisterInfo::
    556 cannotEliminateFrame(const MachineFunction &MF) const {
    557   const MachineFrameInfo *MFI = MF.getFrameInfo();
    558   if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack())
    559     return true;
    560   return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
    561     || needsStackRealignment(MF);
    562 }
    563 
    564 unsigned
    565 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
    566   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    567 
    568   if (TFI->hasFP(MF))
    569     return FramePtr;
    570   return ARM::SP;
    571 }
    572 
    573 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
    574   llvm_unreachable("What is the exception register");
    575 }
    576 
    577 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
    578   llvm_unreachable("What is the exception handler register");
    579 }
    580 
    581 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
    582                                               const MachineFunction &MF) const {
    583   switch (Reg) {
    584   default: break;
    585   // Return 0 if either register of the pair is a special register.
    586   // So no R12, etc.
    587   case ARM::R1: return ARM::R0;
    588   case ARM::R3: return ARM::R2;
    589   case ARM::R5: return ARM::R4;
    590   case ARM::R7:
    591     return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
    592       ? 0 : ARM::R6;
    593   case ARM::R9: return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
    594   case ARM::R11: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
    595 
    596   case ARM::S1: return ARM::S0;
    597   case ARM::S3: return ARM::S2;
    598   case ARM::S5: return ARM::S4;
    599   case ARM::S7: return ARM::S6;
    600   case ARM::S9: return ARM::S8;
    601   case ARM::S11: return ARM::S10;
    602   case ARM::S13: return ARM::S12;
    603   case ARM::S15: return ARM::S14;
    604   case ARM::S17: return ARM::S16;
    605   case ARM::S19: return ARM::S18;
    606   case ARM::S21: return ARM::S20;
    607   case ARM::S23: return ARM::S22;
    608   case ARM::S25: return ARM::S24;
    609   case ARM::S27: return ARM::S26;
    610   case ARM::S29: return ARM::S28;
    611   case ARM::S31: return ARM::S30;
    612 
    613   case ARM::D1: return ARM::D0;
    614   case ARM::D3: return ARM::D2;
    615   case ARM::D5: return ARM::D4;
    616   case ARM::D7: return ARM::D6;
    617   case ARM::D9: return ARM::D8;
    618   case ARM::D11: return ARM::D10;
    619   case ARM::D13: return ARM::D12;
    620   case ARM::D15: return ARM::D14;
    621   case ARM::D17: return ARM::D16;
    622   case ARM::D19: return ARM::D18;
    623   case ARM::D21: return ARM::D20;
    624   case ARM::D23: return ARM::D22;
    625   case ARM::D25: return ARM::D24;
    626   case ARM::D27: return ARM::D26;
    627   case ARM::D29: return ARM::D28;
    628   case ARM::D31: return ARM::D30;
    629   }
    630 
    631   return 0;
    632 }
    633 
    634 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
    635                                              const MachineFunction &MF) const {
    636   switch (Reg) {
    637   default: break;
    638   // Return 0 if either register of the pair is a special register.
    639   // So no R12, etc.
    640   case ARM::R0: return ARM::R1;
    641   case ARM::R2: return ARM::R3;
    642   case ARM::R4: return ARM::R5;
    643   case ARM::R6:
    644     return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
    645       ? 0 : ARM::R7;
    646   case ARM::R8: return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
    647   case ARM::R10: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
    648 
    649   case ARM::S0: return ARM::S1;
    650   case ARM::S2: return ARM::S3;
    651   case ARM::S4: return ARM::S5;
    652   case ARM::S6: return ARM::S7;
    653   case ARM::S8: return ARM::S9;
    654   case ARM::S10: return ARM::S11;
    655   case ARM::S12: return ARM::S13;
    656   case ARM::S14: return ARM::S15;
    657   case ARM::S16: return ARM::S17;
    658   case ARM::S18: return ARM::S19;
    659   case ARM::S20: return ARM::S21;
    660   case ARM::S22: return ARM::S23;
    661   case ARM::S24: return ARM::S25;
    662   case ARM::S26: return ARM::S27;
    663   case ARM::S28: return ARM::S29;
    664   case ARM::S30: return ARM::S31;
    665 
    666   case ARM::D0: return ARM::D1;
    667   case ARM::D2: return ARM::D3;
    668   case ARM::D4: return ARM::D5;
    669   case ARM::D6: return ARM::D7;
    670   case ARM::D8: return ARM::D9;
    671   case ARM::D10: return ARM::D11;
    672   case ARM::D12: return ARM::D13;
    673   case ARM::D14: return ARM::D15;
    674   case ARM::D16: return ARM::D17;
    675   case ARM::D18: return ARM::D19;
    676   case ARM::D20: return ARM::D21;
    677   case ARM::D22: return ARM::D23;
    678   case ARM::D24: return ARM::D25;
    679   case ARM::D26: return ARM::D27;
    680   case ARM::D28: return ARM::D29;
    681   case ARM::D30: return ARM::D31;
    682   }
    683 
    684   return 0;
    685 }
    686 
    687 /// emitLoadConstPool - Emits a load from constpool to materialize the
    688 /// specified immediate.
    689 void ARMBaseRegisterInfo::
    690 emitLoadConstPool(MachineBasicBlock &MBB,
    691                   MachineBasicBlock::iterator &MBBI,
    692                   DebugLoc dl,
    693                   unsigned DestReg, unsigned SubIdx, int Val,
    694                   ARMCC::CondCodes Pred,
    695                   unsigned PredReg, unsigned MIFlags) const {
    696   MachineFunction &MF = *MBB.getParent();
    697   MachineConstantPool *ConstantPool = MF.getConstantPool();
    698   const Constant *C =
    699         ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
    700   unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
    701 
    702   BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
    703     .addReg(DestReg, getDefRegState(true), SubIdx)
    704     .addConstantPoolIndex(Idx)
    705     .addImm(0).addImm(Pred).addReg(PredReg)
    706     .setMIFlags(MIFlags);
    707 }
    708 
    709 bool ARMBaseRegisterInfo::
    710 requiresRegisterScavenging(const MachineFunction &MF) const {
    711   return true;
    712 }
    713 
    714 bool ARMBaseRegisterInfo::
    715 requiresFrameIndexScavenging(const MachineFunction &MF) const {
    716   return true;
    717 }
    718 
    719 bool ARMBaseRegisterInfo::
    720 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
    721   return EnableLocalStackAlloc;
    722 }
    723 
    724 static void
    725 emitSPUpdate(bool isARM,
    726              MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
    727              DebugLoc dl, const ARMBaseInstrInfo &TII,
    728              int NumBytes,
    729              ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
    730   if (isARM)
    731     emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
    732                             Pred, PredReg, TII);
    733   else
    734     emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
    735                            Pred, PredReg, TII);
    736 }
    737 
    738 
    739 void ARMBaseRegisterInfo::
    740 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
    741                               MachineBasicBlock::iterator I) const {
    742   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    743   if (!TFI->hasReservedCallFrame(MF)) {
    744     // If we have alloca, convert as follows:
    745     // ADJCALLSTACKDOWN -> sub, sp, sp, amount
    746     // ADJCALLSTACKUP   -> add, sp, sp, amount
    747     MachineInstr *Old = I;
    748     DebugLoc dl = Old->getDebugLoc();
    749     unsigned Amount = Old->getOperand(0).getImm();
    750     if (Amount != 0) {
    751       // We need to keep the stack aligned properly.  To do this, we round the
    752       // amount of space needed for the outgoing arguments up to the next
    753       // alignment boundary.
    754       unsigned Align = TFI->getStackAlignment();
    755       Amount = (Amount+Align-1)/Align*Align;
    756 
    757       ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
    758       assert(!AFI->isThumb1OnlyFunction() &&
    759              "This eliminateCallFramePseudoInstr does not support Thumb1!");
    760       bool isARM = !AFI->isThumbFunction();
    761 
    762       // Replace the pseudo instruction with a new instruction...
    763       unsigned Opc = Old->getOpcode();
    764       int PIdx = Old->findFirstPredOperandIdx();
    765       ARMCC::CondCodes Pred = (PIdx == -1)
    766         ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
    767       if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
    768         // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
    769         unsigned PredReg = Old->getOperand(2).getReg();
    770         emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
    771       } else {
    772         // Note: PredReg is operand 3 for ADJCALLSTACKUP.
    773         unsigned PredReg = Old->getOperand(3).getReg();
    774         assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
    775         emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
    776       }
    777     }
    778   }
    779   MBB.erase(I);
    780 }
    781 
    782 int64_t ARMBaseRegisterInfo::
    783 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
    784   const MCInstrDesc &Desc = MI->getDesc();
    785   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
    786   int64_t InstrOffs = 0;
    787   int Scale = 1;
    788   unsigned ImmIdx = 0;
    789   switch (AddrMode) {
    790   case ARMII::AddrModeT2_i8:
    791   case ARMII::AddrModeT2_i12:
    792   case ARMII::AddrMode_i12:
    793     InstrOffs = MI->getOperand(Idx+1).getImm();
    794     Scale = 1;
    795     break;
    796   case ARMII::AddrMode5: {
    797     // VFP address mode.
    798     const MachineOperand &OffOp = MI->getOperand(Idx+1);
    799     InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
    800     if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
    801       InstrOffs = -InstrOffs;
    802     Scale = 4;
    803     break;
    804   }
    805   case ARMII::AddrMode2: {
    806     ImmIdx = Idx+2;
    807     InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
    808     if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
    809       InstrOffs = -InstrOffs;
    810     break;
    811   }
    812   case ARMII::AddrMode3: {
    813     ImmIdx = Idx+2;
    814     InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
    815     if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
    816       InstrOffs = -InstrOffs;
    817     break;
    818   }
    819   case ARMII::AddrModeT1_s: {
    820     ImmIdx = Idx+1;
    821     InstrOffs = MI->getOperand(ImmIdx).getImm();
    822     Scale = 4;
    823     break;
    824   }
    825   default:
    826     llvm_unreachable("Unsupported addressing mode!");
    827   }
    828 
    829   return InstrOffs * Scale;
    830 }
    831 
    832 /// needsFrameBaseReg - Returns true if the instruction's frame index
    833 /// reference would be better served by a base register other than FP
    834 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
    835 /// references it should create new base registers for.
    836 bool ARMBaseRegisterInfo::
    837 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
    838   for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
    839     assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
    840   }
    841 
    842   // It's the load/store FI references that cause issues, as it can be difficult
    843   // to materialize the offset if it won't fit in the literal field. Estimate
    844   // based on the size of the local frame and some conservative assumptions
    845   // about the rest of the stack frame (note, this is pre-regalloc, so
    846   // we don't know everything for certain yet) whether this offset is likely
    847   // to be out of range of the immediate. Return true if so.
    848 
    849   // We only generate virtual base registers for loads and stores, so
    850   // return false for everything else.
    851   unsigned Opc = MI->getOpcode();
    852   switch (Opc) {
    853   case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
    854   case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
    855   case ARM::t2LDRi12: case ARM::t2LDRi8:
    856   case ARM::t2STRi12: case ARM::t2STRi8:
    857   case ARM::VLDRS: case ARM::VLDRD:
    858   case ARM::VSTRS: case ARM::VSTRD:
    859   case ARM::tSTRspi: case ARM::tLDRspi:
    860     if (ForceAllBaseRegAlloc)
    861       return true;
    862     break;
    863   default:
    864     return false;
    865   }
    866 
    867   // Without a virtual base register, if the function has variable sized
    868   // objects, all fixed-size local references will be via the frame pointer,
    869   // Approximate the offset and see if it's legal for the instruction.
    870   // Note that the incoming offset is based on the SP value at function entry,
    871   // so it'll be negative.
    872   MachineFunction &MF = *MI->getParent()->getParent();
    873   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    874   MachineFrameInfo *MFI = MF.getFrameInfo();
    875   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
    876 
    877   // Estimate an offset from the frame pointer.
    878   // Conservatively assume all callee-saved registers get pushed. R4-R6
    879   // will be earlier than the FP, so we ignore those.
    880   // R7, LR
    881   int64_t FPOffset = Offset - 8;
    882   // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
    883   if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
    884     FPOffset -= 80;
    885   // Estimate an offset from the stack pointer.
    886   // The incoming offset is relating to the SP at the start of the function,
    887   // but when we access the local it'll be relative to the SP after local
    888   // allocation, so adjust our SP-relative offset by that allocation size.
    889   Offset = -Offset;
    890   Offset += MFI->getLocalFrameSize();
    891   // Assume that we'll have at least some spill slots allocated.
    892   // FIXME: This is a total SWAG number. We should run some statistics
    893   //        and pick a real one.
    894   Offset += 128; // 128 bytes of spill slots
    895 
    896   // If there is a frame pointer, try using it.
    897   // The FP is only available if there is no dynamic realignment. We
    898   // don't know for sure yet whether we'll need that, so we guess based
    899   // on whether there are any local variables that would trigger it.
    900   unsigned StackAlign = TFI->getStackAlignment();
    901   if (TFI->hasFP(MF) &&
    902       !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
    903     if (isFrameOffsetLegal(MI, FPOffset))
    904       return false;
    905   }
    906   // If we can reference via the stack pointer, try that.
    907   // FIXME: This (and the code that resolves the references) can be improved
    908   //        to only disallow SP relative references in the live range of
    909   //        the VLA(s). In practice, it's unclear how much difference that
    910   //        would make, but it may be worth doing.
    911   if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
    912     return false;
    913 
    914   // The offset likely isn't legal, we want to allocate a virtual base register.
    915   return true;
    916 }
    917 
    918 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
    919 /// be a pointer to FrameIdx at the beginning of the basic block.
    920 void ARMBaseRegisterInfo::
    921 materializeFrameBaseRegister(MachineBasicBlock *MBB,
    922                              unsigned BaseReg, int FrameIdx,
    923                              int64_t Offset) const {
    924   ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
    925   unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
    926     (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
    927 
    928   MachineBasicBlock::iterator Ins = MBB->begin();
    929   DebugLoc DL;                  // Defaults to "unknown"
    930   if (Ins != MBB->end())
    931     DL = Ins->getDebugLoc();
    932 
    933   const MCInstrDesc &MCID = TII.get(ADDriOpc);
    934   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
    935   MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this));
    936 
    937   MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
    938     .addFrameIndex(FrameIdx).addImm(Offset));
    939 
    940   if (!AFI->isThumb1OnlyFunction())
    941     AddDefaultCC(MIB);
    942 }
    943 
    944 void
    945 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
    946                                        unsigned BaseReg, int64_t Offset) const {
    947   MachineInstr &MI = *I;
    948   MachineBasicBlock &MBB = *MI.getParent();
    949   MachineFunction &MF = *MBB.getParent();
    950   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
    951   int Off = Offset; // ARM doesn't need the general 64-bit offsets
    952   unsigned i = 0;
    953 
    954   assert(!AFI->isThumb1OnlyFunction() &&
    955          "This resolveFrameIndex does not support Thumb1!");
    956 
    957   while (!MI.getOperand(i).isFI()) {
    958     ++i;
    959     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
    960   }
    961   bool Done = false;
    962   if (!AFI->isThumbFunction())
    963     Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
    964   else {
    965     assert(AFI->isThumb2Function());
    966     Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
    967   }
    968   assert (Done && "Unable to resolve frame index!");
    969   (void)Done;
    970 }
    971 
    972 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
    973                                              int64_t Offset) const {
    974   const MCInstrDesc &Desc = MI->getDesc();
    975   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
    976   unsigned i = 0;
    977 
    978   while (!MI->getOperand(i).isFI()) {
    979     ++i;
    980     assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
    981   }
    982 
    983   // AddrMode4 and AddrMode6 cannot handle any offset.
    984   if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
    985     return Offset == 0;
    986 
    987   unsigned NumBits = 0;
    988   unsigned Scale = 1;
    989   bool isSigned = true;
    990   switch (AddrMode) {
    991   case ARMII::AddrModeT2_i8:
    992   case ARMII::AddrModeT2_i12:
    993     // i8 supports only negative, and i12 supports only positive, so
    994     // based on Offset sign, consider the appropriate instruction
    995     Scale = 1;
    996     if (Offset < 0) {
    997       NumBits = 8;
    998       Offset = -Offset;
    999     } else {
   1000       NumBits = 12;
   1001     }
   1002     break;
   1003   case ARMII::AddrMode5:
   1004     // VFP address mode.
   1005     NumBits = 8;
   1006     Scale = 4;
   1007     break;
   1008   case ARMII::AddrMode_i12:
   1009   case ARMII::AddrMode2:
   1010     NumBits = 12;
   1011     break;
   1012   case ARMII::AddrMode3:
   1013     NumBits = 8;
   1014     break;
   1015   case ARMII::AddrModeT1_s:
   1016     NumBits = 5;
   1017     Scale = 4;
   1018     isSigned = false;
   1019     break;
   1020   default:
   1021     llvm_unreachable("Unsupported addressing mode!");
   1022   }
   1023 
   1024   Offset += getFrameIndexInstrOffset(MI, i);
   1025   // Make sure the offset is encodable for instructions that scale the
   1026   // immediate.
   1027   if ((Offset & (Scale-1)) != 0)
   1028     return false;
   1029 
   1030   if (isSigned && Offset < 0)
   1031     Offset = -Offset;
   1032 
   1033   unsigned Mask = (1 << NumBits) - 1;
   1034   if ((unsigned)Offset <= Mask * Scale)
   1035     return true;
   1036 
   1037   return false;
   1038 }
   1039 
   1040 void
   1041 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   1042                                          int SPAdj, RegScavenger *RS) const {
   1043   unsigned i = 0;
   1044   MachineInstr &MI = *II;
   1045   MachineBasicBlock &MBB = *MI.getParent();
   1046   MachineFunction &MF = *MBB.getParent();
   1047   const ARMFrameLowering *TFI =
   1048     static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
   1049   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
   1050   assert(!AFI->isThumb1OnlyFunction() &&
   1051          "This eliminateFrameIndex does not support Thumb1!");
   1052 
   1053   while (!MI.getOperand(i).isFI()) {
   1054     ++i;
   1055     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
   1056   }
   1057 
   1058   int FrameIndex = MI.getOperand(i).getIndex();
   1059   unsigned FrameReg;
   1060 
   1061   int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
   1062 
   1063   // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
   1064   // call frame setup/destroy instructions have already been eliminated.  That
   1065   // means the stack pointer cannot be used to access the emergency spill slot
   1066   // when !hasReservedCallFrame().
   1067 #ifndef NDEBUG
   1068   if (RS && FrameReg == ARM::SP && FrameIndex == RS->getScavengingFrameIndex()){
   1069     assert(TFI->hasReservedCallFrame(MF) &&
   1070            "Cannot use SP to access the emergency spill slot in "
   1071            "functions without a reserved call frame");
   1072     assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
   1073            "Cannot use SP to access the emergency spill slot in "
   1074            "functions with variable sized frame objects");
   1075   }
   1076 #endif // NDEBUG
   1077 
   1078   // Special handling of dbg_value instructions.
   1079   if (MI.isDebugValue()) {
   1080     MI.getOperand(i).  ChangeToRegister(FrameReg, false /*isDef*/);
   1081     MI.getOperand(i+1).ChangeToImmediate(Offset);
   1082     return;
   1083   }
   1084 
   1085   // Modify MI as necessary to handle as much of 'Offset' as possible
   1086   bool Done = false;
   1087   if (!AFI->isThumbFunction())
   1088     Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
   1089   else {
   1090     assert(AFI->isThumb2Function());
   1091     Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
   1092   }
   1093   if (Done)
   1094     return;
   1095 
   1096   // If we get here, the immediate doesn't fit into the instruction.  We folded
   1097   // as much as possible above, handle the rest, providing a register that is
   1098   // SP+LargeImm.
   1099   assert((Offset ||
   1100           (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
   1101           (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
   1102          "This code isn't needed if offset already handled!");
   1103 
   1104   unsigned ScratchReg = 0;
   1105   int PIdx = MI.findFirstPredOperandIdx();
   1106   ARMCC::CondCodes Pred = (PIdx == -1)
   1107     ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
   1108   unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
   1109   if (Offset == 0)
   1110     // Must be addrmode4/6.
   1111     MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
   1112   else {
   1113     ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
   1114     if (!AFI->isThumbFunction())
   1115       emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
   1116                               Offset, Pred, PredReg, TII);
   1117     else {
   1118       assert(AFI->isThumb2Function());
   1119       emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
   1120                              Offset, Pred, PredReg, TII);
   1121     }
   1122     // Update the original instruction to use the scratch register.
   1123     MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
   1124   }
   1125 }
   1126