1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the ARMMCCodeEmitter class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "mccodeemitter" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "MCTargetDesc/ARMFixupKinds.h" 18 #include "MCTargetDesc/ARMMCExpr.h" 19 #include "MCTargetDesc/ARMMCTargetDesc.h" 20 #include "llvm/MC/MCCodeEmitter.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCExpr.h" 23 #include "llvm/MC/MCInst.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCRegisterInfo.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/ADT/APFloat.h" 28 #include "llvm/ADT/Statistic.h" 29 #include "llvm/Support/raw_ostream.h" 30 31 using namespace llvm; 32 33 STATISTIC(MCNumEmitted, "Number of MC instructions emitted."); 34 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created."); 35 36 namespace { 37 class ARMMCCodeEmitter : public MCCodeEmitter { 38 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT 39 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT 40 const MCInstrInfo &MCII; 41 const MCSubtargetInfo &STI; 42 const MCContext &CTX; 43 44 public: 45 ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti, 46 MCContext &ctx) 47 : MCII(mcii), STI(sti), CTX(ctx) { 48 } 49 50 ~ARMMCCodeEmitter() {} 51 52 bool isThumb() const { 53 // FIXME: Can tablegen auto-generate this? 54 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 55 } 56 bool isThumb2() const { 57 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0; 58 } 59 bool isTargetDarwin() const { 60 Triple TT(STI.getTargetTriple()); 61 Triple::OSType OS = TT.getOS(); 62 return OS == Triple::Darwin || OS == Triple::MacOSX || OS == Triple::IOS; 63 } 64 65 unsigned getMachineSoImmOpValue(unsigned SoImm) const; 66 67 // getBinaryCodeForInstr - TableGen'erated function for getting the 68 // binary encoding for an instruction. 69 uint64_t getBinaryCodeForInstr(const MCInst &MI, 70 SmallVectorImpl<MCFixup> &Fixups) const; 71 72 /// getMachineOpValue - Return binary encoding of operand. If the machine 73 /// operand requires relocation, record the relocation and return zero. 74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 75 SmallVectorImpl<MCFixup> &Fixups) const; 76 77 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of 78 /// the specified operand. This is used for operands with :lower16: and 79 /// :upper16: prefixes. 80 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 81 SmallVectorImpl<MCFixup> &Fixups) const; 82 83 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, 84 unsigned &Reg, unsigned &Imm, 85 SmallVectorImpl<MCFixup> &Fixups) const; 86 87 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate 88 /// BL branch target. 89 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 90 SmallVectorImpl<MCFixup> &Fixups) const; 91 92 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate 93 /// BLX branch target. 94 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 95 SmallVectorImpl<MCFixup> &Fixups) const; 96 97 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. 98 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 99 SmallVectorImpl<MCFixup> &Fixups) const; 100 101 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. 102 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 103 SmallVectorImpl<MCFixup> &Fixups) const; 104 105 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. 106 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 107 SmallVectorImpl<MCFixup> &Fixups) const; 108 109 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate 110 /// branch target. 111 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 112 SmallVectorImpl<MCFixup> &Fixups) const; 113 114 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit 115 /// immediate Thumb2 direct branch target. 116 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 117 SmallVectorImpl<MCFixup> &Fixups) const; 118 119 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate 120 /// branch target. 121 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 122 SmallVectorImpl<MCFixup> &Fixups) const; 123 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 124 SmallVectorImpl<MCFixup> &Fixups) const; 125 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 126 SmallVectorImpl<MCFixup> &Fixups) const; 127 128 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate 129 /// ADR label target. 130 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 131 SmallVectorImpl<MCFixup> &Fixups) const; 132 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 133 SmallVectorImpl<MCFixup> &Fixups) const; 134 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 135 SmallVectorImpl<MCFixup> &Fixups) const; 136 137 138 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' 139 /// operand. 140 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, 141 SmallVectorImpl<MCFixup> &Fixups) const; 142 143 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand. 144 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, 145 SmallVectorImpl<MCFixup> &Fixups)const; 146 147 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2' 148 /// operand. 149 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, 150 SmallVectorImpl<MCFixup> &Fixups) const; 151 152 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2' 153 /// operand. 154 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, 155 SmallVectorImpl<MCFixup> &Fixups) const; 156 157 /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2' 158 /// operand. 159 uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, 160 SmallVectorImpl<MCFixup> &Fixups) const; 161 162 163 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm' 164 /// operand as needed by load/store instructions. 165 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, 166 SmallVectorImpl<MCFixup> &Fixups) const; 167 168 /// getLdStmModeOpValue - Return encoding for load/store multiple mode. 169 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, 170 SmallVectorImpl<MCFixup> &Fixups) const { 171 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); 172 switch (Mode) { 173 default: llvm_unreachable("Unknown addressing sub-mode!"); 174 case ARM_AM::da: return 0; 175 case ARM_AM::ia: return 1; 176 case ARM_AM::db: return 2; 177 case ARM_AM::ib: return 3; 178 } 179 } 180 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 181 /// 182 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { 183 switch (ShOpc) { 184 case ARM_AM::no_shift: 185 case ARM_AM::lsl: return 0; 186 case ARM_AM::lsr: return 1; 187 case ARM_AM::asr: return 2; 188 case ARM_AM::ror: 189 case ARM_AM::rrx: return 3; 190 } 191 llvm_unreachable("Invalid ShiftOpc!"); 192 } 193 194 /// getAddrMode2OpValue - Return encoding for addrmode2 operands. 195 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, 196 SmallVectorImpl<MCFixup> &Fixups) const; 197 198 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands. 199 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, 200 SmallVectorImpl<MCFixup> &Fixups) const; 201 202 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands. 203 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, 204 SmallVectorImpl<MCFixup> &Fixups) const; 205 206 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands. 207 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, 208 SmallVectorImpl<MCFixup> &Fixups) const; 209 210 /// getAddrMode3OpValue - Return encoding for addrmode3 operands. 211 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, 212 SmallVectorImpl<MCFixup> &Fixups) const; 213 214 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12' 215 /// operand. 216 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, 217 SmallVectorImpl<MCFixup> &Fixups) const; 218 219 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands. 220 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, 221 SmallVectorImpl<MCFixup> &Fixups) const; 222 223 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. 224 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, 225 SmallVectorImpl<MCFixup> &Fixups) const; 226 227 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand. 228 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, 229 SmallVectorImpl<MCFixup> &Fixups) const; 230 231 /// getCCOutOpValue - Return encoding of the 's' bit. 232 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op, 233 SmallVectorImpl<MCFixup> &Fixups) const { 234 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or 235 // '1' respectively. 236 return MI.getOperand(Op).getReg() == ARM::CPSR; 237 } 238 239 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value. 240 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op, 241 SmallVectorImpl<MCFixup> &Fixups) const { 242 unsigned SoImm = MI.getOperand(Op).getImm(); 243 int SoImmVal = ARM_AM::getSOImmVal(SoImm); 244 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 245 246 // Encode rotate_imm. 247 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 248 << ARMII::SoRotImmShift; 249 250 // Encode immed_8. 251 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 252 return Binary; 253 } 254 255 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value. 256 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op, 257 SmallVectorImpl<MCFixup> &Fixups) const { 258 unsigned SoImm = MI.getOperand(Op).getImm(); 259 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm); 260 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?"); 261 return Encoded; 262 } 263 264 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, 265 SmallVectorImpl<MCFixup> &Fixups) const; 266 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, 267 SmallVectorImpl<MCFixup> &Fixups) const; 268 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, 269 SmallVectorImpl<MCFixup> &Fixups) const; 270 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum, 271 SmallVectorImpl<MCFixup> &Fixups) const; 272 273 /// getSORegOpValue - Return an encoded so_reg shifted register value. 274 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op, 275 SmallVectorImpl<MCFixup> &Fixups) const; 276 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op, 277 SmallVectorImpl<MCFixup> &Fixups) const; 278 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op, 279 SmallVectorImpl<MCFixup> &Fixups) const; 280 281 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op, 282 SmallVectorImpl<MCFixup> &Fixups) const { 283 return 64 - MI.getOperand(Op).getImm(); 284 } 285 286 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, 287 SmallVectorImpl<MCFixup> &Fixups) const; 288 289 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op, 290 SmallVectorImpl<MCFixup> &Fixups) const; 291 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, 292 SmallVectorImpl<MCFixup> &Fixups) const; 293 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, 294 SmallVectorImpl<MCFixup> &Fixups) const; 295 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, 296 SmallVectorImpl<MCFixup> &Fixups) const; 297 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 298 SmallVectorImpl<MCFixup> &Fixups) const; 299 300 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op, 301 SmallVectorImpl<MCFixup> &Fixups) const; 302 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op, 303 SmallVectorImpl<MCFixup> &Fixups) const; 304 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op, 305 SmallVectorImpl<MCFixup> &Fixups) const; 306 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op, 307 SmallVectorImpl<MCFixup> &Fixups) const; 308 309 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op, 310 SmallVectorImpl<MCFixup> &Fixups) const; 311 312 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI, 313 unsigned EncodedValue) const; 314 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI, 315 unsigned EncodedValue) const; 316 unsigned NEONThumb2DupPostEncoder(const MCInst &MI, 317 unsigned EncodedValue) const; 318 319 unsigned VFPThumb2PostEncoder(const MCInst &MI, 320 unsigned EncodedValue) const; 321 322 void EmitByte(unsigned char C, raw_ostream &OS) const { 323 OS << (char)C; 324 } 325 326 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const { 327 // Output the constant in little endian byte order. 328 for (unsigned i = 0; i != Size; ++i) { 329 EmitByte(Val & 255, OS); 330 Val >>= 8; 331 } 332 } 333 334 void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 335 SmallVectorImpl<MCFixup> &Fixups) const; 336 }; 337 338 } // end anonymous namespace 339 340 MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII, 341 const MCRegisterInfo &MRI, 342 const MCSubtargetInfo &STI, 343 MCContext &Ctx) { 344 return new ARMMCCodeEmitter(MCII, STI, Ctx); 345 } 346 347 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing 348 /// instructions, and rewrite them to their Thumb2 form if we are currently in 349 /// Thumb2 mode. 350 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI, 351 unsigned EncodedValue) const { 352 if (isThumb2()) { 353 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved 354 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are 355 // set to 1111. 356 unsigned Bit24 = EncodedValue & 0x01000000; 357 unsigned Bit28 = Bit24 << 4; 358 EncodedValue &= 0xEFFFFFFF; 359 EncodedValue |= Bit28; 360 EncodedValue |= 0x0F000000; 361 } 362 363 return EncodedValue; 364 } 365 366 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store 367 /// instructions, and rewrite them to their Thumb2 form if we are currently in 368 /// Thumb2 mode. 369 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI, 370 unsigned EncodedValue) const { 371 if (isThumb2()) { 372 EncodedValue &= 0xF0FFFFFF; 373 EncodedValue |= 0x09000000; 374 } 375 376 return EncodedValue; 377 } 378 379 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup 380 /// instructions, and rewrite them to their Thumb2 form if we are currently in 381 /// Thumb2 mode. 382 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI, 383 unsigned EncodedValue) const { 384 if (isThumb2()) { 385 EncodedValue &= 0x00FFFFFF; 386 EncodedValue |= 0xEE000000; 387 } 388 389 return EncodedValue; 390 } 391 392 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite 393 /// them to their Thumb2 form if we are currently in Thumb2 mode. 394 unsigned ARMMCCodeEmitter:: 395 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const { 396 if (isThumb2()) { 397 EncodedValue &= 0x0FFFFFFF; 398 EncodedValue |= 0xE0000000; 399 } 400 return EncodedValue; 401 } 402 403 /// getMachineOpValue - Return binary encoding of operand. If the machine 404 /// operand requires relocation, record the relocation and return zero. 405 unsigned ARMMCCodeEmitter:: 406 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 407 SmallVectorImpl<MCFixup> &Fixups) const { 408 if (MO.isReg()) { 409 unsigned Reg = MO.getReg(); 410 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg); 411 412 // Q registers are encoded as 2x their register number. 413 switch (Reg) { 414 default: 415 return RegNo; 416 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3: 417 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7: 418 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11: 419 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15: 420 return 2 * RegNo; 421 } 422 } else if (MO.isImm()) { 423 return static_cast<unsigned>(MO.getImm()); 424 } else if (MO.isFPImm()) { 425 return static_cast<unsigned>(APFloat(MO.getFPImm()) 426 .bitcastToAPInt().getHiBits(32).getLimitedValue()); 427 } 428 429 llvm_unreachable("Unable to encode MCOperand!"); 430 } 431 432 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. 433 bool ARMMCCodeEmitter:: 434 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, 435 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const { 436 const MCOperand &MO = MI.getOperand(OpIdx); 437 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 438 439 Reg = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 440 441 int32_t SImm = MO1.getImm(); 442 bool isAdd = true; 443 444 // Special value for #-0 445 if (SImm == INT32_MIN) { 446 SImm = 0; 447 isAdd = false; 448 } 449 450 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 451 if (SImm < 0) { 452 SImm = -SImm; 453 isAdd = false; 454 } 455 456 Imm = SImm; 457 return isAdd; 458 } 459 460 /// getBranchTargetOpValue - Helper function to get the branch target operand, 461 /// which is either an immediate or requires a fixup. 462 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 463 unsigned FixupKind, 464 SmallVectorImpl<MCFixup> &Fixups) { 465 const MCOperand &MO = MI.getOperand(OpIdx); 466 467 // If the destination is an immediate, we have nothing to do. 468 if (MO.isImm()) return MO.getImm(); 469 assert(MO.isExpr() && "Unexpected branch target type!"); 470 const MCExpr *Expr = MO.getExpr(); 471 MCFixupKind Kind = MCFixupKind(FixupKind); 472 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc())); 473 474 // All of the information is in the fixup. 475 return 0; 476 } 477 478 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are 479 // determined by negating them and XOR'ing them with bit 23. 480 static int32_t encodeThumbBLOffset(int32_t offset) { 481 offset >>= 1; 482 uint32_t S = (offset & 0x800000) >> 23; 483 uint32_t J1 = (offset & 0x400000) >> 22; 484 uint32_t J2 = (offset & 0x200000) >> 21; 485 J1 = (~J1 & 0x1); 486 J2 = (~J2 & 0x1); 487 J1 ^= S; 488 J2 ^= S; 489 490 offset &= ~0x600000; 491 offset |= J1 << 22; 492 offset |= J2 << 21; 493 494 return offset; 495 } 496 497 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target. 498 uint32_t ARMMCCodeEmitter:: 499 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 500 SmallVectorImpl<MCFixup> &Fixups) const { 501 const MCOperand MO = MI.getOperand(OpIdx); 502 if (MO.isExpr()) 503 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, 504 Fixups); 505 return encodeThumbBLOffset(MO.getImm()); 506 } 507 508 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate 509 /// BLX branch target. 510 uint32_t ARMMCCodeEmitter:: 511 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 512 SmallVectorImpl<MCFixup> &Fixups) const { 513 const MCOperand MO = MI.getOperand(OpIdx); 514 if (MO.isExpr()) 515 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, 516 Fixups); 517 return encodeThumbBLOffset(MO.getImm()); 518 } 519 520 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. 521 uint32_t ARMMCCodeEmitter:: 522 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 523 SmallVectorImpl<MCFixup> &Fixups) const { 524 const MCOperand MO = MI.getOperand(OpIdx); 525 if (MO.isExpr()) 526 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, 527 Fixups); 528 return (MO.getImm() >> 1); 529 } 530 531 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. 532 uint32_t ARMMCCodeEmitter:: 533 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 534 SmallVectorImpl<MCFixup> &Fixups) const { 535 const MCOperand MO = MI.getOperand(OpIdx); 536 if (MO.isExpr()) 537 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, 538 Fixups); 539 return (MO.getImm() >> 1); 540 } 541 542 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. 543 uint32_t ARMMCCodeEmitter:: 544 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 545 SmallVectorImpl<MCFixup> &Fixups) const { 546 const MCOperand MO = MI.getOperand(OpIdx); 547 if (MO.isExpr()) 548 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups); 549 return (MO.getImm() >> 1); 550 } 551 552 /// Return true if this branch has a non-always predication 553 static bool HasConditionalBranch(const MCInst &MI) { 554 int NumOp = MI.getNumOperands(); 555 if (NumOp >= 2) { 556 for (int i = 0; i < NumOp-1; ++i) { 557 const MCOperand &MCOp1 = MI.getOperand(i); 558 const MCOperand &MCOp2 = MI.getOperand(i + 1); 559 if (MCOp1.isImm() && MCOp2.isReg() && 560 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) { 561 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL) 562 return true; 563 } 564 } 565 } 566 return false; 567 } 568 569 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch 570 /// target. 571 uint32_t ARMMCCodeEmitter:: 572 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 573 SmallVectorImpl<MCFixup> &Fixups) const { 574 // FIXME: This really, really shouldn't use TargetMachine. We don't want 575 // coupling between MC and TM anywhere we can help it. 576 if (isThumb2()) 577 return 578 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups); 579 return getARMBranchTargetOpValue(MI, OpIdx, Fixups); 580 } 581 582 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch 583 /// target. 584 uint32_t ARMMCCodeEmitter:: 585 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 586 SmallVectorImpl<MCFixup> &Fixups) const { 587 const MCOperand MO = MI.getOperand(OpIdx); 588 if (MO.isExpr()) { 589 if (HasConditionalBranch(MI)) 590 return ::getBranchTargetOpValue(MI, OpIdx, 591 ARM::fixup_arm_condbranch, Fixups); 592 return ::getBranchTargetOpValue(MI, OpIdx, 593 ARM::fixup_arm_uncondbranch, Fixups); 594 } 595 596 return MO.getImm() >> 2; 597 } 598 599 uint32_t ARMMCCodeEmitter:: 600 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 601 SmallVectorImpl<MCFixup> &Fixups) const { 602 const MCOperand MO = MI.getOperand(OpIdx); 603 if (MO.isExpr()) { 604 if (HasConditionalBranch(MI)) 605 return ::getBranchTargetOpValue(MI, OpIdx, 606 ARM::fixup_arm_condbl, Fixups); 607 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups); 608 } 609 610 return MO.getImm() >> 2; 611 } 612 613 uint32_t ARMMCCodeEmitter:: 614 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 615 SmallVectorImpl<MCFixup> &Fixups) const { 616 const MCOperand MO = MI.getOperand(OpIdx); 617 if (MO.isExpr()) 618 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups); 619 620 return MO.getImm() >> 1; 621 } 622 623 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit 624 /// immediate branch target. 625 uint32_t ARMMCCodeEmitter:: 626 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 627 SmallVectorImpl<MCFixup> &Fixups) const { 628 unsigned Val = 629 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups); 630 bool I = (Val & 0x800000); 631 bool J1 = (Val & 0x400000); 632 bool J2 = (Val & 0x200000); 633 if (I ^ J1) 634 Val &= ~0x400000; 635 else 636 Val |= 0x400000; 637 638 if (I ^ J2) 639 Val &= ~0x200000; 640 else 641 Val |= 0x200000; 642 643 return Val; 644 } 645 646 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate 647 /// ADR label target. 648 uint32_t ARMMCCodeEmitter:: 649 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 650 SmallVectorImpl<MCFixup> &Fixups) const { 651 const MCOperand MO = MI.getOperand(OpIdx); 652 if (MO.isExpr()) 653 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12, 654 Fixups); 655 int32_t offset = MO.getImm(); 656 uint32_t Val = 0x2000; 657 658 if (offset == INT32_MIN) { 659 Val = 0x1000; 660 offset = 0; 661 } else if (offset < 0) { 662 Val = 0x1000; 663 offset *= -1; 664 } 665 666 int SoImmVal = ARM_AM::getSOImmVal(offset); 667 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 668 669 Val |= SoImmVal; 670 return Val; 671 } 672 673 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label 674 /// target. 675 uint32_t ARMMCCodeEmitter:: 676 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 677 SmallVectorImpl<MCFixup> &Fixups) const { 678 const MCOperand MO = MI.getOperand(OpIdx); 679 if (MO.isExpr()) 680 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12, 681 Fixups); 682 int32_t Val = MO.getImm(); 683 if (Val == INT32_MIN) 684 Val = 0x1000; 685 else if (Val < 0) { 686 Val *= -1; 687 Val |= 0x1000; 688 } 689 return Val; 690 } 691 692 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label 693 /// target. 694 uint32_t ARMMCCodeEmitter:: 695 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 696 SmallVectorImpl<MCFixup> &Fixups) const { 697 const MCOperand MO = MI.getOperand(OpIdx); 698 if (MO.isExpr()) 699 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10, 700 Fixups); 701 return MO.getImm(); 702 } 703 704 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg' 705 /// operand. 706 uint32_t ARMMCCodeEmitter:: 707 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, 708 SmallVectorImpl<MCFixup> &) const { 709 // [Rn, Rm] 710 // {5-3} = Rm 711 // {2-0} = Rn 712 const MCOperand &MO1 = MI.getOperand(OpIdx); 713 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); 714 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO1.getReg()); 715 unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO2.getReg()); 716 return (Rm << 3) | Rn; 717 } 718 719 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand. 720 uint32_t ARMMCCodeEmitter:: 721 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, 722 SmallVectorImpl<MCFixup> &Fixups) const { 723 // {17-13} = reg 724 // {12} = (U)nsigned (add == '1', sub == '0') 725 // {11-0} = imm12 726 unsigned Reg, Imm12; 727 bool isAdd = true; 728 // If The first operand isn't a register, we have a label reference. 729 const MCOperand &MO = MI.getOperand(OpIdx); 730 if (!MO.isReg()) { 731 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC. 732 Imm12 = 0; 733 isAdd = false ; // 'U' bit is set as part of the fixup. 734 735 if (MO.isExpr()) { 736 const MCExpr *Expr = MO.getExpr(); 737 738 MCFixupKind Kind; 739 if (isThumb2()) 740 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12); 741 else 742 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12); 743 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc())); 744 745 ++MCNumCPRelocations; 746 } else { 747 Reg = ARM::PC; 748 int32_t Offset = MO.getImm(); 749 // FIXME: Handle #-0. 750 if (Offset < 0) { 751 Offset *= -1; 752 isAdd = false; 753 } 754 Imm12 = Offset; 755 } 756 } else 757 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups); 758 759 uint32_t Binary = Imm12 & 0xfff; 760 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 761 if (isAdd) 762 Binary |= (1 << 12); 763 Binary |= (Reg << 13); 764 return Binary; 765 } 766 767 /// getT2Imm8s4OpValue - Return encoding info for 768 /// '+/- imm8<<2' operand. 769 uint32_t ARMMCCodeEmitter:: 770 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, 771 SmallVectorImpl<MCFixup> &Fixups) const { 772 // FIXME: The immediate operand should have already been encoded like this 773 // before ever getting here. The encoder method should just need to combine 774 // the MI operands for the register and the offset into a single 775 // representation for the complex operand in the .td file. This isn't just 776 // style, unfortunately. As-is, we can't represent the distinct encoding 777 // for #-0. 778 779 // {8} = (U)nsigned (add == '1', sub == '0') 780 // {7-0} = imm8 781 int32_t Imm8 = MI.getOperand(OpIdx).getImm(); 782 bool isAdd = Imm8 >= 0; 783 784 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 785 if (Imm8 < 0) 786 Imm8 = -(uint32_t)Imm8; 787 788 // Scaled by 4. 789 Imm8 /= 4; 790 791 uint32_t Binary = Imm8 & 0xff; 792 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 793 if (isAdd) 794 Binary |= (1 << 8); 795 return Binary; 796 } 797 798 /// getT2AddrModeImm8s4OpValue - Return encoding info for 799 /// 'reg +/- imm8<<2' operand. 800 uint32_t ARMMCCodeEmitter:: 801 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, 802 SmallVectorImpl<MCFixup> &Fixups) const { 803 // {12-9} = reg 804 // {8} = (U)nsigned (add == '1', sub == '0') 805 // {7-0} = imm8 806 unsigned Reg, Imm8; 807 bool isAdd = true; 808 // If The first operand isn't a register, we have a label reference. 809 const MCOperand &MO = MI.getOperand(OpIdx); 810 if (!MO.isReg()) { 811 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC. 812 Imm8 = 0; 813 isAdd = false ; // 'U' bit is set as part of the fixup. 814 815 assert(MO.isExpr() && "Unexpected machine operand type!"); 816 const MCExpr *Expr = MO.getExpr(); 817 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); 818 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc())); 819 820 ++MCNumCPRelocations; 821 } else 822 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups); 823 824 // FIXME: The immediate operand should have already been encoded like this 825 // before ever getting here. The encoder method should just need to combine 826 // the MI operands for the register and the offset into a single 827 // representation for the complex operand in the .td file. This isn't just 828 // style, unfortunately. As-is, we can't represent the distinct encoding 829 // for #-0. 830 uint32_t Binary = (Imm8 >> 2) & 0xff; 831 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 832 if (isAdd) 833 Binary |= (1 << 8); 834 Binary |= (Reg << 9); 835 return Binary; 836 } 837 838 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 839 /// 'reg + imm8<<2' operand. 840 uint32_t ARMMCCodeEmitter:: 841 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, 842 SmallVectorImpl<MCFixup> &Fixups) const { 843 // {11-8} = reg 844 // {7-0} = imm8 845 const MCOperand &MO = MI.getOperand(OpIdx); 846 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 847 unsigned Reg = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 848 unsigned Imm8 = MO1.getImm(); 849 return (Reg << 8) | Imm8; 850 } 851 852 // FIXME: This routine assumes that a binary 853 // expression will always result in a PCRel expression 854 // In reality, its only true if one or more subexpressions 855 // is itself a PCRel (i.e. "." in asm or some other pcrel construct) 856 // but this is good enough for now. 857 static bool EvaluateAsPCRel(const MCExpr *Expr) { 858 switch (Expr->getKind()) { 859 default: llvm_unreachable("Unexpected expression type"); 860 case MCExpr::SymbolRef: return false; 861 case MCExpr::Binary: return true; 862 } 863 } 864 865 uint32_t 866 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 867 SmallVectorImpl<MCFixup> &Fixups) const { 868 // {20-16} = imm{15-12} 869 // {11-0} = imm{11-0} 870 const MCOperand &MO = MI.getOperand(OpIdx); 871 if (MO.isImm()) 872 // Hi / lo 16 bits already extracted during earlier passes. 873 return static_cast<unsigned>(MO.getImm()); 874 875 // Handle :upper16: and :lower16: assembly prefixes. 876 const MCExpr *E = MO.getExpr(); 877 MCFixupKind Kind; 878 if (E->getKind() == MCExpr::Target) { 879 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E); 880 E = ARM16Expr->getSubExpr(); 881 882 switch (ARM16Expr->getKind()) { 883 default: llvm_unreachable("Unsupported ARMFixup"); 884 case ARMMCExpr::VK_ARM_HI16: 885 if (!isTargetDarwin() && EvaluateAsPCRel(E)) 886 Kind = MCFixupKind(isThumb2() 887 ? ARM::fixup_t2_movt_hi16_pcrel 888 : ARM::fixup_arm_movt_hi16_pcrel); 889 else 890 Kind = MCFixupKind(isThumb2() 891 ? ARM::fixup_t2_movt_hi16 892 : ARM::fixup_arm_movt_hi16); 893 break; 894 case ARMMCExpr::VK_ARM_LO16: 895 if (!isTargetDarwin() && EvaluateAsPCRel(E)) 896 Kind = MCFixupKind(isThumb2() 897 ? ARM::fixup_t2_movw_lo16_pcrel 898 : ARM::fixup_arm_movw_lo16_pcrel); 899 else 900 Kind = MCFixupKind(isThumb2() 901 ? ARM::fixup_t2_movw_lo16 902 : ARM::fixup_arm_movw_lo16); 903 break; 904 } 905 Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc())); 906 return 0; 907 } 908 // If the expression doesn't have :upper16: or :lower16: on it, 909 // it's just a plain immediate expression, and those evaluate to 910 // the lower 16 bits of the expression regardless of whether 911 // we have a movt or a movw. 912 if (!isTargetDarwin() && EvaluateAsPCRel(E)) 913 Kind = MCFixupKind(isThumb2() 914 ? ARM::fixup_t2_movw_lo16_pcrel 915 : ARM::fixup_arm_movw_lo16_pcrel); 916 else 917 Kind = MCFixupKind(isThumb2() 918 ? ARM::fixup_t2_movw_lo16 919 : ARM::fixup_arm_movw_lo16); 920 Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc())); 921 return 0; 922 } 923 924 uint32_t ARMMCCodeEmitter:: 925 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, 926 SmallVectorImpl<MCFixup> &Fixups) const { 927 const MCOperand &MO = MI.getOperand(OpIdx); 928 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 929 const MCOperand &MO2 = MI.getOperand(OpIdx+2); 930 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 931 unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO1.getReg()); 932 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); 933 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; 934 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); 935 unsigned SBits = getShiftOp(ShOp); 936 937 // {16-13} = Rn 938 // {12} = isAdd 939 // {11-0} = shifter 940 // {3-0} = Rm 941 // {4} = 0 942 // {6-5} = type 943 // {11-7} = imm 944 uint32_t Binary = Rm; 945 Binary |= Rn << 13; 946 Binary |= SBits << 5; 947 Binary |= ShImm << 7; 948 if (isAdd) 949 Binary |= 1 << 12; 950 return Binary; 951 } 952 953 uint32_t ARMMCCodeEmitter:: 954 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, 955 SmallVectorImpl<MCFixup> &Fixups) const { 956 // {17-14} Rn 957 // {13} 1 == imm12, 0 == Rm 958 // {12} isAdd 959 // {11-0} imm12/Rm 960 const MCOperand &MO = MI.getOperand(OpIdx); 961 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 962 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups); 963 Binary |= Rn << 14; 964 return Binary; 965 } 966 967 uint32_t ARMMCCodeEmitter:: 968 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, 969 SmallVectorImpl<MCFixup> &Fixups) const { 970 // {13} 1 == imm12, 0 == Rm 971 // {12} isAdd 972 // {11-0} imm12/Rm 973 const MCOperand &MO = MI.getOperand(OpIdx); 974 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 975 unsigned Imm = MO1.getImm(); 976 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add; 977 bool isReg = MO.getReg() != 0; 978 uint32_t Binary = ARM_AM::getAM2Offset(Imm); 979 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12 980 if (isReg) { 981 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); 982 Binary <<= 7; // Shift amount is bits [11:7] 983 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] 984 Binary |= CTX.getRegisterInfo().getEncodingValue(MO.getReg()); // Rm is bits [3:0] 985 } 986 return Binary | (isAdd << 12) | (isReg << 13); 987 } 988 989 uint32_t ARMMCCodeEmitter:: 990 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, 991 SmallVectorImpl<MCFixup> &Fixups) const { 992 // {4} isAdd 993 // {3-0} Rm 994 const MCOperand &MO = MI.getOperand(OpIdx); 995 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 996 bool isAdd = MO1.getImm() != 0; 997 return CTX.getRegisterInfo().getEncodingValue(MO.getReg()) | (isAdd << 4); 998 } 999 1000 uint32_t ARMMCCodeEmitter:: 1001 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, 1002 SmallVectorImpl<MCFixup> &Fixups) const { 1003 // {9} 1 == imm8, 0 == Rm 1004 // {8} isAdd 1005 // {7-4} imm7_4/zero 1006 // {3-0} imm3_0/Rm 1007 const MCOperand &MO = MI.getOperand(OpIdx); 1008 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1009 unsigned Imm = MO1.getImm(); 1010 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 1011 bool isImm = MO.getReg() == 0; 1012 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 1013 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 1014 if (!isImm) 1015 Imm8 = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 1016 return Imm8 | (isAdd << 8) | (isImm << 9); 1017 } 1018 1019 uint32_t ARMMCCodeEmitter:: 1020 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, 1021 SmallVectorImpl<MCFixup> &Fixups) const { 1022 // {13} 1 == imm8, 0 == Rm 1023 // {12-9} Rn 1024 // {8} isAdd 1025 // {7-4} imm7_4/zero 1026 // {3-0} imm3_0/Rm 1027 const MCOperand &MO = MI.getOperand(OpIdx); 1028 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1029 const MCOperand &MO2 = MI.getOperand(OpIdx+2); 1030 1031 // If The first operand isn't a register, we have a label reference. 1032 if (!MO.isReg()) { 1033 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC. 1034 1035 assert(MO.isExpr() && "Unexpected machine operand type!"); 1036 const MCExpr *Expr = MO.getExpr(); 1037 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled); 1038 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc())); 1039 1040 ++MCNumCPRelocations; 1041 return (Rn << 9) | (1 << 13); 1042 } 1043 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 1044 unsigned Imm = MO2.getImm(); 1045 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 1046 bool isImm = MO1.getReg() == 0; 1047 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 1048 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 1049 if (!isImm) 1050 Imm8 = CTX.getRegisterInfo().getEncodingValue(MO1.getReg()); 1051 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13); 1052 } 1053 1054 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands. 1055 uint32_t ARMMCCodeEmitter:: 1056 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, 1057 SmallVectorImpl<MCFixup> &Fixups) const { 1058 // [SP, #imm] 1059 // {7-0} = imm8 1060 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1061 assert(MI.getOperand(OpIdx).getReg() == ARM::SP && 1062 "Unexpected base register!"); 1063 1064 // The immediate is already shifted for the implicit zeroes, so no change 1065 // here. 1066 return MO1.getImm() & 0xff; 1067 } 1068 1069 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands. 1070 uint32_t ARMMCCodeEmitter:: 1071 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, 1072 SmallVectorImpl<MCFixup> &Fixups) const { 1073 // [Rn, #imm] 1074 // {7-3} = imm5 1075 // {2-0} = Rn 1076 const MCOperand &MO = MI.getOperand(OpIdx); 1077 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1078 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 1079 unsigned Imm5 = MO1.getImm(); 1080 return ((Imm5 & 0x1f) << 3) | Rn; 1081 } 1082 1083 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. 1084 uint32_t ARMMCCodeEmitter:: 1085 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, 1086 SmallVectorImpl<MCFixup> &Fixups) const { 1087 const MCOperand MO = MI.getOperand(OpIdx); 1088 if (MO.isExpr()) 1089 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups); 1090 return (MO.getImm() >> 2); 1091 } 1092 1093 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand. 1094 uint32_t ARMMCCodeEmitter:: 1095 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, 1096 SmallVectorImpl<MCFixup> &Fixups) const { 1097 // {12-9} = reg 1098 // {8} = (U)nsigned (add == '1', sub == '0') 1099 // {7-0} = imm8 1100 unsigned Reg, Imm8; 1101 bool isAdd; 1102 // If The first operand isn't a register, we have a label reference. 1103 const MCOperand &MO = MI.getOperand(OpIdx); 1104 if (!MO.isReg()) { 1105 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC. 1106 Imm8 = 0; 1107 isAdd = false; // 'U' bit is handled as part of the fixup. 1108 1109 assert(MO.isExpr() && "Unexpected machine operand type!"); 1110 const MCExpr *Expr = MO.getExpr(); 1111 MCFixupKind Kind; 1112 if (isThumb2()) 1113 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); 1114 else 1115 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10); 1116 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc())); 1117 1118 ++MCNumCPRelocations; 1119 } else { 1120 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups); 1121 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add; 1122 } 1123 1124 uint32_t Binary = ARM_AM::getAM5Offset(Imm8); 1125 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1126 if (isAdd) 1127 Binary |= (1 << 8); 1128 Binary |= (Reg << 9); 1129 return Binary; 1130 } 1131 1132 unsigned ARMMCCodeEmitter:: 1133 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx, 1134 SmallVectorImpl<MCFixup> &Fixups) const { 1135 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be 1136 // shifted. The second is Rs, the amount to shift by, and the third specifies 1137 // the type of the shift. 1138 // 1139 // {3-0} = Rm. 1140 // {4} = 1 1141 // {6-5} = type 1142 // {11-8} = Rs 1143 // {7} = 0 1144 1145 const MCOperand &MO = MI.getOperand(OpIdx); 1146 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1147 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); 1148 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 1149 1150 // Encode Rm. 1151 unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 1152 1153 // Encode the shift opcode. 1154 unsigned SBits = 0; 1155 unsigned Rs = MO1.getReg(); 1156 if (Rs) { 1157 // Set shift operand (bit[7:4]). 1158 // LSL - 0001 1159 // LSR - 0011 1160 // ASR - 0101 1161 // ROR - 0111 1162 switch (SOpc) { 1163 default: llvm_unreachable("Unknown shift opc!"); 1164 case ARM_AM::lsl: SBits = 0x1; break; 1165 case ARM_AM::lsr: SBits = 0x3; break; 1166 case ARM_AM::asr: SBits = 0x5; break; 1167 case ARM_AM::ror: SBits = 0x7; break; 1168 } 1169 } 1170 1171 Binary |= SBits << 4; 1172 1173 // Encode the shift operation Rs. 1174 // Encode Rs bit[11:8]. 1175 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 1176 return Binary | (CTX.getRegisterInfo().getEncodingValue(Rs) << ARMII::RegRsShift); 1177 } 1178 1179 unsigned ARMMCCodeEmitter:: 1180 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, 1181 SmallVectorImpl<MCFixup> &Fixups) const { 1182 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be 1183 // shifted. The second is the amount to shift by. 1184 // 1185 // {3-0} = Rm. 1186 // {4} = 0 1187 // {6-5} = type 1188 // {11-7} = imm 1189 1190 const MCOperand &MO = MI.getOperand(OpIdx); 1191 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1192 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); 1193 1194 // Encode Rm. 1195 unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 1196 1197 // Encode the shift opcode. 1198 unsigned SBits = 0; 1199 1200 // Set shift operand (bit[6:4]). 1201 // LSL - 000 1202 // LSR - 010 1203 // ASR - 100 1204 // ROR - 110 1205 // RRX - 110 and bit[11:8] clear. 1206 switch (SOpc) { 1207 default: llvm_unreachable("Unknown shift opc!"); 1208 case ARM_AM::lsl: SBits = 0x0; break; 1209 case ARM_AM::lsr: SBits = 0x2; break; 1210 case ARM_AM::asr: SBits = 0x4; break; 1211 case ARM_AM::ror: SBits = 0x6; break; 1212 case ARM_AM::rrx: 1213 Binary |= 0x60; 1214 return Binary; 1215 } 1216 1217 // Encode shift_imm bit[11:7]. 1218 Binary |= SBits << 4; 1219 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm()); 1220 assert(Offset < 32 && "Offset must be in range 0-31!"); 1221 return Binary | (Offset << 7); 1222 } 1223 1224 1225 unsigned ARMMCCodeEmitter:: 1226 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, 1227 SmallVectorImpl<MCFixup> &Fixups) const { 1228 const MCOperand &MO1 = MI.getOperand(OpNum); 1229 const MCOperand &MO2 = MI.getOperand(OpNum+1); 1230 const MCOperand &MO3 = MI.getOperand(OpNum+2); 1231 1232 // Encoded as [Rn, Rm, imm]. 1233 // FIXME: Needs fixup support. 1234 unsigned Value = CTX.getRegisterInfo().getEncodingValue(MO1.getReg()); 1235 Value <<= 4; 1236 Value |= CTX.getRegisterInfo().getEncodingValue(MO2.getReg()); 1237 Value <<= 2; 1238 Value |= MO3.getImm(); 1239 1240 return Value; 1241 } 1242 1243 unsigned ARMMCCodeEmitter:: 1244 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, 1245 SmallVectorImpl<MCFixup> &Fixups) const { 1246 const MCOperand &MO1 = MI.getOperand(OpNum); 1247 const MCOperand &MO2 = MI.getOperand(OpNum+1); 1248 1249 // FIXME: Needs fixup support. 1250 unsigned Value = CTX.getRegisterInfo().getEncodingValue(MO1.getReg()); 1251 1252 // Even though the immediate is 8 bits long, we need 9 bits in order 1253 // to represent the (inverse of the) sign bit. 1254 Value <<= 9; 1255 int32_t tmp = (int32_t)MO2.getImm(); 1256 if (tmp < 0) 1257 tmp = abs(tmp); 1258 else 1259 Value |= 256; // Set the ADD bit 1260 Value |= tmp & 255; 1261 return Value; 1262 } 1263 1264 unsigned ARMMCCodeEmitter:: 1265 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, 1266 SmallVectorImpl<MCFixup> &Fixups) const { 1267 const MCOperand &MO1 = MI.getOperand(OpNum); 1268 1269 // FIXME: Needs fixup support. 1270 unsigned Value = 0; 1271 int32_t tmp = (int32_t)MO1.getImm(); 1272 if (tmp < 0) 1273 tmp = abs(tmp); 1274 else 1275 Value |= 256; // Set the ADD bit 1276 Value |= tmp & 255; 1277 return Value; 1278 } 1279 1280 unsigned ARMMCCodeEmitter:: 1281 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum, 1282 SmallVectorImpl<MCFixup> &Fixups) const { 1283 const MCOperand &MO1 = MI.getOperand(OpNum); 1284 1285 // FIXME: Needs fixup support. 1286 unsigned Value = 0; 1287 int32_t tmp = (int32_t)MO1.getImm(); 1288 if (tmp < 0) 1289 tmp = abs(tmp); 1290 else 1291 Value |= 4096; // Set the ADD bit 1292 Value |= tmp & 4095; 1293 return Value; 1294 } 1295 1296 unsigned ARMMCCodeEmitter:: 1297 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx, 1298 SmallVectorImpl<MCFixup> &Fixups) const { 1299 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be 1300 // shifted. The second is the amount to shift by. 1301 // 1302 // {3-0} = Rm. 1303 // {4} = 0 1304 // {6-5} = type 1305 // {11-7} = imm 1306 1307 const MCOperand &MO = MI.getOperand(OpIdx); 1308 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1309 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); 1310 1311 // Encode Rm. 1312 unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 1313 1314 // Encode the shift opcode. 1315 unsigned SBits = 0; 1316 // Set shift operand (bit[6:4]). 1317 // LSL - 000 1318 // LSR - 010 1319 // ASR - 100 1320 // ROR - 110 1321 switch (SOpc) { 1322 default: llvm_unreachable("Unknown shift opc!"); 1323 case ARM_AM::lsl: SBits = 0x0; break; 1324 case ARM_AM::lsr: SBits = 0x2; break; 1325 case ARM_AM::asr: SBits = 0x4; break; 1326 case ARM_AM::rrx: // FALLTHROUGH 1327 case ARM_AM::ror: SBits = 0x6; break; 1328 } 1329 1330 Binary |= SBits << 4; 1331 if (SOpc == ARM_AM::rrx) 1332 return Binary; 1333 1334 // Encode shift_imm bit[11:7]. 1335 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7; 1336 } 1337 1338 unsigned ARMMCCodeEmitter:: 1339 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, 1340 SmallVectorImpl<MCFixup> &Fixups) const { 1341 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the 1342 // msb of the mask. 1343 const MCOperand &MO = MI.getOperand(Op); 1344 uint32_t v = ~MO.getImm(); 1345 uint32_t lsb = CountTrailingZeros_32(v); 1346 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1; 1347 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!"); 1348 return lsb | (msb << 5); 1349 } 1350 1351 unsigned ARMMCCodeEmitter:: 1352 getRegisterListOpValue(const MCInst &MI, unsigned Op, 1353 SmallVectorImpl<MCFixup> &Fixups) const { 1354 // VLDM/VSTM: 1355 // {12-8} = Vd 1356 // {7-0} = Number of registers 1357 // 1358 // LDM/STM: 1359 // {15-0} = Bitfield of GPRs. 1360 unsigned Reg = MI.getOperand(Op).getReg(); 1361 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg); 1362 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg); 1363 1364 unsigned Binary = 0; 1365 1366 if (SPRRegs || DPRRegs) { 1367 // VLDM/VSTM 1368 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg); 1369 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff; 1370 Binary |= (RegNo & 0x1f) << 8; 1371 if (SPRRegs) 1372 Binary |= NumRegs; 1373 else 1374 Binary |= NumRegs * 2; 1375 } else { 1376 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) { 1377 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(MI.getOperand(I).getReg()); 1378 Binary |= 1 << RegNo; 1379 } 1380 } 1381 1382 return Binary; 1383 } 1384 1385 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along 1386 /// with the alignment operand. 1387 unsigned ARMMCCodeEmitter:: 1388 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, 1389 SmallVectorImpl<MCFixup> &Fixups) const { 1390 const MCOperand &Reg = MI.getOperand(Op); 1391 const MCOperand &Imm = MI.getOperand(Op + 1); 1392 1393 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg()); 1394 unsigned Align = 0; 1395 1396 switch (Imm.getImm()) { 1397 default: break; 1398 case 2: 1399 case 4: 1400 case 8: Align = 0x01; break; 1401 case 16: Align = 0x02; break; 1402 case 32: Align = 0x03; break; 1403 } 1404 1405 return RegNo | (Align << 4); 1406 } 1407 1408 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number 1409 /// along with the alignment operand for use in VST1 and VLD1 with size 32. 1410 unsigned ARMMCCodeEmitter:: 1411 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, 1412 SmallVectorImpl<MCFixup> &Fixups) const { 1413 const MCOperand &Reg = MI.getOperand(Op); 1414 const MCOperand &Imm = MI.getOperand(Op + 1); 1415 1416 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg()); 1417 unsigned Align = 0; 1418 1419 switch (Imm.getImm()) { 1420 default: break; 1421 case 8: 1422 case 16: 1423 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes. 1424 case 2: Align = 0x00; break; 1425 case 4: Align = 0x03; break; 1426 } 1427 1428 return RegNo | (Align << 4); 1429 } 1430 1431 1432 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and 1433 /// alignment operand for use in VLD-dup instructions. This is the same as 1434 /// getAddrMode6AddressOpValue except for the alignment encoding, which is 1435 /// different for VLD4-dup. 1436 unsigned ARMMCCodeEmitter:: 1437 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, 1438 SmallVectorImpl<MCFixup> &Fixups) const { 1439 const MCOperand &Reg = MI.getOperand(Op); 1440 const MCOperand &Imm = MI.getOperand(Op + 1); 1441 1442 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg()); 1443 unsigned Align = 0; 1444 1445 switch (Imm.getImm()) { 1446 default: break; 1447 case 2: 1448 case 4: 1449 case 8: Align = 0x01; break; 1450 case 16: Align = 0x03; break; 1451 } 1452 1453 return RegNo | (Align << 4); 1454 } 1455 1456 unsigned ARMMCCodeEmitter:: 1457 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 1458 SmallVectorImpl<MCFixup> &Fixups) const { 1459 const MCOperand &MO = MI.getOperand(Op); 1460 if (MO.getReg() == 0) return 0x0D; 1461 return CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 1462 } 1463 1464 unsigned ARMMCCodeEmitter:: 1465 getShiftRight8Imm(const MCInst &MI, unsigned Op, 1466 SmallVectorImpl<MCFixup> &Fixups) const { 1467 return 8 - MI.getOperand(Op).getImm(); 1468 } 1469 1470 unsigned ARMMCCodeEmitter:: 1471 getShiftRight16Imm(const MCInst &MI, unsigned Op, 1472 SmallVectorImpl<MCFixup> &Fixups) const { 1473 return 16 - MI.getOperand(Op).getImm(); 1474 } 1475 1476 unsigned ARMMCCodeEmitter:: 1477 getShiftRight32Imm(const MCInst &MI, unsigned Op, 1478 SmallVectorImpl<MCFixup> &Fixups) const { 1479 return 32 - MI.getOperand(Op).getImm(); 1480 } 1481 1482 unsigned ARMMCCodeEmitter:: 1483 getShiftRight64Imm(const MCInst &MI, unsigned Op, 1484 SmallVectorImpl<MCFixup> &Fixups) const { 1485 return 64 - MI.getOperand(Op).getImm(); 1486 } 1487 1488 void ARMMCCodeEmitter:: 1489 EncodeInstruction(const MCInst &MI, raw_ostream &OS, 1490 SmallVectorImpl<MCFixup> &Fixups) const { 1491 // Pseudo instructions don't get encoded. 1492 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 1493 uint64_t TSFlags = Desc.TSFlags; 1494 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo) 1495 return; 1496 1497 int Size; 1498 if (Desc.getSize() == 2 || Desc.getSize() == 4) 1499 Size = Desc.getSize(); 1500 else 1501 llvm_unreachable("Unexpected instruction size!"); 1502 1503 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups); 1504 // Thumb 32-bit wide instructions need to emit the high order halfword 1505 // first. 1506 if (isThumb() && Size == 4) { 1507 EmitConstant(Binary >> 16, 2, OS); 1508 EmitConstant(Binary & 0xffff, 2, OS); 1509 } else 1510 EmitConstant(Binary, Size, OS); 1511 ++MCNumEmitted; // Keep track of the # of mi's emitted. 1512 } 1513 1514 #include "ARMGenMCCodeEmitter.inc" 1515