1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides X86 specific target descriptions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86MCTargetDesc.h" 15 #include "X86MCAsmInfo.h" 16 #include "InstPrinter/X86ATTInstPrinter.h" 17 #include "InstPrinter/X86IntelInstPrinter.h" 18 #include "llvm/MC/MachineLocation.h" 19 #include "llvm/MC/MCCodeGenInfo.h" 20 #include "llvm/MC/MCInstrAnalysis.h" 21 #include "llvm/MC/MCInstrInfo.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCStreamer.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/ADT/Triple.h" 26 #include "llvm/Support/Host.h" 27 #include "llvm/Support/ErrorHandling.h" 28 #include "llvm/Support/TargetRegistry.h" 29 30 #define GET_REGINFO_MC_DESC 31 #include "X86GenRegisterInfo.inc" 32 33 #define GET_INSTRINFO_MC_DESC 34 #include "X86GenInstrInfo.inc" 35 36 #define GET_SUBTARGETINFO_MC_DESC 37 #include "X86GenSubtargetInfo.inc" 38 39 #if _MSC_VER 40 #include <intrin.h> 41 #endif 42 43 using namespace llvm; 44 45 46 std::string X86_MC::ParseX86Triple(StringRef TT) { 47 Triple TheTriple(TT); 48 std::string FS; 49 if (TheTriple.getArch() == Triple::x86_64) 50 FS = "+64bit-mode"; 51 else 52 FS = "-64bit-mode"; 53 return FS; 54 } 55 56 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the 57 /// specified arguments. If we can't run cpuid on the host, return true. 58 bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, 59 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) { 60 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) 61 #if defined(__GNUC__) 62 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. 63 asm ("movq\t%%rbx, %%rsi\n\t" 64 "cpuid\n\t" 65 "xchgq\t%%rbx, %%rsi\n\t" 66 : "=a" (*rEAX), 67 "=S" (*rEBX), 68 "=c" (*rECX), 69 "=d" (*rEDX) 70 : "a" (value)); 71 return false; 72 #elif defined(_MSC_VER) 73 int registers[4]; 74 __cpuid(registers, value); 75 *rEAX = registers[0]; 76 *rEBX = registers[1]; 77 *rECX = registers[2]; 78 *rEDX = registers[3]; 79 return false; 80 #else 81 return true; 82 #endif 83 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) 84 #if defined(__GNUC__) 85 asm ("movl\t%%ebx, %%esi\n\t" 86 "cpuid\n\t" 87 "xchgl\t%%ebx, %%esi\n\t" 88 : "=a" (*rEAX), 89 "=S" (*rEBX), 90 "=c" (*rECX), 91 "=d" (*rEDX) 92 : "a" (value)); 93 return false; 94 #elif defined(_MSC_VER) 95 __asm { 96 mov eax,value 97 cpuid 98 mov esi,rEAX 99 mov dword ptr [esi],eax 100 mov esi,rEBX 101 mov dword ptr [esi],ebx 102 mov esi,rECX 103 mov dword ptr [esi],ecx 104 mov esi,rEDX 105 mov dword ptr [esi],edx 106 } 107 return false; 108 #else 109 return true; 110 #endif 111 #else 112 return true; 113 #endif 114 } 115 116 /// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the 117 /// 4 values in the specified arguments. If we can't run cpuid on the host, 118 /// return true. 119 bool X86_MC::GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX, 120 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) { 121 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) 122 #if defined(__GNUC__) 123 // gcc desn't know cpuid would clobber ebx/rbx. Preseve it manually. 124 asm ("movq\t%%rbx, %%rsi\n\t" 125 "cpuid\n\t" 126 "xchgq\t%%rbx, %%rsi\n\t" 127 : "=a" (*rEAX), 128 "=S" (*rEBX), 129 "=c" (*rECX), 130 "=d" (*rEDX) 131 : "a" (value), 132 "c" (subleaf)); 133 return false; 134 #elif defined(_MSC_VER) 135 // __cpuidex was added in MSVC++ 9.0 SP1 136 #if (_MSC_VER > 1500) || (_MSC_VER == 1500 && _MSC_FULL_VER >= 150030729) 137 int registers[4]; 138 __cpuidex(registers, value, subleaf); 139 *rEAX = registers[0]; 140 *rEBX = registers[1]; 141 *rECX = registers[2]; 142 *rEDX = registers[3]; 143 return false; 144 #else 145 return true; 146 #endif 147 #else 148 return true; 149 #endif 150 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) 151 #if defined(__GNUC__) 152 asm ("movl\t%%ebx, %%esi\n\t" 153 "cpuid\n\t" 154 "xchgl\t%%ebx, %%esi\n\t" 155 : "=a" (*rEAX), 156 "=S" (*rEBX), 157 "=c" (*rECX), 158 "=d" (*rEDX) 159 : "a" (value), 160 "c" (subleaf)); 161 return false; 162 #elif defined(_MSC_VER) 163 __asm { 164 mov eax,value 165 mov ecx,subleaf 166 cpuid 167 mov esi,rEAX 168 mov dword ptr [esi],eax 169 mov esi,rEBX 170 mov dword ptr [esi],ebx 171 mov esi,rECX 172 mov dword ptr [esi],ecx 173 mov esi,rEDX 174 mov dword ptr [esi],edx 175 } 176 return false; 177 #else 178 return true; 179 #endif 180 #else 181 return true; 182 #endif 183 } 184 185 void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family, 186 unsigned &Model) { 187 Family = (EAX >> 8) & 0xf; // Bits 8 - 11 188 Model = (EAX >> 4) & 0xf; // Bits 4 - 7 189 if (Family == 6 || Family == 0xf) { 190 if (Family == 0xf) 191 // Examine extended family ID if family ID is F. 192 Family += (EAX >> 20) & 0xff; // Bits 20 - 27 193 // Examine extended model ID if family ID is 6 or F. 194 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 195 } 196 } 197 198 unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) { 199 Triple TheTriple(TT); 200 if (TheTriple.getArch() == Triple::x86_64) 201 return DWARFFlavour::X86_64; 202 203 if (TheTriple.isOSDarwin()) 204 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic; 205 if (TheTriple.getOS() == Triple::MinGW32 || 206 TheTriple.getOS() == Triple::Cygwin) 207 // Unsupported by now, just quick fallback 208 return DWARFFlavour::X86_32_Generic; 209 return DWARFFlavour::X86_32_Generic; 210 } 211 212 /// getX86RegNum - This function maps LLVM register identifiers to their X86 213 /// specific numbering, which is used in various places encoding instructions. 214 unsigned X86_MC::getX86RegNum(unsigned RegNo) { 215 switch(RegNo) { 216 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX; 217 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX; 218 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX; 219 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX; 220 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH: 221 return N86::ESP; 222 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH: 223 return N86::EBP; 224 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH: 225 return N86::ESI; 226 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH: 227 return N86::EDI; 228 229 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: 230 return N86::EAX; 231 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B: 232 return N86::ECX; 233 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B: 234 return N86::EDX; 235 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B: 236 return N86::EBX; 237 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B: 238 return N86::ESP; 239 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B: 240 return N86::EBP; 241 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B: 242 return N86::ESI; 243 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B: 244 return N86::EDI; 245 246 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3: 247 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7: 248 return RegNo-X86::ST0; 249 250 case X86::XMM0: case X86::XMM8: 251 case X86::YMM0: case X86::YMM8: case X86::MM0: 252 return 0; 253 case X86::XMM1: case X86::XMM9: 254 case X86::YMM1: case X86::YMM9: case X86::MM1: 255 return 1; 256 case X86::XMM2: case X86::XMM10: 257 case X86::YMM2: case X86::YMM10: case X86::MM2: 258 return 2; 259 case X86::XMM3: case X86::XMM11: 260 case X86::YMM3: case X86::YMM11: case X86::MM3: 261 return 3; 262 case X86::XMM4: case X86::XMM12: 263 case X86::YMM4: case X86::YMM12: case X86::MM4: 264 return 4; 265 case X86::XMM5: case X86::XMM13: 266 case X86::YMM5: case X86::YMM13: case X86::MM5: 267 return 5; 268 case X86::XMM6: case X86::XMM14: 269 case X86::YMM6: case X86::YMM14: case X86::MM6: 270 return 6; 271 case X86::XMM7: case X86::XMM15: 272 case X86::YMM7: case X86::YMM15: case X86::MM7: 273 return 7; 274 275 case X86::ES: return 0; 276 case X86::CS: return 1; 277 case X86::SS: return 2; 278 case X86::DS: return 3; 279 case X86::FS: return 4; 280 case X86::GS: return 5; 281 282 case X86::CR0: case X86::CR8 : case X86::DR0: return 0; 283 case X86::CR1: case X86::CR9 : case X86::DR1: return 1; 284 case X86::CR2: case X86::CR10: case X86::DR2: return 2; 285 case X86::CR3: case X86::CR11: case X86::DR3: return 3; 286 case X86::CR4: case X86::CR12: case X86::DR4: return 4; 287 case X86::CR5: case X86::CR13: case X86::DR5: return 5; 288 case X86::CR6: case X86::CR14: case X86::DR6: return 6; 289 case X86::CR7: case X86::CR15: case X86::DR7: return 7; 290 291 // Pseudo index registers are equivalent to a "none" 292 // scaled index (See Intel Manual 2A, table 2-3) 293 case X86::EIZ: 294 case X86::RIZ: 295 return 4; 296 297 default: 298 assert((int(RegNo) > 0) && "Unknown physical register!"); 299 return 0; 300 } 301 } 302 303 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) { 304 // FIXME: TableGen these. 305 for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) { 306 int SEH = X86_MC::getX86RegNum(Reg); 307 switch (Reg) { 308 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: 309 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B: 310 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B: 311 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B: 312 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B: 313 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B: 314 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B: 315 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B: 316 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: 317 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15: 318 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11: 319 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15: 320 SEH += 8; 321 break; 322 } 323 MRI->mapLLVMRegToSEHReg(Reg, SEH); 324 } 325 } 326 327 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU, 328 StringRef FS) { 329 std::string ArchFS = X86_MC::ParseX86Triple(TT); 330 if (!FS.empty()) { 331 if (!ArchFS.empty()) 332 ArchFS = ArchFS + "," + FS.str(); 333 else 334 ArchFS = FS; 335 } 336 337 std::string CPUName = CPU; 338 if (CPUName.empty()) { 339 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\ 340 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) 341 CPUName = sys::getHostCPUName(); 342 #else 343 CPUName = "generic"; 344 #endif 345 } 346 347 MCSubtargetInfo *X = new MCSubtargetInfo(); 348 InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS); 349 return X; 350 } 351 352 static MCInstrInfo *createX86MCInstrInfo() { 353 MCInstrInfo *X = new MCInstrInfo(); 354 InitX86MCInstrInfo(X); 355 return X; 356 } 357 358 static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) { 359 Triple TheTriple(TT); 360 unsigned RA = (TheTriple.getArch() == Triple::x86_64) 361 ? X86::RIP // Should have dwarf #16. 362 : X86::EIP; // Should have dwarf #8. 363 364 MCRegisterInfo *X = new MCRegisterInfo(); 365 InitX86MCRegisterInfo(X, RA, 366 X86_MC::getDwarfRegFlavour(TT, false), 367 X86_MC::getDwarfRegFlavour(TT, true)); 368 X86_MC::InitLLVM2SEHRegisterMapping(X); 369 return X; 370 } 371 372 static MCAsmInfo *createX86MCAsmInfo(const Target &T, StringRef TT) { 373 Triple TheTriple(TT); 374 bool is64Bit = TheTriple.getArch() == Triple::x86_64; 375 376 MCAsmInfo *MAI; 377 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) { 378 if (is64Bit) 379 MAI = new X86_64MCAsmInfoDarwin(TheTriple); 380 else 381 MAI = new X86MCAsmInfoDarwin(TheTriple); 382 } else if (TheTriple.getOS() == Triple::Win32) { 383 MAI = new X86MCAsmInfoMicrosoft(TheTriple); 384 } else if (TheTriple.getOS() == Triple::MinGW32 || TheTriple.getOS() == Triple::Cygwin) { 385 MAI = new X86MCAsmInfoGNUCOFF(TheTriple); 386 } else { 387 MAI = new X86ELFMCAsmInfo(TheTriple); 388 } 389 390 // Initialize initial frame state. 391 // Calculate amount of bytes used for return address storing 392 int stackGrowth = is64Bit ? -8 : -4; 393 394 // Initial state of the frame pointer is esp+stackGrowth. 395 MachineLocation Dst(MachineLocation::VirtualFP); 396 MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth); 397 MAI->addInitialFrameState(0, Dst, Src); 398 399 // Add return address to move list 400 MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth); 401 MachineLocation CSSrc(is64Bit ? X86::RIP : X86::EIP); 402 MAI->addInitialFrameState(0, CSDst, CSSrc); 403 404 return MAI; 405 } 406 407 static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM, 408 CodeModel::Model CM, 409 CodeGenOpt::Level OL) { 410 MCCodeGenInfo *X = new MCCodeGenInfo(); 411 412 Triple T(TT); 413 bool is64Bit = T.getArch() == Triple::x86_64; 414 415 if (RM == Reloc::Default) { 416 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode. 417 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we 418 // use static relocation model by default. 419 if (T.isOSDarwin()) { 420 if (is64Bit) 421 RM = Reloc::PIC_; 422 else 423 RM = Reloc::DynamicNoPIC; 424 } else if (T.isOSWindows() && is64Bit) 425 RM = Reloc::PIC_; 426 else 427 RM = Reloc::Static; 428 } 429 430 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC 431 // is defined as a model for code which may be used in static or dynamic 432 // executables but not necessarily a shared library. On X86-32 we just 433 // compile in -static mode, in x86-64 we use PIC. 434 if (RM == Reloc::DynamicNoPIC) { 435 if (is64Bit) 436 RM = Reloc::PIC_; 437 else if (!T.isOSDarwin()) 438 RM = Reloc::Static; 439 } 440 441 // If we are on Darwin, disallow static relocation model in X86-64 mode, since 442 // the Mach-O file format doesn't support it. 443 if (RM == Reloc::Static && T.isOSDarwin() && is64Bit) 444 RM = Reloc::PIC_; 445 446 // For static codegen, if we're not already set, use Small codegen. 447 if (CM == CodeModel::Default) 448 CM = CodeModel::Small; 449 else if (CM == CodeModel::JITDefault) 450 // 64-bit JIT places everything in the same buffer except external funcs. 451 CM = is64Bit ? CodeModel::Large : CodeModel::Small; 452 453 X->InitMCCodeGenInfo(RM, CM, OL); 454 return X; 455 } 456 457 static MCStreamer *createMCStreamer(const Target &T, StringRef TT, 458 MCContext &Ctx, MCAsmBackend &MAB, 459 raw_ostream &_OS, 460 MCCodeEmitter *_Emitter, 461 bool RelaxAll, 462 bool NoExecStack) { 463 Triple TheTriple(TT); 464 465 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) 466 return createMachOStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll); 467 468 if (TheTriple.isOSWindows()) 469 return createWinCOFFStreamer(Ctx, MAB, *_Emitter, _OS, RelaxAll); 470 471 return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack); 472 } 473 474 static MCInstPrinter *createX86MCInstPrinter(const Target &T, 475 unsigned SyntaxVariant, 476 const MCAsmInfo &MAI, 477 const MCInstrInfo &MII, 478 const MCRegisterInfo &MRI, 479 const MCSubtargetInfo &STI) { 480 if (SyntaxVariant == 0) 481 return new X86ATTInstPrinter(MAI, MII, MRI); 482 if (SyntaxVariant == 1) 483 return new X86IntelInstPrinter(MAI, MII, MRI); 484 return 0; 485 } 486 487 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) { 488 return new MCInstrAnalysis(Info); 489 } 490 491 // Force static initialization. 492 extern "C" void LLVMInitializeX86TargetMC() { 493 // Register the MC asm info. 494 RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo); 495 RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo); 496 497 // Register the MC codegen info. 498 RegisterMCCodeGenInfoFn C(TheX86_32Target, createX86MCCodeGenInfo); 499 RegisterMCCodeGenInfoFn D(TheX86_64Target, createX86MCCodeGenInfo); 500 501 // Register the MC instruction info. 502 TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo); 503 TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo); 504 505 // Register the MC register info. 506 TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo); 507 TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo); 508 509 // Register the MC subtarget info. 510 TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target, 511 X86_MC::createX86MCSubtargetInfo); 512 TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target, 513 X86_MC::createX86MCSubtargetInfo); 514 515 // Register the MC instruction analyzer. 516 TargetRegistry::RegisterMCInstrAnalysis(TheX86_32Target, 517 createX86MCInstrAnalysis); 518 TargetRegistry::RegisterMCInstrAnalysis(TheX86_64Target, 519 createX86MCInstrAnalysis); 520 521 // Register the code emitter. 522 TargetRegistry::RegisterMCCodeEmitter(TheX86_32Target, 523 createX86MCCodeEmitter); 524 TargetRegistry::RegisterMCCodeEmitter(TheX86_64Target, 525 createX86MCCodeEmitter); 526 527 // Register the asm backend. 528 TargetRegistry::RegisterMCAsmBackend(TheX86_32Target, 529 createX86_32AsmBackend); 530 TargetRegistry::RegisterMCAsmBackend(TheX86_64Target, 531 createX86_64AsmBackend); 532 533 // Register the object streamer. 534 TargetRegistry::RegisterMCObjectStreamer(TheX86_32Target, 535 createMCStreamer); 536 TargetRegistry::RegisterMCObjectStreamer(TheX86_64Target, 537 createMCStreamer); 538 539 // Register the MCInstPrinter. 540 TargetRegistry::RegisterMCInstPrinter(TheX86_32Target, 541 createX86MCInstPrinter); 542 TargetRegistry::RegisterMCInstPrinter(TheX86_64Target, 543 createX86MCInstPrinter); 544 } 545
