1 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Hexagon implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef HexagonINSTRUCTIONINFO_H 15 #define HexagonINSTRUCTIONINFO_H 16 17 #include "HexagonRegisterInfo.h" 18 #include "MCTargetDesc/HexagonBaseInfo.h" 19 #include "llvm/Target/TargetFrameLowering.h" 20 #include "llvm/Target/TargetInstrInfo.h" 21 22 23 #define GET_INSTRINFO_HEADER 24 #include "HexagonGenInstrInfo.inc" 25 26 namespace llvm { 27 28 class HexagonInstrInfo : public HexagonGenInstrInfo { 29 const HexagonRegisterInfo RI; 30 const HexagonSubtarget& Subtarget; 31 public: 32 explicit HexagonInstrInfo(HexagonSubtarget &ST); 33 34 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 35 /// such, whenever a client has an instance of instruction info, it should 36 /// always be able to get register info as well (through this method). 37 /// 38 virtual const HexagonRegisterInfo &getRegisterInfo() const { return RI; } 39 40 /// isLoadFromStackSlot - If the specified machine instruction is a direct 41 /// load from a stack slot, return the virtual or physical register number of 42 /// the destination along with the FrameIndex of the loaded stack slot. If 43 /// not, return 0. This predicate must return 0 if the instruction has 44 /// any side effects other than loading from the stack slot. 45 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 46 int &FrameIndex) const; 47 48 /// isStoreToStackSlot - If the specified machine instruction is a direct 49 /// store to a stack slot, return the virtual or physical register number of 50 /// the source reg along with the FrameIndex of the loaded stack slot. If 51 /// not, return 0. This predicate must return 0 if the instruction has 52 /// any side effects other than storing to the stack slot. 53 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 54 int &FrameIndex) const; 55 56 57 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 58 MachineBasicBlock *&FBB, 59 SmallVectorImpl<MachineOperand> &Cond, 60 bool AllowModify) const; 61 62 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 63 64 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 65 MachineBasicBlock *FBB, 66 const SmallVectorImpl<MachineOperand> &Cond, 67 DebugLoc DL) const; 68 69 virtual bool analyzeCompare(const MachineInstr *MI, 70 unsigned &SrcReg, unsigned &SrcReg2, 71 int &Mask, int &Value) const; 72 73 virtual void copyPhysReg(MachineBasicBlock &MBB, 74 MachineBasicBlock::iterator I, DebugLoc DL, 75 unsigned DestReg, unsigned SrcReg, 76 bool KillSrc) const; 77 78 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 79 MachineBasicBlock::iterator MBBI, 80 unsigned SrcReg, bool isKill, int FrameIndex, 81 const TargetRegisterClass *RC, 82 const TargetRegisterInfo *TRI) const; 83 84 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 85 SmallVectorImpl<MachineOperand> &Addr, 86 const TargetRegisterClass *RC, 87 SmallVectorImpl<MachineInstr*> &NewMIs) const; 88 89 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 90 MachineBasicBlock::iterator MBBI, 91 unsigned DestReg, int FrameIndex, 92 const TargetRegisterClass *RC, 93 const TargetRegisterInfo *TRI) const; 94 95 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 96 SmallVectorImpl<MachineOperand> &Addr, 97 const TargetRegisterClass *RC, 98 SmallVectorImpl<MachineInstr*> &NewMIs) const; 99 100 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 101 MachineInstr* MI, 102 const SmallVectorImpl<unsigned> &Ops, 103 int FrameIndex) const; 104 105 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 106 MachineInstr* MI, 107 const SmallVectorImpl<unsigned> &Ops, 108 MachineInstr* LoadMI) const { 109 return 0; 110 } 111 112 unsigned createVR(MachineFunction* MF, MVT VT) const; 113 114 virtual bool isPredicable(MachineInstr *MI) const; 115 virtual bool 116 PredicateInstruction(MachineInstr *MI, 117 const SmallVectorImpl<MachineOperand> &Cond) const; 118 119 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 120 unsigned ExtraPredCycles, 121 const BranchProbability &Probability) const; 122 123 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 124 unsigned NumTCycles, unsigned ExtraTCycles, 125 MachineBasicBlock &FMBB, 126 unsigned NumFCycles, unsigned ExtraFCycles, 127 const BranchProbability &Probability) const; 128 129 virtual bool isPredicated(const MachineInstr *MI) const; 130 virtual bool DefinesPredicate(MachineInstr *MI, 131 std::vector<MachineOperand> &Pred) const; 132 virtual bool 133 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 134 const SmallVectorImpl<MachineOperand> &Pred2) const; 135 136 virtual bool 137 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 138 139 virtual bool 140 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles, 141 const BranchProbability &Probability) const; 142 143 virtual DFAPacketizer* 144 CreateTargetScheduleState(const TargetMachine *TM, 145 const ScheduleDAG *DAG) const; 146 147 virtual bool isSchedulingBoundary(const MachineInstr *MI, 148 const MachineBasicBlock *MBB, 149 const MachineFunction &MF) const; 150 bool isValidOffset(const int Opcode, const int Offset) const; 151 bool isValidAutoIncImm(const EVT VT, const int Offset) const; 152 bool isMemOp(const MachineInstr *MI) const; 153 bool isSpillPredRegOp(const MachineInstr *MI) const; 154 bool isU6_3Immediate(const int value) const; 155 bool isU6_2Immediate(const int value) const; 156 bool isU6_1Immediate(const int value) const; 157 bool isU6_0Immediate(const int value) const; 158 bool isS4_3Immediate(const int value) const; 159 bool isS4_2Immediate(const int value) const; 160 bool isS4_1Immediate(const int value) const; 161 bool isS4_0Immediate(const int value) const; 162 bool isS12_Immediate(const int value) const; 163 bool isU6_Immediate(const int value) const; 164 bool isS8_Immediate(const int value) const; 165 bool isS6_Immediate(const int value) const; 166 167 bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const; 168 bool isConditionalTransfer(const MachineInstr* MI) const; 169 bool isConditionalALU32 (const MachineInstr* MI) const; 170 bool isConditionalLoad (const MachineInstr* MI) const; 171 bool isConditionalStore(const MachineInstr* MI) const; 172 bool isNewValueInst(const MachineInstr* MI) const; 173 bool isDeallocRet(const MachineInstr *MI) const; 174 unsigned getInvertedPredicatedOpcode(const int Opc) const; 175 bool isExtendable(const MachineInstr* MI) const; 176 bool isExtended(const MachineInstr* MI) const; 177 bool isPostIncrement(const MachineInstr* MI) const; 178 bool isNewValueStore(const MachineInstr* MI) const; 179 bool isNewValueJump(const MachineInstr* MI) const; 180 bool isNewValueJumpCandidate(const MachineInstr *MI) const; 181 182 183 void immediateExtend(MachineInstr *MI) const; 184 bool isConstExtended(MachineInstr *MI) const; 185 unsigned getAddrMode(const MachineInstr* MI) const; 186 bool isOperandExtended(const MachineInstr *MI, 187 unsigned short OperandNum) const; 188 unsigned short getCExtOpNum(const MachineInstr *MI) const; 189 int getMinValue(const MachineInstr *MI) const; 190 int getMaxValue(const MachineInstr *MI) const; 191 bool NonExtEquivalentExists (const MachineInstr *MI) const; 192 short getNonExtOpcode(const MachineInstr *MI) const; 193 private: 194 int getMatchingCondBranchOpcode(int Opc, bool sense) const; 195 196 }; 197 198 } 199 200 #endif 201
