| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.cpp | 139 unsigned BaseReg =
142 BaseReg, FrameReg, BaseReg, Offset);
143 FrameReg = BaseReg;
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1RegisterInfo.h | 53 unsigned BaseReg, int64_t Offset) const;
|
| Thumb1RegisterInfo.cpp | 86 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
93 unsigned DestReg, unsigned BaseReg,
100 (BaseReg != 0 && !isARMLowRegister(BaseReg));
112 assert(BaseReg == ARM::SP && "Unexpected!");
135 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
137 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
166 /// a destreg = basereg + immediate in Thumb code.
170 unsigned DestReg, unsigned BaseReg,
186 if (DestReg == BaseReg && BaseReg == ARM::SP)
[all...] |
| Thumb2InstrInfo.cpp | 179 unsigned DestReg, unsigned BaseReg, int NumBytes,
187 if (DestReg != ARM::SP && DestReg != BaseReg &&
209 .addReg(BaseReg, RegState::Kill)
216 .addReg(BaseReg, RegState::Kill)
227 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
230 .addReg(BaseReg).setMIFlags(MIFlags));
231 BaseReg = ARM::SP;
236 if (BaseReg == ARM::SP) {
242 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags));
260 assert(DestReg != ARM::SP && BaseReg != ARM::SP)
[all...] |
| ARMBaseRegisterInfo.h | 132 unsigned BaseReg, int FrameIdx,
135 unsigned BaseReg, int64_t Offset) const;
|
| ARMBaseRegisterInfo.cpp | 538 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
542 unsigned BaseReg, int FrameIdx,
556 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
558 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
567 unsigned BaseReg, int64_t Offset) const {
584 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
587 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
|
| ARMBaseInstrInfo.h | 380 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
384 unsigned DestReg, unsigned BaseReg, int NumBytes,
390 unsigned DestReg, unsigned BaseReg, int NumBytes,
395 unsigned DestReg, unsigned BaseReg,
|
| ARMLoadStoreOptimizer.cpp | [all...] |
| Thumb2SizeReduction.cpp | 129 // ARM::t2STM (with no basereg writeback) has no Thumb1 equivalent
391 unsigned BaseReg = MI->getOperand(0).getReg();
392 if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA)
399 if (MI->getOperand(i).getReg() == BaseReg) {
413 unsigned BaseReg = MI->getOperand(1).getReg();
414 if (BaseReg != ARM::SP)
427 unsigned BaseReg = MI->getOperand(1).getReg();
428 if (BaseReg == ARM::SP &&
433 } else if (!isARMLowRegister(BaseReg) ||
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMBaseInstrInfo.cpp | 159 unsigned BaseReg = Base.getReg();
175 .addReg(BaseReg).addImm(Amt)
182 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
187 .addReg(BaseReg).addReg(OffReg)
198 .addReg(BaseReg).addImm(Amt)
203 .addReg(BaseReg).addReg(OffReg)
225 .addReg(BaseReg).addImm(0).addImm(Pred);
229 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
[all...] |
| /external/llvm/lib/CodeGen/ |
| LocalStackSlotAllocation.cpp | 290 unsigned BaseReg = 0;
310 BaseReg = RegOffset.first;
319 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
321 DEBUG(dbgs() << " Materializing base register " << BaseReg <<
328 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx,
339 std::pair<unsigned, int64_t>(BaseReg, BaseOffset));
343 assert(BaseReg != 0 && "Unable to allocate virtual base register!");
347 TRI->resolveFrameIndex(I, BaseReg, Offset);
|
| MachineScheduler.cpp | 757 unsigned BaseReg;
760 : SU(su), BaseReg(reg), Offset(ofs) {}
781 if (LHS.BaseReg != RHS.BaseReg)
782 return LHS.BaseReg < RHS.BaseReg;
791 unsigned BaseReg;
793 if (TII->getLdStBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI))
794 LoadRecords.push_back(LoadInfo(SU, BaseReg, Offset));
801 if (LoadRecords[Idx].BaseReg != LoadRecords[Idx+1].BaseReg)
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86IntelInstPrinter.cpp | 160 const MCOperand &BaseReg = MI->getOperand(Op);
175 if (BaseReg.getReg()) {
194 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
| X86ATTInstPrinter.cpp | 176 const MCOperand &BaseReg = MI->getOperand(Op);
191 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
198 if (IndexReg.getReg() || BaseReg.getReg()) {
200 if (BaseReg.getReg())
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 190 unsigned BaseReg;
254 return Mem.BaseReg;
507 Res->Mem.BaseReg = 0;
518 unsigned BaseReg, unsigned IndexReg,
523 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
531 Res->Mem.BaseReg = BaseReg;
544 unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI; local
550 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0)
554 unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI; local
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 167 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
170 if ((BaseReg.getReg() != 0 &&
171 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
182 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
185 if ((BaseReg.getReg() != 0 &&
186 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
197 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
200 if ((BaseReg.getReg() != 0 &&
201 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
307 unsigned BaseReg = Base.getReg()
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86CodeEmitter.cpp | 489 unsigned BaseReg = Base.getReg();
492 if (BaseReg == X86::RIP ||
507 // If no BaseReg, issue a RIP relative instruction only if the MCE can
511 if (BaseReg != 0 && BaseReg != X86::RIP)
512 BaseRegNo = getX86RegNum(BaseReg);
522 (!Is64BitMode || BaseReg != 0)) {
523 if (BaseReg == 0 || // [disp32] in X86-32 mode
524 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
558 if (BaseReg == 0)
[all...] |
| X86AsmPrinter.cpp | 272 const MachineOperand &BaseReg = MI->getOperand(Op);
277 bool HasBaseReg = BaseReg.getReg() != 0;
279 BaseReg.getReg() == X86::RIP)
331 const MachineOperand &BaseReg = MI->getOperand(Op);
346 if (BaseReg.getReg()) {
364 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
| /external/llvm/lib/Transforms/Scalar/ |
| CodeGenPrepare.cpp | 827 Value *BaseReg;
829 ExtAddrMode() : BaseReg(0), ScaledReg(0) {}
834 return (BaseReg == O.BaseReg) && (ScaledReg == O.ScaledReg) &&
858 if (BaseReg) {
861 WriteAsOperand(OS, BaseReg, /*PrintType=*/false);
[all...] |
| LoopStrengthReduce.cpp | [all...] |
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 714 /// BaseReg to be a pointer to FrameIdx before insertion point I.
716 unsigned BaseReg, int FrameIdx,
725 unsigned BaseReg, int64_t Offset) const {
[all...] |
| TargetInstrInfo.h | 622 unsigned &BaseReg, unsigned &Offset,
[all...] |
| /external/clang/lib/StaticAnalyzer/Core/ |
| Store.cpp | 285 const MemRegion *BaseReg =
289 return loc::MemRegionVal(BaseReg);
|
| /external/llvm/lib/Target/R600/ |
| AMDILISelDAGToDAG.cpp | 76 SDValue &BaseReg, SDValue& Offset);
572 SDValue& BaseReg, SDValue &Offset) {
574 BaseReg = Addr;
|
