1 //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief Contains the definition of a TargetInstrInfo class that is common 12 /// to all AMD GPUs. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef AMDGPUINSTRUCTIONINFO_H 17 #define AMDGPUINSTRUCTIONINFO_H 18 19 #include "AMDGPUInstrInfo.h" 20 #include "AMDGPURegisterInfo.h" 21 #include "llvm/Target/TargetInstrInfo.h" 22 #include <map> 23 24 #define GET_INSTRINFO_HEADER 25 #define GET_INSTRINFO_ENUM 26 #define GET_INSTRINFO_OPERAND_ENUM 27 #include "AMDGPUGenInstrInfo.inc" 28 29 #define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT 30 #define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT 31 #define OPCODE_IS_ZERO AMDGPU::PRED_SETE 32 #define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE 33 34 namespace llvm { 35 36 class AMDGPUTargetMachine; 37 class MachineFunction; 38 class MachineInstr; 39 class MachineInstrBuilder; 40 41 class AMDGPUInstrInfo : public AMDGPUGenInstrInfo { 42 private: 43 const AMDGPURegisterInfo RI; 44 bool getNextBranchInstr(MachineBasicBlock::iterator &iter, 45 MachineBasicBlock &MBB) const; 46 protected: 47 TargetMachine &TM; 48 public: 49 explicit AMDGPUInstrInfo(TargetMachine &tm); 50 51 virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0; 52 53 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, 54 unsigned &DstReg, unsigned &SubIdx) const; 55 56 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 57 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 58 int &FrameIndex) const; 59 bool hasLoadFromStackSlot(const MachineInstr *MI, 60 const MachineMemOperand *&MMO, 61 int &FrameIndex) const; 62 unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 63 unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI, 64 int &FrameIndex) const; 65 bool hasStoreFromStackSlot(const MachineInstr *MI, 66 const MachineMemOperand *&MMO, 67 int &FrameIndex) const; 68 69 MachineInstr * 70 convertToThreeAddress(MachineFunction::iterator &MFI, 71 MachineBasicBlock::iterator &MBBI, 72 LiveVariables *LV) const; 73 74 75 virtual void copyPhysReg(MachineBasicBlock &MBB, 76 MachineBasicBlock::iterator MI, DebugLoc DL, 77 unsigned DestReg, unsigned SrcReg, 78 bool KillSrc) const = 0; 79 80 void storeRegToStackSlot(MachineBasicBlock &MBB, 81 MachineBasicBlock::iterator MI, 82 unsigned SrcReg, bool isKill, int FrameIndex, 83 const TargetRegisterClass *RC, 84 const TargetRegisterInfo *TRI) const; 85 void loadRegFromStackSlot(MachineBasicBlock &MBB, 86 MachineBasicBlock::iterator MI, 87 unsigned DestReg, int FrameIndex, 88 const TargetRegisterClass *RC, 89 const TargetRegisterInfo *TRI) const; 90 91 protected: 92 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, 93 MachineInstr *MI, 94 const SmallVectorImpl<unsigned> &Ops, 95 int FrameIndex) const; 96 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, 97 MachineInstr *MI, 98 const SmallVectorImpl<unsigned> &Ops, 99 MachineInstr *LoadMI) const; 100 public: 101 bool canFoldMemoryOperand(const MachineInstr *MI, 102 const SmallVectorImpl<unsigned> &Ops) const; 103 bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 104 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 105 SmallVectorImpl<MachineInstr *> &NewMIs) const; 106 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 107 SmallVectorImpl<SDNode *> &NewNodes) const; 108 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 109 bool UnfoldLoad, bool UnfoldStore, 110 unsigned *LoadRegIndex = 0) const; 111 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 112 int64_t Offset1, int64_t Offset2, 113 unsigned NumLoads) const; 114 115 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 116 void insertNoop(MachineBasicBlock &MBB, 117 MachineBasicBlock::iterator MI) const; 118 bool isPredicated(const MachineInstr *MI) const; 119 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 120 const SmallVectorImpl<MachineOperand> &Pred2) const; 121 bool DefinesPredicate(MachineInstr *MI, 122 std::vector<MachineOperand> &Pred) const; 123 bool isPredicable(MachineInstr *MI) const; 124 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 125 126 // Helper functions that check the opcode for status information 127 bool isLoadInst(llvm::MachineInstr *MI) const; 128 bool isExtLoadInst(llvm::MachineInstr *MI) const; 129 bool isSWSExtLoadInst(llvm::MachineInstr *MI) const; 130 bool isSExtLoadInst(llvm::MachineInstr *MI) const; 131 bool isZExtLoadInst(llvm::MachineInstr *MI) const; 132 bool isAExtLoadInst(llvm::MachineInstr *MI) const; 133 bool isStoreInst(llvm::MachineInstr *MI) const; 134 bool isTruncStoreInst(llvm::MachineInstr *MI) const; 135 bool isRegisterStore(const MachineInstr &MI) const; 136 bool isRegisterLoad(const MachineInstr &MI) const; 137 138 //===---------------------------------------------------------------------===// 139 // Pure virtual funtions to be implemented by sub-classes. 140 //===---------------------------------------------------------------------===// 141 142 virtual MachineInstr* getMovImmInstr(MachineFunction *MF, unsigned DstReg, 143 int64_t Imm) const = 0; 144 virtual unsigned getIEQOpcode() const = 0; 145 virtual bool isMov(unsigned opcode) const = 0; 146 147 /// \returns the smallest register index that will be accessed by an indirect 148 /// read or write or -1 if indirect addressing is not used by this program. 149 virtual int getIndirectIndexBegin(const MachineFunction &MF) const = 0; 150 151 /// \returns the largest register index that will be accessed by an indirect 152 /// read or write or -1 if indirect addressing is not used by this program. 153 virtual int getIndirectIndexEnd(const MachineFunction &MF) const = 0; 154 155 /// \brief Calculate the "Indirect Address" for the given \p RegIndex and 156 /// \p Channel 157 /// 158 /// We model indirect addressing using a virtual address space that can be 159 /// accesed with loads and stores. The "Indirect Address" is the memory 160 /// address in this virtual address space that maps to the given \p RegIndex 161 /// and \p Channel. 162 virtual unsigned calculateIndirectAddress(unsigned RegIndex, 163 unsigned Channel) const = 0; 164 165 /// \returns The register class to be used for storing values to an 166 /// "Indirect Address" . 167 virtual const TargetRegisterClass *getIndirectAddrStoreRegClass( 168 unsigned SourceReg) const = 0; 169 170 /// \returns The register class to be used for loading values from 171 /// an "Indirect Address" . 172 virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const = 0; 173 174 /// \brief Build instruction(s) for an indirect register write. 175 /// 176 /// \returns The instruction that performs the indirect register write 177 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, 178 MachineBasicBlock::iterator I, 179 unsigned ValueReg, unsigned Address, 180 unsigned OffsetReg) const = 0; 181 182 /// \brief Build instruction(s) for an indirect register read. 183 /// 184 /// \returns The instruction that performs the indirect register read 185 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, 186 MachineBasicBlock::iterator I, 187 unsigned ValueReg, unsigned Address, 188 unsigned OffsetReg) const = 0; 189 190 /// \returns the register class whose sub registers are the set of all 191 /// possible registers that can be used for indirect addressing. 192 virtual const TargetRegisterClass *getSuperIndirectRegClass() const = 0; 193 194 195 /// \brief Convert the AMDIL MachineInstr to a supported ISA 196 /// MachineInstr 197 virtual void convertToISA(MachineInstr & MI, MachineFunction &MF, 198 DebugLoc DL) const; 199 200 }; 201 202 namespace AMDGPU { 203 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex); 204 } // End namespace AMDGPU 205 206 } // End llvm namespace 207 208 #define AMDGPU_FLAG_REGISTER_LOAD (UINT64_C(1) << 63) 209 #define AMDGPU_FLAG_REGISTER_STORE (UINT64_C(1) << 62) 210 211 #endif // AMDGPUINSTRINFO_H 212
