| /external/llvm/lib/Target/R600/ |
| AMDGPURegisterInfo.cpp | 1 //===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
30 const uint16_t AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;
52 case 0: return AMDGPU::sub0;
53 case 1: return AMDGPU::sub1;
54 case 2: return AMDGPU::sub2;
55 case 3: return AMDGPU::sub3;
56 case 4: return AMDGPU::sub4;
57 case 5: return AMDGPU::sub5;
58 case 6: return AMDGPU::sub6;
59 case 7: return AMDGPU::sub7
[all...] |
| SIInstrInfo.cpp | 43 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
46 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
47 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7
[all...] |
| R600RegisterInfo.cpp | 31 Reserved.set(AMDGPU::ZERO);
32 Reserved.set(AMDGPU::HALF);
33 Reserved.set(AMDGPU::ONE);
34 Reserved.set(AMDGPU::ONE_INT);
35 Reserved.set(AMDGPU::NEG_HALF);
36 Reserved.set(AMDGPU::NEG_ONE);
37 Reserved.set(AMDGPU::PV_X);
38 Reserved.set(AMDGPU::ALU_LITERAL_X);
39 Reserved.set(AMDGPU::ALU_CONST);
40 Reserved.set(AMDGPU::PREDICATE_BIT)
[all...] |
| R600InstrInfo.cpp | 16 #include "AMDGPU.h"
55 if (AMDGPU::R600_Reg128RegClass.contains(DestReg) &&
56 AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
58 } else if(AMDGPU::R600_Reg64RegClass.contains(DestReg) &&
59 AMDGPU::R600_Reg64RegClass.contains(SrcReg)) {
66 buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
73 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
75 NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0))
82 MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc());
85 MIB.addReg(AMDGPU::ALU_LITERAL_X)
[all...] |
| SIRegisterInfo.cpp | 39 case AMDGPU::GPRF32RegClassID:
40 return &AMDGPU::VReg_32RegClass;
49 case MVT::i32: return &AMDGPU::VReg_32RegClass;
57 &AMDGPU::VReg_32RegClass,
58 &AMDGPU::SReg_32RegClass,
59 &AMDGPU::VReg_64RegClass,
60 &AMDGPU::SReg_64RegClass,
61 &AMDGPU::SReg_128RegClass,
62 &AMDGPU::SReg_256RegClass
|
| SILowerControlFlow.cpp | 51 #include "AMDGPU.h"
138 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
140 .addReg(AMDGPU::EXEC);
155 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
157 .addReg(AMDGPU::EXEC);
160 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP))
166 .addReg(AMDGPU::VGPR0)
167 .addReg(AMDGPU::VGPR0)
168 .addReg(AMDGPU::VGPR0)
169 .addReg(AMDGPU::VGPR0)
[all...] |
| R600EmitClauseMarkers.cpp | 17 #include "AMDGPU.h"
39 case AMDGPU::INTERP_PAIR_XY:
40 case AMDGPU::INTERP_PAIR_ZW:
41 case AMDGPU::INTERP_VEC_LOAD:
42 case AMDGPU::DOT_4:
44 case AMDGPU::KILL:
59 if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X)
71 case AMDGPU::PRED_X:
72 case AMDGPU::INTERP_PAIR_XY:
73 case AMDGPU::INTERP_PAIR_ZW
[all...] |
| R600ControlFlowFinalizer.cpp | 17 #include "AMDGPU.h"
58 case AMDGPU::KILL:
59 case AMDGPU::RETURN:
71 Opcode = isEg ? AMDGPU::CF_TC_EG : AMDGPU::CF_TC_R600;
74 Opcode = isEg ? AMDGPU::CF_VC_EG : AMDGPU::CF_VC_R600;
77 Opcode = isEg ? AMDGPU::CF_CALL_FS_EG : AMDGPU::CF_CALL_FS_R600;
80 Opcode = isEg ? AMDGPU::WHILE_LOOP_EG : AMDGPU::WHILE_LOOP_R600
[all...] |
| R600ExpandSpecialInstrs.cpp | 17 #include "AMDGPU.h"
74 case AMDGPU::PRED_X: {
82 AMDGPU::ZERO); // src1
85 TII->setImmOperand(PredSet, AMDGPU::OpName::update_exec_mask, 1);
87 TII->setImmOperand(PredSet, AMDGPU::OpName::update_pred, 1);
93 case AMDGPU::INTERP_PAIR_XY: {
95 unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
104 DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W;
106 BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_XY
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600RegisterInfo.cpp | 32 Reserved.set(AMDGPU::ZERO);
33 Reserved.set(AMDGPU::HALF);
34 Reserved.set(AMDGPU::ONE);
35 Reserved.set(AMDGPU::ONE_INT);
36 Reserved.set(AMDGPU::NEG_HALF);
37 Reserved.set(AMDGPU::NEG_ONE);
38 Reserved.set(AMDGPU::PV_X);
39 Reserved.set(AMDGPU::ALU_LITERAL_X);
40 Reserved.set(AMDGPU::PREDICATE_BIT);
41 Reserved.set(AMDGPU::PRED_SEL_OFF)
[all...] |
| SIAssignInterpRegs.cpp | 21 #include "AMDGPU.h"
71 {false, {AMDGPU::PERSP_SAMPLE_I, AMDGPU::PERSP_SAMPLE_J}, 2},
72 {false, {AMDGPU::PERSP_CENTER_I, AMDGPU::PERSP_CENTER_J}, 2},
73 {false, {AMDGPU::PERSP_CENTROID_I, AMDGPU::PERSP_CENTROID_J}, 2},
74 {false, {AMDGPU::PERSP_I_W, AMDGPU::PERSP_J_W, AMDGPU::PERSP_1_W}, 3}
[all...] |
| SIRegisterInfo.cpp | 36 case AMDGPU::M0: return 124;
37 case AMDGPU::SREG_LIT_0: return 128;
46 case AMDGPU::GPRF32RegClassID:
47 return &AMDGPU::VReg_32RegClass;
57 case MVT::i32: return &AMDGPU::VReg_32RegClass;
|
| SIInstrInfo.cpp | 46 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
55 MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_IMM_I32), DebugLoc());
67 case AMDGPU::S_MOV_B32:
68 case AMDGPU::S_MOV_B64:
69 case AMDGPU::V_MOV_B32_e32:
70 case AMDGPU::V_MOV_B32_e64:
71 case AMDGPU::V_MOV_IMM_F32:
72 case AMDGPU::V_MOV_IMM_I32
[all...] |
| R600InstrInfo.cpp | 54 if (AMDGPU::R600_Reg128RegClass.contains(DestReg)
55 && AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
58 BuildMI(MBB, MI, DL, get(AMDGPU::MOV))
68 assert(!AMDGPU::R600_Reg128RegClass.contains(DestReg)
69 && !AMDGPU::R600_Reg128RegClass.contains(SrcReg));
71 BuildMI(MBB, MI, DL, get(AMDGPU::MOV), DestReg)
81 MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc());
83 MachineInstrBuilder(MI).addReg(AMDGPU::ALU_LITERAL_X);
92 return AMDGPU::SETE_INT;
101 case AMDGPU::MOV
[all...] |
| R600ISelLowering.cpp | 30 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
31 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
32 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
33 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
62 case AMDGPU::CLAMP_R600:
65 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
69 .addReg(AMDGPU::PRED_SEL_OFF);
73 case AMDGPU::FABS_R600:
76 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
80 .addReg(AMDGPU::PRED_SEL_OFF)
[all...] |
| Makefile | 40 $(call tablegen, -gen-register-info, AMDGPU.td, $@)
43 $(call tablegen, -gen-instr-info, AMDGPU.td, $@)
46 $(call tablegen, -gen-asm-writer, AMDGPU.td, $@)
49 $(call tablegen, -gen-dag-isel, AMDGPU.td, $@)
52 $(call tablegen, -gen-callingconv, AMDGPU.td, $@)
55 $(call tablegen, -gen-subtarget, AMDGPU.td, $@)
58 $(call tablegen, -gen-enhanced-disassembly-info, AMDGPU.td, $@)
61 $(call tablegen, -gen-tgt-intrinsic, AMDGPU.td, $@)
64 $(call tablegen, -gen-emitter, AMDGPU.td, $@)
67 $(call tablegen, -mc-emitter -gen-emitter, AMDGPU.td, $@
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600RegisterInfo.cpp | 32 Reserved.set(AMDGPU::ZERO);
33 Reserved.set(AMDGPU::HALF);
34 Reserved.set(AMDGPU::ONE);
35 Reserved.set(AMDGPU::ONE_INT);
36 Reserved.set(AMDGPU::NEG_HALF);
37 Reserved.set(AMDGPU::NEG_ONE);
38 Reserved.set(AMDGPU::PV_X);
39 Reserved.set(AMDGPU::ALU_LITERAL_X);
40 Reserved.set(AMDGPU::PREDICATE_BIT);
41 Reserved.set(AMDGPU::PRED_SEL_OFF)
[all...] |
| SIAssignInterpRegs.cpp | 21 #include "AMDGPU.h"
71 {false, {AMDGPU::PERSP_SAMPLE_I, AMDGPU::PERSP_SAMPLE_J}, 2},
72 {false, {AMDGPU::PERSP_CENTER_I, AMDGPU::PERSP_CENTER_J}, 2},
73 {false, {AMDGPU::PERSP_CENTROID_I, AMDGPU::PERSP_CENTROID_J}, 2},
74 {false, {AMDGPU::PERSP_I_W, AMDGPU::PERSP_J_W, AMDGPU::PERSP_1_W}, 3}
[all...] |
| SIRegisterInfo.cpp | 36 case AMDGPU::M0: return 124;
37 case AMDGPU::SREG_LIT_0: return 128;
46 case AMDGPU::GPRF32RegClassID:
47 return &AMDGPU::VReg_32RegClass;
57 case MVT::i32: return &AMDGPU::VReg_32RegClass;
|
| SIInstrInfo.cpp | 46 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
55 MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_IMM_I32), DebugLoc());
67 case AMDGPU::S_MOV_B32:
68 case AMDGPU::S_MOV_B64:
69 case AMDGPU::V_MOV_B32_e32:
70 case AMDGPU::V_MOV_B32_e64:
71 case AMDGPU::V_MOV_IMM_F32:
72 case AMDGPU::V_MOV_IMM_I32
[all...] |
| R600InstrInfo.cpp | 54 if (AMDGPU::R600_Reg128RegClass.contains(DestReg)
55 && AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
58 BuildMI(MBB, MI, DL, get(AMDGPU::MOV))
68 assert(!AMDGPU::R600_Reg128RegClass.contains(DestReg)
69 && !AMDGPU::R600_Reg128RegClass.contains(SrcReg));
71 BuildMI(MBB, MI, DL, get(AMDGPU::MOV), DestReg)
81 MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc());
83 MachineInstrBuilder(MI).addReg(AMDGPU::ALU_LITERAL_X);
92 return AMDGPU::SETE_INT;
101 case AMDGPU::MOV
[all...] |
| R600ISelLowering.cpp | 30 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
31 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
32 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
33 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
62 case AMDGPU::CLAMP_R600:
65 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
69 .addReg(AMDGPU::PRED_SEL_OFF);
73 case AMDGPU::FABS_R600:
76 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
80 .addReg(AMDGPU::PRED_SEL_OFF)
[all...] |
| Makefile | 40 $(call tablegen, -gen-register-info, AMDGPU.td, $@)
43 $(call tablegen, -gen-instr-info, AMDGPU.td, $@)
46 $(call tablegen, -gen-asm-writer, AMDGPU.td, $@)
49 $(call tablegen, -gen-dag-isel, AMDGPU.td, $@)
52 $(call tablegen, -gen-callingconv, AMDGPU.td, $@)
55 $(call tablegen, -gen-subtarget, AMDGPU.td, $@)
58 $(call tablegen, -gen-enhanced-disassembly-info, AMDGPU.td, $@)
61 $(call tablegen, -gen-tgt-intrinsic, AMDGPU.td, $@)
64 $(call tablegen, -gen-emitter, AMDGPU.td, $@)
67 $(call tablegen, -mc-emitter -gen-emitter, AMDGPU.td, $@
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 156 } else if (MI.getOpcode() == AMDGPU::RETURN ||
157 MI.getOpcode() == AMDGPU::BUNDLE ||
158 MI.getOpcode() == AMDGPU::KILL) {
162 case AMDGPU::RAT_WRITE_CACHELESS_eg:
169 case AMDGPU::VTX_READ_PARAM_i32_eg:
170 case AMDGPU::VTX_READ_PARAM_f32_eg:
171 case AMDGPU::VTX_READ_GLOBAL_i32_eg:
172 case AMDGPU::VTX_READ_GLOBAL_f32_eg:
173 case AMDGPU::VTX_READ_GLOBAL_v4i32_eg:
174 case AMDGPU::VTX_READ_GLOBAL_v4f32_eg
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 156 } else if (MI.getOpcode() == AMDGPU::RETURN ||
157 MI.getOpcode() == AMDGPU::BUNDLE ||
158 MI.getOpcode() == AMDGPU::KILL) {
162 case AMDGPU::RAT_WRITE_CACHELESS_eg:
169 case AMDGPU::VTX_READ_PARAM_i32_eg:
170 case AMDGPU::VTX_READ_PARAM_f32_eg:
171 case AMDGPU::VTX_READ_GLOBAL_i32_eg:
172 case AMDGPU::VTX_READ_GLOBAL_f32_eg:
173 case AMDGPU::VTX_READ_GLOBAL_v4i32_eg:
174 case AMDGPU::VTX_READ_GLOBAL_v4f32_eg
[all...] |
