| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIRegisterInfo.cpp | 53 MVT VT) const
57 case MVT::i32: return &AMDGPU::VReg_32RegClass;
|
| SIRegisterInfo.h | 48 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
|
| R600ISelLowering.cpp | 29 setOperationAction(ISD::MUL, MVT::i64, Expand);
30 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
31 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
32 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
33 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
36 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
38 setOperationAction(ISD::FSUB, MVT::f32, Expand);
40 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
41 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
43 setOperationAction(ISD::ROTL, MVT::i32, Custom)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIRegisterInfo.cpp | 53 MVT VT) const
57 case MVT::i32: return &AMDGPU::VReg_32RegClass;
|
| SIRegisterInfo.h | 48 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
|
| R600ISelLowering.cpp | 29 setOperationAction(ISD::MUL, MVT::i64, Expand);
30 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
31 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
32 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
33 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
36 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
38 setOperationAction(ISD::FSUB, MVT::f32, Expand);
40 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
41 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
43 setOperationAction(ISD::ROTL, MVT::i32, Custom)
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 154 virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const { return PointerTy; }
155 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
162 virtual MVT getVectorIdxTy() const {
206 /// BRCOND nodes. In the case of BRCOND the argument passed is MVT::Other
214 MVT::SimpleValueType getCmpLibcallReturnType() const;
244 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
257 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
264 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
280 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
287 LegalizeTypeAction getTypeAction(MVT VT) const
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 75 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
76 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
77 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
80 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal)
[all...] |
| PPCFastISel.cpp | 95 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
96 unsigned PPCMaterializeInt(const Constant *C, MVT VT);
117 unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
119 if (VT != MVT::f32 && VT != MVT::f64)
132 (VT == MVT::f32) ? 4 : 8, Align);
141 unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD;
245 unsigned PPCFastISel::PPCMaterializeInt(const Constant *C, MVT VT) {
247 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMCallingConv.h | 28 static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
58 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
64 if (LocVT == MVT::v2f64 &&
71 static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
112 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
118 if (LocVT == MVT::v2f64 &
[all...] |
| ARMISelDAGToDAG.cpp | 85 return CurDAG->getTargetConstant(Imm, MVT::i32);
291 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
404 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32,
406 CurDAG->getConstant(Srl_imm+TZ, MVT::i32));
407 N1 = CurDAG->getNode(ISD::AND, SDLoc(N1), MVT::i32,
408 Srl, CurDAG->getConstant(And_imm, MVT::i32));
409 N1 = CurDAG->getNode(ISD::SHL, SDLoc(N1), MVT::i32,
410 N1, CurDAG->getConstant(TZ, MVT::i32));
495 MVT::i32);
522 MVT::i32)
[all...] |
| ARMISelLowering.cpp | 93 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
94 MVT PromotedBitwiseVT) {
103 MVT ElemTy = VT.getVectorElementType();
104 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
108 if (ElemTy == MVT::i32) {
152 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
154 addTypeForNEON(VT, MVT::f64, MVT::v2i32)
[all...] |
| ARMFastISel.cpp | 139 unsigned FastEmitInst_extractsubreg(MVT RetVT,
179 bool isTypeLegal(Type *Ty, MVT &VT);
180 bool isLoadTypeLegal(Type *Ty, MVT &VT);
183 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
186 bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
189 void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
193 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
194 unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
195 unsigned ARMMaterializeInt(const Constant *C, MVT VT)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86SelectionDAGInfo.cpp | 95 AVT = MVT::i16;
100 AVT = MVT::i32;
105 AVT = MVT::i64;
111 AVT = MVT::i8;
117 if (AVT.bitsGT(MVT::i8)) {
127 AVT = MVT::i8;
142 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
151 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
152 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 122 return CurDAG->getTargetConstant(bitPos, MVT::i32);
150 return CurDAG->getTargetConstant( - Imm, MVT::i32);
158 return CurDAG->getTargetConstant(Imm - 1, MVT::i8);
163 return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
169 return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
365 if (MemType == MVT::i64 && isShiftedInt<11,3>(Offset)) {
368 if (MemType == MVT::i32 && isShiftedInt<11,2>(Offset)) {
371 if (MemType == MVT::i16 && isShiftedInt<11,1>(Offset)) {
374 if (MemType == MVT::i8 && isInt<11>(Offset)) {
397 MVT PointerTy = getTargetLowering()->getPointerTy()
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 68 DecodePALIGNRMask(MVT::v16i8,
78 DecodePALIGNRMask(MVT::v32i8,
90 DecodePSHUFMask(MVT::v4i32, MI->getOperand(MI->getNumOperands()-1).getImm(),
98 DecodePSHUFMask(MVT::v8i32, MI->getOperand(MI->getNumOperands()-1).getImm(),
110 DecodePSHUFHWMask(MVT::v8i16,
119 DecodePSHUFHWMask(MVT::v16i16,
130 DecodePSHUFLWMask(MVT::v8i16,
139 DecodePSHUFLWMask(MVT::v16i16,
152 DecodeUNPCKHMask(MVT::v16i8, ShuffleMask);
160 DecodeUNPCKHMask(MVT::v32i8, ShuffleMask)
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIRegisterInfo.h | 43 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
|
| R600ISelLowering.cpp | 32 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
33 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
34 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
35 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
36 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
37 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass);
41 setOperationAction(ISD::FADD, MVT::v4f32, Expand);
42 setOperationAction(ISD::FADD, MVT::v2f32, Expand);
43 setOperationAction(ISD::FMUL, MVT::v4f32, Expand);
44 setOperationAction(ISD::FMUL, MVT::v2f32, Expand)
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.h | 51 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
53 MVT::SimpleValueType getValueType(Record *Rec);
55 std::string getName(MVT::SimpleValueType T);
56 std::string getEnumName(MVT::SimpleValueType T);
71 mutable SmallVector<MVT::SimpleValueType, 8> LegalValueTypes;
130 std::vector<MVT::SimpleValueType> getRegisterVTs(Record *R) const;
132 ArrayRef<MVT::SimpleValueType> getLegalValueTypes() const {
139 bool isLegalValueType(MVT::SimpleValueType VT) const {
140 ArrayRef<MVT::SimpleValueType> LegalVTs = getLegalValueTypes();
191 MVT::SimpleValueType Ty
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 226 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
227 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
228 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
231 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
232 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
238 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
241 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
242 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 67 addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
68 addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
83 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
84 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
86 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
87 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
88 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
90 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
93 setTruncStoreAction(MVT::i16, MVT::i8, Expand)
[all...] |
| MSP430ISelDAGToDAG.cpp | 268 MVT::i16, AM.Disp,
271 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16,
274 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/);
276 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i16, 0/*AM.SymbolFlags*/);
278 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, 0,
281 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i16);
311 case MVT::i8:
317 case MVT::i16:
335 MVT VT = LD->getMemoryVT().getSimpleVT();
339 case MVT::i8
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 62 UImm12 = CurDAG->getTargetConstant(CN->getZExtValue() / MemSize, MVT::i64);
77 Shift = CurDAG->getTargetConstant(LogShift, MVT::i32);
143 FixedPos = CurDAG->getTargetConstant(64 - FBits, MVT::i32);
173 Dummy = CurDAG->getTargetConstant(0, MVT::i32);
187 Imm = CurDAG->getTargetConstant(Bits, MVT::i32);
212 MOVType = MVT::i32;
220 CurDAG->getTargetConstant(LogicalBits, MVT::i32));
228 CurDAG->getTargetConstant(UImm16, MVT::i32),
229 CurDAG->getTargetConstant(Shift, MVT::i32));
233 MVT::i64, MVT::i32, MVT::Other
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 79 Offset = CurDAG->getTargetConstant(0, MVT::i32);
97 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
113 Offset = CurDAG->getTargetConstant(0, MVT::i32);
153 if (N->getValueType(0) == MVT::i64)
162 TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS,
163 CurDAG->getTargetConstant(31, MVT::i32)), 0);
165 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
167 TopPart = SDValue(CurDAG->getMachineNode(SP::WRYrr, dl, MVT::Glue, TopPart,
168 CurDAG->getRegister(SP::G0, MVT::i32)), 0);
172 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.h | 90 bool isTypeSupportedInIntrinsic(MVT VT) const;
107 return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
108 return MVT::i1;
113 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
141 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
149 EVT = MVT::i32) const;
|
