1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the TargetLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetLowering.h" 15 #include "llvm/ADT/BitVector.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/CodeGen/Analysis.h" 18 #include "llvm/CodeGen/MachineFrameInfo.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 #include "llvm/CodeGen/MachineJumpTableInfo.h" 21 #include "llvm/CodeGen/SelectionDAG.h" 22 #include "llvm/IR/DataLayout.h" 23 #include "llvm/IR/DerivedTypes.h" 24 #include "llvm/IR/GlobalVariable.h" 25 #include "llvm/IR/LLVMContext.h" 26 #include "llvm/MC/MCAsmInfo.h" 27 #include "llvm/MC/MCExpr.h" 28 #include "llvm/Support/CommandLine.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/MathExtras.h" 31 #include "llvm/Target/TargetLoweringObjectFile.h" 32 #include "llvm/Target/TargetMachine.h" 33 #include "llvm/Target/TargetRegisterInfo.h" 34 #include "llvm/Target/TargetSubtargetInfo.h" 35 #include <cctype> 36 using namespace llvm; 37 38 /// NOTE: The TargetMachine owns TLOF. 39 TargetLowering::TargetLowering(const TargetMachine &tm) 40 : TargetLoweringBase(tm) {} 41 42 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 43 return nullptr; 44 } 45 46 /// Check whether a given call node is in tail position within its function. If 47 /// so, it sets Chain to the input chain of the tail call. 48 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, 49 SDValue &Chain) const { 50 const Function *F = DAG.getMachineFunction().getFunction(); 51 52 // Conservatively require the attributes of the call to match those of 53 // the return. Ignore noalias because it doesn't affect the call sequence. 54 AttributeSet CallerAttrs = F->getAttributes(); 55 if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex) 56 .removeAttribute(Attribute::NoAlias).hasAttributes()) 57 return false; 58 59 // It's not safe to eliminate the sign / zero extension of the return value. 60 if (CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt) || 61 CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 62 return false; 63 64 // Check if the only use is a function return node. 65 return isUsedByReturnOnly(Node, Chain); 66 } 67 68 /// \brief Set CallLoweringInfo attribute flags based on a call instruction 69 /// and called function attributes. 70 void TargetLowering::ArgListEntry::setAttributes(ImmutableCallSite *CS, 71 unsigned AttrIdx) { 72 isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt); 73 isZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt); 74 isInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg); 75 isSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet); 76 isNest = CS->paramHasAttr(AttrIdx, Attribute::Nest); 77 isByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal); 78 isInAlloca = CS->paramHasAttr(AttrIdx, Attribute::InAlloca); 79 isReturned = CS->paramHasAttr(AttrIdx, Attribute::Returned); 80 Alignment = CS->getParamAlignment(AttrIdx); 81 } 82 83 /// Generate a libcall taking the given operands as arguments and returning a 84 /// result of type RetVT. 85 std::pair<SDValue, SDValue> 86 TargetLowering::makeLibCall(SelectionDAG &DAG, 87 RTLIB::Libcall LC, EVT RetVT, 88 const SDValue *Ops, unsigned NumOps, 89 bool isSigned, SDLoc dl, 90 bool doesNotReturn, 91 bool isReturnValueUsed) const { 92 TargetLowering::ArgListTy Args; 93 Args.reserve(NumOps); 94 95 TargetLowering::ArgListEntry Entry; 96 for (unsigned i = 0; i != NumOps; ++i) { 97 Entry.Node = Ops[i]; 98 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext()); 99 Entry.isSExt = shouldSignExtendTypeInLibCall(Ops[i].getValueType(), isSigned); 100 Entry.isZExt = !shouldSignExtendTypeInLibCall(Ops[i].getValueType(), isSigned); 101 Args.push_back(Entry); 102 } 103 if (LC == RTLIB::UNKNOWN_LIBCALL) 104 report_fatal_error("Unsupported library call operation!"); 105 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), getPointerTy()); 106 107 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); 108 TargetLowering::CallLoweringInfo CLI(DAG); 109 bool signExtend = shouldSignExtendTypeInLibCall(RetVT, isSigned); 110 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode()) 111 .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0) 112 .setNoReturn(doesNotReturn).setDiscardResult(!isReturnValueUsed) 113 .setSExtResult(signExtend).setZExtResult(!signExtend); 114 return LowerCallTo(CLI); 115 } 116 117 118 /// SoftenSetCCOperands - Soften the operands of a comparison. This code is 119 /// shared among BR_CC, SELECT_CC, and SETCC handlers. 120 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT, 121 SDValue &NewLHS, SDValue &NewRHS, 122 ISD::CondCode &CCCode, 123 SDLoc dl) const { 124 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128) 125 && "Unsupported setcc type!"); 126 127 // Expand into one or more soft-fp libcall(s). 128 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; 129 switch (CCCode) { 130 case ISD::SETEQ: 131 case ISD::SETOEQ: 132 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : 133 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128; 134 break; 135 case ISD::SETNE: 136 case ISD::SETUNE: 137 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : 138 (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128; 139 break; 140 case ISD::SETGE: 141 case ISD::SETOGE: 142 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : 143 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128; 144 break; 145 case ISD::SETLT: 146 case ISD::SETOLT: 147 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : 148 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128; 149 break; 150 case ISD::SETLE: 151 case ISD::SETOLE: 152 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : 153 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128; 154 break; 155 case ISD::SETGT: 156 case ISD::SETOGT: 157 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : 158 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128; 159 break; 160 case ISD::SETUO: 161 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : 162 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128; 163 break; 164 case ISD::SETO: 165 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : 166 (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128; 167 break; 168 default: 169 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : 170 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128; 171 switch (CCCode) { 172 case ISD::SETONE: 173 // SETONE = SETOLT | SETOGT 174 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : 175 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128; 176 // Fallthrough 177 case ISD::SETUGT: 178 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : 179 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128; 180 break; 181 case ISD::SETUGE: 182 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : 183 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128; 184 break; 185 case ISD::SETULT: 186 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : 187 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128; 188 break; 189 case ISD::SETULE: 190 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : 191 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128; 192 break; 193 case ISD::SETUEQ: 194 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : 195 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128; 196 break; 197 default: llvm_unreachable("Do not know how to soften this setcc!"); 198 } 199 } 200 201 // Use the target specific return value for comparions lib calls. 202 EVT RetVT = getCmpLibcallReturnType(); 203 SDValue Ops[2] = { NewLHS, NewRHS }; 204 NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/, 205 dl).first; 206 NewRHS = DAG.getConstant(0, RetVT); 207 CCCode = getCmpLibcallCC(LC1); 208 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 209 SDValue Tmp = DAG.getNode(ISD::SETCC, dl, 210 getSetCCResultType(*DAG.getContext(), RetVT), 211 NewLHS, NewRHS, DAG.getCondCode(CCCode)); 212 NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/, 213 dl).first; 214 NewLHS = DAG.getNode(ISD::SETCC, dl, 215 getSetCCResultType(*DAG.getContext(), RetVT), NewLHS, 216 NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2))); 217 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS); 218 NewRHS = SDValue(); 219 } 220 } 221 222 /// getJumpTableEncoding - Return the entry encoding for a jump table in the 223 /// current function. The returned value is a member of the 224 /// MachineJumpTableInfo::JTEntryKind enum. 225 unsigned TargetLowering::getJumpTableEncoding() const { 226 // In non-pic modes, just use the address of a block. 227 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 228 return MachineJumpTableInfo::EK_BlockAddress; 229 230 // In PIC mode, if the target supports a GPRel32 directive, use it. 231 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr) 232 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 233 234 // Otherwise, use a label difference. 235 return MachineJumpTableInfo::EK_LabelDifference32; 236 } 237 238 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 239 SelectionDAG &DAG) const { 240 // If our PIC model is GP relative, use the global offset table as the base. 241 unsigned JTEncoding = getJumpTableEncoding(); 242 243 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) || 244 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress)) 245 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0)); 246 247 return Table; 248 } 249 250 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 251 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 252 /// MCExpr. 253 const MCExpr * 254 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 255 unsigned JTI,MCContext &Ctx) const{ 256 // The normal PIC reloc base is the label at the start of the jump table. 257 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 258 } 259 260 bool 261 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 262 // Assume that everything is safe in static mode. 263 if (getTargetMachine().getRelocationModel() == Reloc::Static) 264 return true; 265 266 // In dynamic-no-pic mode, assume that known defined values are safe. 267 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 268 GA && 269 !GA->getGlobal()->isDeclaration() && 270 !GA->getGlobal()->isWeakForLinker()) 271 return true; 272 273 // Otherwise assume nothing is safe. 274 return false; 275 } 276 277 //===----------------------------------------------------------------------===// 278 // Optimization Methods 279 //===----------------------------------------------------------------------===// 280 281 /// ShrinkDemandedConstant - Check to see if the specified operand of the 282 /// specified instruction is a constant integer. If so, check to see if there 283 /// are any bits set in the constant that are not demanded. If so, shrink the 284 /// constant and return true. 285 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 286 const APInt &Demanded) { 287 SDLoc dl(Op); 288 289 // FIXME: ISD::SELECT, ISD::SELECT_CC 290 switch (Op.getOpcode()) { 291 default: break; 292 case ISD::XOR: 293 case ISD::AND: 294 case ISD::OR: { 295 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 296 if (!C) return false; 297 298 if (Op.getOpcode() == ISD::XOR && 299 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 300 return false; 301 302 // if we can expand it to have all bits set, do it 303 if (C->getAPIntValue().intersects(~Demanded)) { 304 EVT VT = Op.getValueType(); 305 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 306 DAG.getConstant(Demanded & 307 C->getAPIntValue(), 308 VT)); 309 return CombineTo(Op, New); 310 } 311 312 break; 313 } 314 } 315 316 return false; 317 } 318 319 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 320 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 321 /// cast, but it could be generalized for targets with other types of 322 /// implicit widening casts. 323 bool 324 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 325 unsigned BitWidth, 326 const APInt &Demanded, 327 SDLoc dl) { 328 assert(Op.getNumOperands() == 2 && 329 "ShrinkDemandedOp only supports binary operators!"); 330 assert(Op.getNode()->getNumValues() == 1 && 331 "ShrinkDemandedOp only supports nodes with one result!"); 332 333 // Early return, as this function cannot handle vector types. 334 if (Op.getValueType().isVector()) 335 return false; 336 337 // Don't do this if the node has another user, which may require the 338 // full value. 339 if (!Op.getNode()->hasOneUse()) 340 return false; 341 342 // Search for the smallest integer type with free casts to and from 343 // Op's type. For expedience, just check power-of-2 integer types. 344 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 345 unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros(); 346 unsigned SmallVTBits = DemandedSize; 347 if (!isPowerOf2_32(SmallVTBits)) 348 SmallVTBits = NextPowerOf2(SmallVTBits); 349 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 350 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 351 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 352 TLI.isZExtFree(SmallVT, Op.getValueType())) { 353 // We found a type with free casts. 354 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 355 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 356 Op.getNode()->getOperand(0)), 357 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 358 Op.getNode()->getOperand(1))); 359 bool NeedZext = DemandedSize > SmallVTBits; 360 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND, 361 dl, Op.getValueType(), X); 362 return CombineTo(Op, Z); 363 } 364 } 365 return false; 366 } 367 368 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 369 /// DemandedMask bits of the result of Op are ever used downstream. If we can 370 /// use this information to simplify Op, create a new simplified DAG node and 371 /// return true, returning the original and new nodes in Old and New. Otherwise, 372 /// analyze the expression and return a mask of KnownOne and KnownZero bits for 373 /// the expression (used to simplify the caller). The KnownZero/One bits may 374 /// only be accurate for those bits in the DemandedMask. 375 bool TargetLowering::SimplifyDemandedBits(SDValue Op, 376 const APInt &DemandedMask, 377 APInt &KnownZero, 378 APInt &KnownOne, 379 TargetLoweringOpt &TLO, 380 unsigned Depth) const { 381 unsigned BitWidth = DemandedMask.getBitWidth(); 382 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 383 "Mask size mismatches value type size!"); 384 APInt NewMask = DemandedMask; 385 SDLoc dl(Op); 386 387 // Don't know anything. 388 KnownZero = KnownOne = APInt(BitWidth, 0); 389 390 // Other users may use these bits. 391 if (!Op.getNode()->hasOneUse()) { 392 if (Depth != 0) { 393 // If not at the root, Just compute the KnownZero/KnownOne bits to 394 // simplify things downstream. 395 TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth); 396 return false; 397 } 398 // If this is the root being simplified, allow it to have multiple uses, 399 // just set the NewMask to all bits. 400 NewMask = APInt::getAllOnesValue(BitWidth); 401 } else if (DemandedMask == 0) { 402 // Not demanding any bits from Op. 403 if (Op.getOpcode() != ISD::UNDEF) 404 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 405 return false; 406 } else if (Depth == 6) { // Limit search depth. 407 return false; 408 } 409 410 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 411 switch (Op.getOpcode()) { 412 case ISD::Constant: 413 // We know all of the bits for a constant! 414 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue(); 415 KnownZero = ~KnownOne; 416 return false; // Don't fall through, will infinitely loop. 417 case ISD::AND: 418 // If the RHS is a constant, check to see if the LHS would be zero without 419 // using the bits from the RHS. Below, we use knowledge about the RHS to 420 // simplify the LHS, here we're using information from the LHS to simplify 421 // the RHS. 422 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 423 APInt LHSZero, LHSOne; 424 // Do not increment Depth here; that can cause an infinite loop. 425 TLO.DAG.computeKnownBits(Op.getOperand(0), LHSZero, LHSOne, Depth); 426 // If the LHS already has zeros where RHSC does, this and is dead. 427 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 428 return TLO.CombineTo(Op, Op.getOperand(0)); 429 // If any of the set bits in the RHS are known zero on the LHS, shrink 430 // the constant. 431 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 432 return true; 433 } 434 435 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 436 KnownOne, TLO, Depth+1)) 437 return true; 438 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 439 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 440 KnownZero2, KnownOne2, TLO, Depth+1)) 441 return true; 442 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 443 444 // If all of the demanded bits are known one on one side, return the other. 445 // These bits cannot contribute to the result of the 'and'. 446 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 447 return TLO.CombineTo(Op, Op.getOperand(0)); 448 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 449 return TLO.CombineTo(Op, Op.getOperand(1)); 450 // If all of the demanded bits in the inputs are known zeros, return zero. 451 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 452 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 453 // If the RHS is a constant, see if we can simplify it. 454 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 455 return true; 456 // If the operation can be done in a smaller type, do so. 457 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 458 return true; 459 460 // Output known-1 bits are only known if set in both the LHS & RHS. 461 KnownOne &= KnownOne2; 462 // Output known-0 are known to be clear if zero in either the LHS | RHS. 463 KnownZero |= KnownZero2; 464 break; 465 case ISD::OR: 466 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 467 KnownOne, TLO, Depth+1)) 468 return true; 469 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 470 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 471 KnownZero2, KnownOne2, TLO, Depth+1)) 472 return true; 473 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 474 475 // If all of the demanded bits are known zero on one side, return the other. 476 // These bits cannot contribute to the result of the 'or'. 477 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 478 return TLO.CombineTo(Op, Op.getOperand(0)); 479 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 480 return TLO.CombineTo(Op, Op.getOperand(1)); 481 // If all of the potentially set bits on one side are known to be set on 482 // the other side, just use the 'other' side. 483 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 484 return TLO.CombineTo(Op, Op.getOperand(0)); 485 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 486 return TLO.CombineTo(Op, Op.getOperand(1)); 487 // If the RHS is a constant, see if we can simplify it. 488 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 489 return true; 490 // If the operation can be done in a smaller type, do so. 491 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 492 return true; 493 494 // Output known-0 bits are only known if clear in both the LHS & RHS. 495 KnownZero &= KnownZero2; 496 // Output known-1 are known to be set if set in either the LHS | RHS. 497 KnownOne |= KnownOne2; 498 break; 499 case ISD::XOR: 500 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 501 KnownOne, TLO, Depth+1)) 502 return true; 503 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 504 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 505 KnownOne2, TLO, Depth+1)) 506 return true; 507 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 508 509 // If all of the demanded bits are known zero on one side, return the other. 510 // These bits cannot contribute to the result of the 'xor'. 511 if ((KnownZero & NewMask) == NewMask) 512 return TLO.CombineTo(Op, Op.getOperand(0)); 513 if ((KnownZero2 & NewMask) == NewMask) 514 return TLO.CombineTo(Op, Op.getOperand(1)); 515 // If the operation can be done in a smaller type, do so. 516 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 517 return true; 518 519 // If all of the unknown bits are known to be zero on one side or the other 520 // (but not both) turn this into an *inclusive* or. 521 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 522 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 523 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 524 Op.getOperand(0), 525 Op.getOperand(1))); 526 527 // Output known-0 bits are known if clear or set in both the LHS & RHS. 528 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 529 // Output known-1 are known to be set if set in only one of the LHS, RHS. 530 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 531 532 // If all of the demanded bits on one side are known, and all of the set 533 // bits on that side are also known to be set on the other side, turn this 534 // into an AND, as we know the bits will be cleared. 535 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 536 // NB: it is okay if more bits are known than are requested 537 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side 538 if (KnownOne == KnownOne2) { // set bits are the same on both sides 539 EVT VT = Op.getValueType(); 540 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 541 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 542 Op.getOperand(0), ANDC)); 543 } 544 } 545 546 // If the RHS is a constant, see if we can simplify it. 547 // for XOR, we prefer to force bits to 1 if they will make a -1. 548 // if we can't force bits, try to shrink constant 549 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 550 APInt Expanded = C->getAPIntValue() | (~NewMask); 551 // if we can expand it to have all bits set, do it 552 if (Expanded.isAllOnesValue()) { 553 if (Expanded != C->getAPIntValue()) { 554 EVT VT = Op.getValueType(); 555 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 556 TLO.DAG.getConstant(Expanded, VT)); 557 return TLO.CombineTo(Op, New); 558 } 559 // if it already has all the bits set, nothing to change 560 // but don't shrink either! 561 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 562 return true; 563 } 564 } 565 566 KnownZero = KnownZeroOut; 567 KnownOne = KnownOneOut; 568 break; 569 case ISD::SELECT: 570 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 571 KnownOne, TLO, Depth+1)) 572 return true; 573 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 574 KnownOne2, TLO, Depth+1)) 575 return true; 576 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 577 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 578 579 // If the operands are constants, see if we can simplify them. 580 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 581 return true; 582 583 // Only known if known in both the LHS and RHS. 584 KnownOne &= KnownOne2; 585 KnownZero &= KnownZero2; 586 break; 587 case ISD::SELECT_CC: 588 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 589 KnownOne, TLO, Depth+1)) 590 return true; 591 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 592 KnownOne2, TLO, Depth+1)) 593 return true; 594 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 595 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 596 597 // If the operands are constants, see if we can simplify them. 598 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 599 return true; 600 601 // Only known if known in both the LHS and RHS. 602 KnownOne &= KnownOne2; 603 KnownZero &= KnownZero2; 604 break; 605 case ISD::SHL: 606 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 607 unsigned ShAmt = SA->getZExtValue(); 608 SDValue InOp = Op.getOperand(0); 609 610 // If the shift count is an invalid immediate, don't do anything. 611 if (ShAmt >= BitWidth) 612 break; 613 614 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 615 // single shift. We can do this if the bottom bits (which are shifted 616 // out) are never demanded. 617 if (InOp.getOpcode() == ISD::SRL && 618 isa<ConstantSDNode>(InOp.getOperand(1))) { 619 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 620 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 621 unsigned Opc = ISD::SHL; 622 int Diff = ShAmt-C1; 623 if (Diff < 0) { 624 Diff = -Diff; 625 Opc = ISD::SRL; 626 } 627 628 SDValue NewSA = 629 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 630 EVT VT = Op.getValueType(); 631 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 632 InOp.getOperand(0), NewSA)); 633 } 634 } 635 636 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt), 637 KnownZero, KnownOne, TLO, Depth+1)) 638 return true; 639 640 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits 641 // are not demanded. This will likely allow the anyext to be folded away. 642 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) { 643 SDValue InnerOp = InOp.getNode()->getOperand(0); 644 EVT InnerVT = InnerOp.getValueType(); 645 unsigned InnerBits = InnerVT.getSizeInBits(); 646 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 && 647 isTypeDesirableForOp(ISD::SHL, InnerVT)) { 648 EVT ShTy = getShiftAmountTy(InnerVT); 649 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) 650 ShTy = InnerVT; 651 SDValue NarrowShl = 652 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, 653 TLO.DAG.getConstant(ShAmt, ShTy)); 654 return 655 TLO.CombineTo(Op, 656 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), 657 NarrowShl)); 658 } 659 // Repeat the SHL optimization above in cases where an extension 660 // intervenes: (shl (anyext (shr x, c1)), c2) to 661 // (shl (anyext x), c2-c1). This requires that the bottom c1 bits 662 // aren't demanded (as above) and that the shifted upper c1 bits of 663 // x aren't demanded. 664 if (InOp.hasOneUse() && 665 InnerOp.getOpcode() == ISD::SRL && 666 InnerOp.hasOneUse() && 667 isa<ConstantSDNode>(InnerOp.getOperand(1))) { 668 uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1)) 669 ->getZExtValue(); 670 if (InnerShAmt < ShAmt && 671 InnerShAmt < InnerBits && 672 NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 && 673 NewMask.trunc(ShAmt) == 0) { 674 SDValue NewSA = 675 TLO.DAG.getConstant(ShAmt - InnerShAmt, 676 Op.getOperand(1).getValueType()); 677 EVT VT = Op.getValueType(); 678 SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, 679 InnerOp.getOperand(0)); 680 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT, 681 NewExt, NewSA)); 682 } 683 } 684 } 685 686 KnownZero <<= SA->getZExtValue(); 687 KnownOne <<= SA->getZExtValue(); 688 // low bits known zero. 689 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 690 } 691 break; 692 case ISD::SRL: 693 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 694 EVT VT = Op.getValueType(); 695 unsigned ShAmt = SA->getZExtValue(); 696 unsigned VTSize = VT.getSizeInBits(); 697 SDValue InOp = Op.getOperand(0); 698 699 // If the shift count is an invalid immediate, don't do anything. 700 if (ShAmt >= BitWidth) 701 break; 702 703 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 704 // single shift. We can do this if the top bits (which are shifted out) 705 // are never demanded. 706 if (InOp.getOpcode() == ISD::SHL && 707 isa<ConstantSDNode>(InOp.getOperand(1))) { 708 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 709 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 710 unsigned Opc = ISD::SRL; 711 int Diff = ShAmt-C1; 712 if (Diff < 0) { 713 Diff = -Diff; 714 Opc = ISD::SHL; 715 } 716 717 SDValue NewSA = 718 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 719 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 720 InOp.getOperand(0), NewSA)); 721 } 722 } 723 724 // Compute the new bits that are at the top now. 725 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 726 KnownZero, KnownOne, TLO, Depth+1)) 727 return true; 728 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 729 KnownZero = KnownZero.lshr(ShAmt); 730 KnownOne = KnownOne.lshr(ShAmt); 731 732 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 733 KnownZero |= HighBits; // High bits known zero. 734 } 735 break; 736 case ISD::SRA: 737 // If this is an arithmetic shift right and only the low-bit is set, we can 738 // always convert this into a logical shr, even if the shift amount is 739 // variable. The low bit of the shift cannot be an input sign bit unless 740 // the shift amount is >= the size of the datatype, which is undefined. 741 if (NewMask == 1) 742 return TLO.CombineTo(Op, 743 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 744 Op.getOperand(0), Op.getOperand(1))); 745 746 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 747 EVT VT = Op.getValueType(); 748 unsigned ShAmt = SA->getZExtValue(); 749 750 // If the shift count is an invalid immediate, don't do anything. 751 if (ShAmt >= BitWidth) 752 break; 753 754 APInt InDemandedMask = (NewMask << ShAmt); 755 756 // If any of the demanded bits are produced by the sign extension, we also 757 // demand the input sign bit. 758 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 759 if (HighBits.intersects(NewMask)) 760 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 761 762 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 763 KnownZero, KnownOne, TLO, Depth+1)) 764 return true; 765 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 766 KnownZero = KnownZero.lshr(ShAmt); 767 KnownOne = KnownOne.lshr(ShAmt); 768 769 // Handle the sign bit, adjusted to where it is now in the mask. 770 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 771 772 // If the input sign bit is known to be zero, or if none of the top bits 773 // are demanded, turn this into an unsigned shift right. 774 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) 775 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 776 Op.getOperand(0), 777 Op.getOperand(1))); 778 779 int Log2 = NewMask.exactLogBase2(); 780 if (Log2 >= 0) { 781 // The bit must come from the sign. 782 SDValue NewSA = 783 TLO.DAG.getConstant(BitWidth - 1 - Log2, 784 Op.getOperand(1).getValueType()); 785 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 786 Op.getOperand(0), NewSA)); 787 } 788 789 if (KnownOne.intersects(SignBit)) 790 // New bits are known one. 791 KnownOne |= HighBits; 792 } 793 break; 794 case ISD::SIGN_EXTEND_INREG: { 795 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 796 797 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1); 798 // If we only care about the highest bit, don't bother shifting right. 799 if (MsbMask == NewMask) { 800 unsigned ShAmt = ExVT.getScalarType().getSizeInBits(); 801 SDValue InOp = Op.getOperand(0); 802 unsigned VTBits = Op->getValueType(0).getScalarType().getSizeInBits(); 803 bool AlreadySignExtended = 804 TLO.DAG.ComputeNumSignBits(InOp) >= VTBits-ShAmt+1; 805 // However if the input is already sign extended we expect the sign 806 // extension to be dropped altogether later and do not simplify. 807 if (!AlreadySignExtended) { 808 // Compute the correct shift amount type, which must be getShiftAmountTy 809 // for scalar types after legalization. 810 EVT ShiftAmtTy = Op.getValueType(); 811 if (TLO.LegalTypes() && !ShiftAmtTy.isVector()) 812 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy); 813 814 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy); 815 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 816 Op.getValueType(), InOp, 817 ShiftAmt)); 818 } 819 } 820 821 // Sign extension. Compute the demanded bits in the result that are not 822 // present in the input. 823 APInt NewBits = 824 APInt::getHighBitsSet(BitWidth, 825 BitWidth - ExVT.getScalarType().getSizeInBits()); 826 827 // If none of the extended bits are demanded, eliminate the sextinreg. 828 if ((NewBits & NewMask) == 0) 829 return TLO.CombineTo(Op, Op.getOperand(0)); 830 831 APInt InSignBit = 832 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth); 833 APInt InputDemandedBits = 834 APInt::getLowBitsSet(BitWidth, 835 ExVT.getScalarType().getSizeInBits()) & 836 NewMask; 837 838 // Since the sign extended bits are demanded, we know that the sign 839 // bit is demanded. 840 InputDemandedBits |= InSignBit; 841 842 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 843 KnownZero, KnownOne, TLO, Depth+1)) 844 return true; 845 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 846 847 // If the sign bit of the input is known set or clear, then we know the 848 // top bits of the result. 849 850 // If the input sign bit is known zero, convert this into a zero extension. 851 if (KnownZero.intersects(InSignBit)) 852 return TLO.CombineTo(Op, 853 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT)); 854 855 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 856 KnownOne |= NewBits; 857 KnownZero &= ~NewBits; 858 } else { // Input sign bit unknown 859 KnownZero &= ~NewBits; 860 KnownOne &= ~NewBits; 861 } 862 break; 863 } 864 case ISD::BUILD_PAIR: { 865 EVT HalfVT = Op.getOperand(0).getValueType(); 866 unsigned HalfBitWidth = HalfVT.getScalarSizeInBits(); 867 868 APInt MaskLo = NewMask.getLoBits(HalfBitWidth).trunc(HalfBitWidth); 869 APInt MaskHi = NewMask.getHiBits(HalfBitWidth).trunc(HalfBitWidth); 870 871 APInt KnownZeroLo, KnownOneLo; 872 APInt KnownZeroHi, KnownOneHi; 873 874 if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownZeroLo, 875 KnownOneLo, TLO, Depth + 1)) 876 return true; 877 878 if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownZeroHi, 879 KnownOneHi, TLO, Depth + 1)) 880 return true; 881 882 KnownZero = KnownZeroLo.zext(BitWidth) | 883 KnownZeroHi.zext(BitWidth).shl(HalfBitWidth); 884 885 KnownOne = KnownOneLo.zext(BitWidth) | 886 KnownOneHi.zext(BitWidth).shl(HalfBitWidth); 887 break; 888 } 889 case ISD::ZERO_EXTEND: { 890 unsigned OperandBitWidth = 891 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 892 APInt InMask = NewMask.trunc(OperandBitWidth); 893 894 // If none of the top bits are demanded, convert this into an any_extend. 895 APInt NewBits = 896 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 897 if (!NewBits.intersects(NewMask)) 898 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 899 Op.getValueType(), 900 Op.getOperand(0))); 901 902 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 903 KnownZero, KnownOne, TLO, Depth+1)) 904 return true; 905 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 906 KnownZero = KnownZero.zext(BitWidth); 907 KnownOne = KnownOne.zext(BitWidth); 908 KnownZero |= NewBits; 909 break; 910 } 911 case ISD::SIGN_EXTEND: { 912 EVT InVT = Op.getOperand(0).getValueType(); 913 unsigned InBits = InVT.getScalarType().getSizeInBits(); 914 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 915 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 916 APInt NewBits = ~InMask & NewMask; 917 918 // If none of the top bits are demanded, convert this into an any_extend. 919 if (NewBits == 0) 920 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 921 Op.getValueType(), 922 Op.getOperand(0))); 923 924 // Since some of the sign extended bits are demanded, we know that the sign 925 // bit is demanded. 926 APInt InDemandedBits = InMask & NewMask; 927 InDemandedBits |= InSignBit; 928 InDemandedBits = InDemandedBits.trunc(InBits); 929 930 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 931 KnownOne, TLO, Depth+1)) 932 return true; 933 KnownZero = KnownZero.zext(BitWidth); 934 KnownOne = KnownOne.zext(BitWidth); 935 936 // If the sign bit is known zero, convert this to a zero extend. 937 if (KnownZero.intersects(InSignBit)) 938 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 939 Op.getValueType(), 940 Op.getOperand(0))); 941 942 // If the sign bit is known one, the top bits match. 943 if (KnownOne.intersects(InSignBit)) { 944 KnownOne |= NewBits; 945 assert((KnownZero & NewBits) == 0); 946 } else { // Otherwise, top bits aren't known. 947 assert((KnownOne & NewBits) == 0); 948 assert((KnownZero & NewBits) == 0); 949 } 950 break; 951 } 952 case ISD::ANY_EXTEND: { 953 unsigned OperandBitWidth = 954 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 955 APInt InMask = NewMask.trunc(OperandBitWidth); 956 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 957 KnownZero, KnownOne, TLO, Depth+1)) 958 return true; 959 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 960 KnownZero = KnownZero.zext(BitWidth); 961 KnownOne = KnownOne.zext(BitWidth); 962 break; 963 } 964 case ISD::TRUNCATE: { 965 // Simplify the input, using demanded bit information, and compute the known 966 // zero/one bits live out. 967 unsigned OperandBitWidth = 968 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 969 APInt TruncMask = NewMask.zext(OperandBitWidth); 970 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 971 KnownZero, KnownOne, TLO, Depth+1)) 972 return true; 973 KnownZero = KnownZero.trunc(BitWidth); 974 KnownOne = KnownOne.trunc(BitWidth); 975 976 // If the input is only used by this truncate, see if we can shrink it based 977 // on the known demanded bits. 978 if (Op.getOperand(0).getNode()->hasOneUse()) { 979 SDValue In = Op.getOperand(0); 980 switch (In.getOpcode()) { 981 default: break; 982 case ISD::SRL: 983 // Shrink SRL by a constant if none of the high bits shifted in are 984 // demanded. 985 if (TLO.LegalTypes() && 986 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 987 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 988 // undesirable. 989 break; 990 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 991 if (!ShAmt) 992 break; 993 SDValue Shift = In.getOperand(1); 994 if (TLO.LegalTypes()) { 995 uint64_t ShVal = ShAmt->getZExtValue(); 996 Shift = 997 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType())); 998 } 999 1000 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1001 OperandBitWidth - BitWidth); 1002 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth); 1003 1004 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1005 // None of the shifted in bits are needed. Add a truncate of the 1006 // shift input, then shift it. 1007 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1008 Op.getValueType(), 1009 In.getOperand(0)); 1010 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1011 Op.getValueType(), 1012 NewTrunc, 1013 Shift)); 1014 } 1015 break; 1016 } 1017 } 1018 1019 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1020 break; 1021 } 1022 case ISD::AssertZext: { 1023 // AssertZext demands all of the high bits, plus any of the low bits 1024 // demanded by its users. 1025 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1026 APInt InMask = APInt::getLowBitsSet(BitWidth, 1027 VT.getSizeInBits()); 1028 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask, 1029 KnownZero, KnownOne, TLO, Depth+1)) 1030 return true; 1031 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1032 1033 KnownZero |= ~InMask & NewMask; 1034 break; 1035 } 1036 case ISD::BITCAST: 1037 // If this is an FP->Int bitcast and if the sign bit is the only 1038 // thing demanded, turn this into a FGETSIGN. 1039 if (!TLO.LegalOperations() && 1040 !Op.getValueType().isVector() && 1041 !Op.getOperand(0).getValueType().isVector() && 1042 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && 1043 Op.getOperand(0).getValueType().isFloatingPoint()) { 1044 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); 1045 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); 1046 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) { 1047 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32; 1048 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1049 // place. We expect the SHL to be eliminated by other optimizations. 1050 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); 1051 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits(); 1052 if (!OpVTLegal && OpVTSizeInBits > 32) 1053 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); 1054 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1055 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); 1056 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 1057 Op.getValueType(), 1058 Sign, ShAmt)); 1059 } 1060 } 1061 break; 1062 case ISD::ADD: 1063 case ISD::MUL: 1064 case ISD::SUB: { 1065 // Add, Sub, and Mul don't demand any bits in positions beyond that 1066 // of the highest bit demanded of them. 1067 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1068 BitWidth - NewMask.countLeadingZeros()); 1069 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1070 KnownOne2, TLO, Depth+1)) 1071 return true; 1072 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1073 KnownOne2, TLO, Depth+1)) 1074 return true; 1075 // See if the operation should be performed at a smaller bit width. 1076 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1077 return true; 1078 } 1079 // FALL THROUGH 1080 default: 1081 // Just use computeKnownBits to compute output bits. 1082 TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth); 1083 break; 1084 } 1085 1086 // If we know the value of all of the demanded bits, return this as a 1087 // constant. 1088 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1089 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1090 1091 return false; 1092 } 1093 1094 /// computeKnownBitsForTargetNode - Determine which of the bits specified 1095 /// in Mask are known to be either zero or one and return them in the 1096 /// KnownZero/KnownOne bitsets. 1097 void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op, 1098 APInt &KnownZero, 1099 APInt &KnownOne, 1100 const SelectionDAG &DAG, 1101 unsigned Depth) const { 1102 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1103 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1104 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1105 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1106 "Should use MaskedValueIsZero if you don't know whether Op" 1107 " is a target node!"); 1108 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); 1109 } 1110 1111 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 1112 /// targets that want to expose additional information about sign bits to the 1113 /// DAG Combiner. 1114 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1115 const SelectionDAG &, 1116 unsigned Depth) const { 1117 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1118 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1119 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1120 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1121 "Should use ComputeNumSignBits if you don't know whether Op" 1122 " is a target node!"); 1123 return 1; 1124 } 1125 1126 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1127 /// one bit set. This differs from computeKnownBits in that it doesn't need to 1128 /// determine which bit is set. 1129 /// 1130 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1131 // A left-shift of a constant one will have exactly one bit set, because 1132 // shifting the bit off the end is undefined. 1133 if (Val.getOpcode() == ISD::SHL) 1134 if (ConstantSDNode *C = 1135 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1136 if (C->getAPIntValue() == 1) 1137 return true; 1138 1139 // Similarly, a right-shift of a constant sign-bit will have exactly 1140 // one bit set. 1141 if (Val.getOpcode() == ISD::SRL) 1142 if (ConstantSDNode *C = 1143 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1144 if (C->getAPIntValue().isSignBit()) 1145 return true; 1146 1147 // More could be done here, though the above checks are enough 1148 // to handle some common cases. 1149 1150 // Fall back to computeKnownBits to catch other known cases. 1151 EVT OpVT = Val.getValueType(); 1152 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1153 APInt KnownZero, KnownOne; 1154 DAG.computeKnownBits(Val, KnownZero, KnownOne); 1155 return (KnownZero.countPopulation() == BitWidth - 1) && 1156 (KnownOne.countPopulation() == 1); 1157 } 1158 1159 bool TargetLowering::isConstTrueVal(const SDNode *N) const { 1160 if (!N) 1161 return false; 1162 1163 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N); 1164 if (!CN) { 1165 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N); 1166 if (!BV) 1167 return false; 1168 1169 BitVector UndefElements; 1170 CN = BV->getConstantSplatNode(&UndefElements); 1171 // Only interested in constant splats, and we don't try to handle undef 1172 // elements in identifying boolean constants. 1173 if (!CN || UndefElements.none()) 1174 return false; 1175 } 1176 1177 switch (getBooleanContents(N->getValueType(0))) { 1178 case UndefinedBooleanContent: 1179 return CN->getAPIntValue()[0]; 1180 case ZeroOrOneBooleanContent: 1181 return CN->isOne(); 1182 case ZeroOrNegativeOneBooleanContent: 1183 return CN->isAllOnesValue(); 1184 } 1185 1186 llvm_unreachable("Invalid boolean contents"); 1187 } 1188 1189 bool TargetLowering::isConstFalseVal(const SDNode *N) const { 1190 if (!N) 1191 return false; 1192 1193 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N); 1194 if (!CN) { 1195 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N); 1196 if (!BV) 1197 return false; 1198 1199 BitVector UndefElements; 1200 CN = BV->getConstantSplatNode(&UndefElements); 1201 // Only interested in constant splats, and we don't try to handle undef 1202 // elements in identifying boolean constants. 1203 if (!CN || UndefElements.none()) 1204 return false; 1205 } 1206 1207 if (getBooleanContents(N->getValueType(0)) == UndefinedBooleanContent) 1208 return !CN->getAPIntValue()[0]; 1209 1210 return CN->isNullValue(); 1211 } 1212 1213 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 1214 /// and cc. If it is unable to simplify it, return a null SDValue. 1215 SDValue 1216 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1217 ISD::CondCode Cond, bool foldBooleans, 1218 DAGCombinerInfo &DCI, SDLoc dl) const { 1219 SelectionDAG &DAG = DCI.DAG; 1220 1221 // These setcc operations always fold. 1222 switch (Cond) { 1223 default: break; 1224 case ISD::SETFALSE: 1225 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1226 case ISD::SETTRUE: 1227 case ISD::SETTRUE2: { 1228 TargetLowering::BooleanContent Cnt = 1229 getBooleanContents(N0->getValueType(0)); 1230 return DAG.getConstant( 1231 Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, VT); 1232 } 1233 } 1234 1235 // Ensure that the constant occurs on the RHS, and fold constant 1236 // comparisons. 1237 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond); 1238 if (isa<ConstantSDNode>(N0.getNode()) && 1239 (DCI.isBeforeLegalizeOps() || 1240 isCondCodeLegal(SwappedCC, N0.getSimpleValueType()))) 1241 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC); 1242 1243 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1244 const APInt &C1 = N1C->getAPIntValue(); 1245 1246 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1247 // equality comparison, then we're just comparing whether X itself is 1248 // zero. 1249 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1250 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1251 N0.getOperand(1).getOpcode() == ISD::Constant) { 1252 const APInt &ShAmt 1253 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1254 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1255 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1256 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1257 // (srl (ctlz x), 5) == 0 -> X != 0 1258 // (srl (ctlz x), 5) != 1 -> X != 0 1259 Cond = ISD::SETNE; 1260 } else { 1261 // (srl (ctlz x), 5) != 0 -> X == 0 1262 // (srl (ctlz x), 5) == 1 -> X == 0 1263 Cond = ISD::SETEQ; 1264 } 1265 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1266 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1267 Zero, Cond); 1268 } 1269 } 1270 1271 SDValue CTPOP = N0; 1272 // Look through truncs that don't change the value of a ctpop. 1273 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE) 1274 CTPOP = N0.getOperand(0); 1275 1276 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP && 1277 (N0 == CTPOP || N0.getValueType().getSizeInBits() > 1278 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) { 1279 EVT CTVT = CTPOP.getValueType(); 1280 SDValue CTOp = CTPOP.getOperand(0); 1281 1282 // (ctpop x) u< 2 -> (x & x-1) == 0 1283 // (ctpop x) u> 1 -> (x & x-1) != 0 1284 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ 1285 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp, 1286 DAG.getConstant(1, CTVT)); 1287 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub); 1288 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; 1289 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC); 1290 } 1291 1292 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal. 1293 } 1294 1295 // (zext x) == C --> x == (trunc C) 1296 // (sext x) == C --> x == (trunc C) 1297 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1298 DCI.isBeforeLegalize() && N0->hasOneUse()) { 1299 unsigned MinBits = N0.getValueSizeInBits(); 1300 SDValue PreExt; 1301 bool Signed = false; 1302 if (N0->getOpcode() == ISD::ZERO_EXTEND) { 1303 // ZExt 1304 MinBits = N0->getOperand(0).getValueSizeInBits(); 1305 PreExt = N0->getOperand(0); 1306 } else if (N0->getOpcode() == ISD::AND) { 1307 // DAGCombine turns costly ZExts into ANDs 1308 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1))) 1309 if ((C->getAPIntValue()+1).isPowerOf2()) { 1310 MinBits = C->getAPIntValue().countTrailingOnes(); 1311 PreExt = N0->getOperand(0); 1312 } 1313 } else if (N0->getOpcode() == ISD::SIGN_EXTEND) { 1314 // SExt 1315 MinBits = N0->getOperand(0).getValueSizeInBits(); 1316 PreExt = N0->getOperand(0); 1317 Signed = true; 1318 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) { 1319 // ZEXTLOAD / SEXTLOAD 1320 if (LN0->getExtensionType() == ISD::ZEXTLOAD) { 1321 MinBits = LN0->getMemoryVT().getSizeInBits(); 1322 PreExt = N0; 1323 } else if (LN0->getExtensionType() == ISD::SEXTLOAD) { 1324 Signed = true; 1325 MinBits = LN0->getMemoryVT().getSizeInBits(); 1326 PreExt = N0; 1327 } 1328 } 1329 1330 // Figure out how many bits we need to preserve this constant. 1331 unsigned ReqdBits = Signed ? 1332 C1.getBitWidth() - C1.getNumSignBits() + 1 : 1333 C1.getActiveBits(); 1334 1335 // Make sure we're not losing bits from the constant. 1336 if (MinBits > 0 && 1337 MinBits < C1.getBitWidth() && 1338 MinBits >= ReqdBits) { 1339 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits); 1340 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { 1341 // Will get folded away. 1342 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt); 1343 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT); 1344 return DAG.getSetCC(dl, VT, Trunc, C, Cond); 1345 } 1346 } 1347 } 1348 1349 // If the LHS is '(and load, const)', the RHS is 0, 1350 // the test is for equality or unsigned, and all 1 bits of the const are 1351 // in the same partial word, see if we can shorten the load. 1352 if (DCI.isBeforeLegalize() && 1353 !ISD::isSignedIntSetCC(Cond) && 1354 N0.getOpcode() == ISD::AND && C1 == 0 && 1355 N0.getNode()->hasOneUse() && 1356 isa<LoadSDNode>(N0.getOperand(0)) && 1357 N0.getOperand(0).getNode()->hasOneUse() && 1358 isa<ConstantSDNode>(N0.getOperand(1))) { 1359 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1360 APInt bestMask; 1361 unsigned bestWidth = 0, bestOffset = 0; 1362 if (!Lod->isVolatile() && Lod->isUnindexed()) { 1363 unsigned origWidth = N0.getValueType().getSizeInBits(); 1364 unsigned maskWidth = origWidth; 1365 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1366 // 8 bits, but have to be careful... 1367 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1368 origWidth = Lod->getMemoryVT().getSizeInBits(); 1369 const APInt &Mask = 1370 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1371 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1372 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 1373 for (unsigned offset=0; offset<origWidth/width; offset++) { 1374 if ((newMask & Mask) == Mask) { 1375 if (!getDataLayout()->isLittleEndian()) 1376 bestOffset = (origWidth/width - offset - 1) * (width/8); 1377 else 1378 bestOffset = (uint64_t)offset * (width/8); 1379 bestMask = Mask.lshr(offset * (width/8) * 8); 1380 bestWidth = width; 1381 break; 1382 } 1383 newMask = newMask << width; 1384 } 1385 } 1386 } 1387 if (bestWidth) { 1388 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth); 1389 if (newVT.isRound()) { 1390 EVT PtrType = Lod->getOperand(1).getValueType(); 1391 SDValue Ptr = Lod->getBasePtr(); 1392 if (bestOffset != 0) 1393 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1394 DAG.getConstant(bestOffset, PtrType)); 1395 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1396 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1397 Lod->getPointerInfo().getWithOffset(bestOffset), 1398 false, false, false, NewAlign); 1399 return DAG.getSetCC(dl, VT, 1400 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1401 DAG.getConstant(bestMask.trunc(bestWidth), 1402 newVT)), 1403 DAG.getConstant(0LL, newVT), Cond); 1404 } 1405 } 1406 } 1407 1408 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1409 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1410 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1411 1412 // If the comparison constant has bits in the upper part, the 1413 // zero-extended value could never match. 1414 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1415 C1.getBitWidth() - InSize))) { 1416 switch (Cond) { 1417 case ISD::SETUGT: 1418 case ISD::SETUGE: 1419 case ISD::SETEQ: return DAG.getConstant(0, VT); 1420 case ISD::SETULT: 1421 case ISD::SETULE: 1422 case ISD::SETNE: return DAG.getConstant(1, VT); 1423 case ISD::SETGT: 1424 case ISD::SETGE: 1425 // True if the sign bit of C1 is set. 1426 return DAG.getConstant(C1.isNegative(), VT); 1427 case ISD::SETLT: 1428 case ISD::SETLE: 1429 // True if the sign bit of C1 isn't set. 1430 return DAG.getConstant(C1.isNonNegative(), VT); 1431 default: 1432 break; 1433 } 1434 } 1435 1436 // Otherwise, we can perform the comparison with the low bits. 1437 switch (Cond) { 1438 case ISD::SETEQ: 1439 case ISD::SETNE: 1440 case ISD::SETUGT: 1441 case ISD::SETUGE: 1442 case ISD::SETULT: 1443 case ISD::SETULE: { 1444 EVT newVT = N0.getOperand(0).getValueType(); 1445 if (DCI.isBeforeLegalizeOps() || 1446 (isOperationLegal(ISD::SETCC, newVT) && 1447 getCondCodeAction(Cond, newVT.getSimpleVT()) == Legal)) { 1448 EVT NewSetCCVT = getSetCCResultType(*DAG.getContext(), newVT); 1449 SDValue NewConst = DAG.getConstant(C1.trunc(InSize), newVT); 1450 1451 SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0), 1452 NewConst, Cond); 1453 return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType()); 1454 } 1455 break; 1456 } 1457 default: 1458 break; // todo, be more careful with signed comparisons 1459 } 1460 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1461 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1462 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1463 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1464 EVT ExtDstTy = N0.getValueType(); 1465 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1466 1467 // If the constant doesn't fit into the number of bits for the source of 1468 // the sign extension, it is impossible for both sides to be equal. 1469 if (C1.getMinSignedBits() > ExtSrcTyBits) 1470 return DAG.getConstant(Cond == ISD::SETNE, VT); 1471 1472 SDValue ZextOp; 1473 EVT Op0Ty = N0.getOperand(0).getValueType(); 1474 if (Op0Ty == ExtSrcTy) { 1475 ZextOp = N0.getOperand(0); 1476 } else { 1477 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1478 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1479 DAG.getConstant(Imm, Op0Ty)); 1480 } 1481 if (!DCI.isCalledByLegalizer()) 1482 DCI.AddToWorklist(ZextOp.getNode()); 1483 // Otherwise, make this a use of a zext. 1484 return DAG.getSetCC(dl, VT, ZextOp, 1485 DAG.getConstant(C1 & APInt::getLowBitsSet( 1486 ExtDstTyBits, 1487 ExtSrcTyBits), 1488 ExtDstTy), 1489 Cond); 1490 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1491 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1492 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1493 if (N0.getOpcode() == ISD::SETCC && 1494 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 1495 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 1496 if (TrueWhenTrue) 1497 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 1498 // Invert the condition. 1499 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1500 CC = ISD::getSetCCInverse(CC, 1501 N0.getOperand(0).getValueType().isInteger()); 1502 if (DCI.isBeforeLegalizeOps() || 1503 isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType())) 1504 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 1505 } 1506 1507 if ((N0.getOpcode() == ISD::XOR || 1508 (N0.getOpcode() == ISD::AND && 1509 N0.getOperand(0).getOpcode() == ISD::XOR && 1510 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1511 isa<ConstantSDNode>(N0.getOperand(1)) && 1512 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1513 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1514 // can only do this if the top bits are known zero. 1515 unsigned BitWidth = N0.getValueSizeInBits(); 1516 if (DAG.MaskedValueIsZero(N0, 1517 APInt::getHighBitsSet(BitWidth, 1518 BitWidth-1))) { 1519 // Okay, get the un-inverted input value. 1520 SDValue Val; 1521 if (N0.getOpcode() == ISD::XOR) 1522 Val = N0.getOperand(0); 1523 else { 1524 assert(N0.getOpcode() == ISD::AND && 1525 N0.getOperand(0).getOpcode() == ISD::XOR); 1526 // ((X^1)&1)^1 -> X & 1 1527 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 1528 N0.getOperand(0).getOperand(0), 1529 N0.getOperand(1)); 1530 } 1531 1532 return DAG.getSetCC(dl, VT, Val, N1, 1533 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1534 } 1535 } else if (N1C->getAPIntValue() == 1 && 1536 (VT == MVT::i1 || 1537 getBooleanContents(N0->getValueType(0)) == 1538 ZeroOrOneBooleanContent)) { 1539 SDValue Op0 = N0; 1540 if (Op0.getOpcode() == ISD::TRUNCATE) 1541 Op0 = Op0.getOperand(0); 1542 1543 if ((Op0.getOpcode() == ISD::XOR) && 1544 Op0.getOperand(0).getOpcode() == ISD::SETCC && 1545 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 1546 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 1547 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 1548 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 1549 Cond); 1550 } 1551 if (Op0.getOpcode() == ISD::AND && 1552 isa<ConstantSDNode>(Op0.getOperand(1)) && 1553 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 1554 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 1555 if (Op0.getValueType().bitsGT(VT)) 1556 Op0 = DAG.getNode(ISD::AND, dl, VT, 1557 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 1558 DAG.getConstant(1, VT)); 1559 else if (Op0.getValueType().bitsLT(VT)) 1560 Op0 = DAG.getNode(ISD::AND, dl, VT, 1561 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 1562 DAG.getConstant(1, VT)); 1563 1564 return DAG.getSetCC(dl, VT, Op0, 1565 DAG.getConstant(0, Op0.getValueType()), 1566 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1567 } 1568 if (Op0.getOpcode() == ISD::AssertZext && 1569 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1) 1570 return DAG.getSetCC(dl, VT, Op0, 1571 DAG.getConstant(0, Op0.getValueType()), 1572 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1573 } 1574 } 1575 1576 APInt MinVal, MaxVal; 1577 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1578 if (ISD::isSignedIntSetCC(Cond)) { 1579 MinVal = APInt::getSignedMinValue(OperandBitSize); 1580 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1581 } else { 1582 MinVal = APInt::getMinValue(OperandBitSize); 1583 MaxVal = APInt::getMaxValue(OperandBitSize); 1584 } 1585 1586 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1587 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1588 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1589 // X >= C0 --> X > (C0 - 1) 1590 APInt C = C1 - 1; 1591 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; 1592 if ((DCI.isBeforeLegalizeOps() || 1593 isCondCodeLegal(NewCC, VT.getSimpleVT())) && 1594 (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 && 1595 isLegalICmpImmediate(C.getSExtValue())))) { 1596 return DAG.getSetCC(dl, VT, N0, 1597 DAG.getConstant(C, N1.getValueType()), 1598 NewCC); 1599 } 1600 } 1601 1602 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1603 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1604 // X <= C0 --> X < (C0 + 1) 1605 APInt C = C1 + 1; 1606 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; 1607 if ((DCI.isBeforeLegalizeOps() || 1608 isCondCodeLegal(NewCC, VT.getSimpleVT())) && 1609 (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 && 1610 isLegalICmpImmediate(C.getSExtValue())))) { 1611 return DAG.getSetCC(dl, VT, N0, 1612 DAG.getConstant(C, N1.getValueType()), 1613 NewCC); 1614 } 1615 } 1616 1617 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1618 return DAG.getConstant(0, VT); // X < MIN --> false 1619 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1620 return DAG.getConstant(1, VT); // X >= MIN --> true 1621 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1622 return DAG.getConstant(0, VT); // X > MAX --> false 1623 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1624 return DAG.getConstant(1, VT); // X <= MAX --> true 1625 1626 // Canonicalize setgt X, Min --> setne X, Min 1627 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1628 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1629 // Canonicalize setlt X, Max --> setne X, Max 1630 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1631 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1632 1633 // If we have setult X, 1, turn it into seteq X, 0 1634 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1635 return DAG.getSetCC(dl, VT, N0, 1636 DAG.getConstant(MinVal, N0.getValueType()), 1637 ISD::SETEQ); 1638 // If we have setugt X, Max-1, turn it into seteq X, Max 1639 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1640 return DAG.getSetCC(dl, VT, N0, 1641 DAG.getConstant(MaxVal, N0.getValueType()), 1642 ISD::SETEQ); 1643 1644 // If we have "setcc X, C0", check to see if we can shrink the immediate 1645 // by changing cc. 1646 1647 // SETUGT X, SINTMAX -> SETLT X, 0 1648 if (Cond == ISD::SETUGT && 1649 C1 == APInt::getSignedMaxValue(OperandBitSize)) 1650 return DAG.getSetCC(dl, VT, N0, 1651 DAG.getConstant(0, N1.getValueType()), 1652 ISD::SETLT); 1653 1654 // SETULT X, SINTMIN -> SETGT X, -1 1655 if (Cond == ISD::SETULT && 1656 C1 == APInt::getSignedMinValue(OperandBitSize)) { 1657 SDValue ConstMinusOne = 1658 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 1659 N1.getValueType()); 1660 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 1661 } 1662 1663 // Fold bit comparisons when we can. 1664 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1665 (VT == N0.getValueType() || 1666 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 1667 N0.getOpcode() == ISD::AND) 1668 if (ConstantSDNode *AndRHS = 1669 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1670 EVT ShiftTy = DCI.isBeforeLegalize() ? 1671 getPointerTy() : getShiftAmountTy(N0.getValueType()); 1672 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1673 // Perform the xform if the AND RHS is a single bit. 1674 if (AndRHS->getAPIntValue().isPowerOf2()) { 1675 return DAG.getNode(ISD::TRUNCATE, dl, VT, 1676 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 1677 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 1678 } 1679 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 1680 // (X & 8) == 8 --> (X & 8) >> 3 1681 // Perform the xform if C1 is a single bit. 1682 if (C1.isPowerOf2()) { 1683 return DAG.getNode(ISD::TRUNCATE, dl, VT, 1684 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 1685 DAG.getConstant(C1.logBase2(), ShiftTy))); 1686 } 1687 } 1688 } 1689 1690 if (C1.getMinSignedBits() <= 64 && 1691 !isLegalICmpImmediate(C1.getSExtValue())) { 1692 // (X & -256) == 256 -> (X >> 8) == 1 1693 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1694 N0.getOpcode() == ISD::AND && N0.hasOneUse()) { 1695 if (ConstantSDNode *AndRHS = 1696 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1697 const APInt &AndRHSC = AndRHS->getAPIntValue(); 1698 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) { 1699 unsigned ShiftBits = AndRHSC.countTrailingZeros(); 1700 EVT ShiftTy = DCI.isBeforeLegalize() ? 1701 getPointerTy() : getShiftAmountTy(N0.getValueType()); 1702 EVT CmpTy = N0.getValueType(); 1703 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0), 1704 DAG.getConstant(ShiftBits, ShiftTy)); 1705 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy); 1706 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond); 1707 } 1708 } 1709 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || 1710 Cond == ISD::SETULE || Cond == ISD::SETUGT) { 1711 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT); 1712 // X < 0x100000000 -> (X >> 32) < 1 1713 // X >= 0x100000000 -> (X >> 32) >= 1 1714 // X <= 0x0ffffffff -> (X >> 32) < 1 1715 // X > 0x0ffffffff -> (X >> 32) >= 1 1716 unsigned ShiftBits; 1717 APInt NewC = C1; 1718 ISD::CondCode NewCond = Cond; 1719 if (AdjOne) { 1720 ShiftBits = C1.countTrailingOnes(); 1721 NewC = NewC + 1; 1722 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 1723 } else { 1724 ShiftBits = C1.countTrailingZeros(); 1725 } 1726 NewC = NewC.lshr(ShiftBits); 1727 if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) { 1728 EVT ShiftTy = DCI.isBeforeLegalize() ? 1729 getPointerTy() : getShiftAmountTy(N0.getValueType()); 1730 EVT CmpTy = N0.getValueType(); 1731 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0, 1732 DAG.getConstant(ShiftBits, ShiftTy)); 1733 SDValue CmpRHS = DAG.getConstant(NewC, CmpTy); 1734 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond); 1735 } 1736 } 1737 } 1738 } 1739 1740 if (isa<ConstantFPSDNode>(N0.getNode())) { 1741 // Constant fold or commute setcc. 1742 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 1743 if (O.getNode()) return O; 1744 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1745 // If the RHS of an FP comparison is a constant, simplify it away in 1746 // some cases. 1747 if (CFP->getValueAPF().isNaN()) { 1748 // If an operand is known to be a nan, we can fold it. 1749 switch (ISD::getUnorderedFlavor(Cond)) { 1750 default: llvm_unreachable("Unknown flavor!"); 1751 case 0: // Known false. 1752 return DAG.getConstant(0, VT); 1753 case 1: // Known true. 1754 return DAG.getConstant(1, VT); 1755 case 2: // Undefined. 1756 return DAG.getUNDEF(VT); 1757 } 1758 } 1759 1760 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1761 // constant if knowing that the operand is non-nan is enough. We prefer to 1762 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1763 // materialize 0.0. 1764 if (Cond == ISD::SETO || Cond == ISD::SETUO) 1765 return DAG.getSetCC(dl, VT, N0, N0, Cond); 1766 1767 // If the condition is not legal, see if we can find an equivalent one 1768 // which is legal. 1769 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) { 1770 // If the comparison was an awkward floating-point == or != and one of 1771 // the comparison operands is infinity or negative infinity, convert the 1772 // condition to a less-awkward <= or >=. 1773 if (CFP->getValueAPF().isInfinity()) { 1774 if (CFP->getValueAPF().isNegative()) { 1775 if (Cond == ISD::SETOEQ && 1776 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) 1777 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 1778 if (Cond == ISD::SETUEQ && 1779 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) 1780 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 1781 if (Cond == ISD::SETUNE && 1782 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType())) 1783 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 1784 if (Cond == ISD::SETONE && 1785 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType())) 1786 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 1787 } else { 1788 if (Cond == ISD::SETOEQ && 1789 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) 1790 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 1791 if (Cond == ISD::SETUEQ && 1792 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) 1793 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 1794 if (Cond == ISD::SETUNE && 1795 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType())) 1796 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 1797 if (Cond == ISD::SETONE && 1798 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType())) 1799 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 1800 } 1801 } 1802 } 1803 } 1804 1805 if (N0 == N1) { 1806 // The sext(setcc()) => setcc() optimization relies on the appropriate 1807 // constant being emitted. 1808 uint64_t EqVal = 0; 1809 switch (getBooleanContents(N0.getValueType())) { 1810 case UndefinedBooleanContent: 1811 case ZeroOrOneBooleanContent: 1812 EqVal = ISD::isTrueWhenEqual(Cond); 1813 break; 1814 case ZeroOrNegativeOneBooleanContent: 1815 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0; 1816 break; 1817 } 1818 1819 // We can always fold X == X for integer setcc's. 1820 if (N0.getValueType().isInteger()) { 1821 return DAG.getConstant(EqVal, VT); 1822 } 1823 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1824 if (UOF == 2) // FP operators that are undefined on NaNs. 1825 return DAG.getConstant(EqVal, VT); 1826 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1827 return DAG.getConstant(EqVal, VT); 1828 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1829 // if it is not already. 1830 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1831 if (NewCond != Cond && (DCI.isBeforeLegalizeOps() || 1832 getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal)) 1833 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 1834 } 1835 1836 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1837 N0.getValueType().isInteger()) { 1838 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1839 N0.getOpcode() == ISD::XOR) { 1840 // Simplify (X+Y) == (X+Z) --> Y == Z 1841 if (N0.getOpcode() == N1.getOpcode()) { 1842 if (N0.getOperand(0) == N1.getOperand(0)) 1843 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 1844 if (N0.getOperand(1) == N1.getOperand(1)) 1845 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 1846 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1847 // If X op Y == Y op X, try other combinations. 1848 if (N0.getOperand(0) == N1.getOperand(1)) 1849 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 1850 Cond); 1851 if (N0.getOperand(1) == N1.getOperand(0)) 1852 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 1853 Cond); 1854 } 1855 } 1856 1857 // If RHS is a legal immediate value for a compare instruction, we need 1858 // to be careful about increasing register pressure needlessly. 1859 bool LegalRHSImm = false; 1860 1861 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1862 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1863 // Turn (X+C1) == C2 --> X == C2-C1 1864 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 1865 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1866 DAG.getConstant(RHSC->getAPIntValue()- 1867 LHSR->getAPIntValue(), 1868 N0.getValueType()), Cond); 1869 } 1870 1871 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1872 if (N0.getOpcode() == ISD::XOR) 1873 // If we know that all of the inverted bits are zero, don't bother 1874 // performing the inversion. 1875 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 1876 return 1877 DAG.getSetCC(dl, VT, N0.getOperand(0), 1878 DAG.getConstant(LHSR->getAPIntValue() ^ 1879 RHSC->getAPIntValue(), 1880 N0.getValueType()), 1881 Cond); 1882 } 1883 1884 // Turn (C1-X) == C2 --> X == C1-C2 1885 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1886 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 1887 return 1888 DAG.getSetCC(dl, VT, N0.getOperand(1), 1889 DAG.getConstant(SUBC->getAPIntValue() - 1890 RHSC->getAPIntValue(), 1891 N0.getValueType()), 1892 Cond); 1893 } 1894 } 1895 1896 // Could RHSC fold directly into a compare? 1897 if (RHSC->getValueType(0).getSizeInBits() <= 64) 1898 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue()); 1899 } 1900 1901 // Simplify (X+Z) == X --> Z == 0 1902 // Don't do this if X is an immediate that can fold into a cmp 1903 // instruction and X+Z has other uses. It could be an induction variable 1904 // chain, and the transform would increase register pressure. 1905 if (!LegalRHSImm || N0.getNode()->hasOneUse()) { 1906 if (N0.getOperand(0) == N1) 1907 return DAG.getSetCC(dl, VT, N0.getOperand(1), 1908 DAG.getConstant(0, N0.getValueType()), Cond); 1909 if (N0.getOperand(1) == N1) { 1910 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1911 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1912 DAG.getConstant(0, N0.getValueType()), Cond); 1913 if (N0.getNode()->hasOneUse()) { 1914 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1915 // (Z-X) == X --> Z == X<<1 1916 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1, 1917 DAG.getConstant(1, getShiftAmountTy(N1.getValueType()))); 1918 if (!DCI.isCalledByLegalizer()) 1919 DCI.AddToWorklist(SH.getNode()); 1920 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 1921 } 1922 } 1923 } 1924 } 1925 1926 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1927 N1.getOpcode() == ISD::XOR) { 1928 // Simplify X == (X+Z) --> Z == 0 1929 if (N1.getOperand(0) == N0) 1930 return DAG.getSetCC(dl, VT, N1.getOperand(1), 1931 DAG.getConstant(0, N1.getValueType()), Cond); 1932 if (N1.getOperand(1) == N0) { 1933 if (DAG.isCommutativeBinOp(N1.getOpcode())) 1934 return DAG.getSetCC(dl, VT, N1.getOperand(0), 1935 DAG.getConstant(0, N1.getValueType()), Cond); 1936 if (N1.getNode()->hasOneUse()) { 1937 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1938 // X == (Z-X) --> X<<1 == Z 1939 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 1940 DAG.getConstant(1, getShiftAmountTy(N0.getValueType()))); 1941 if (!DCI.isCalledByLegalizer()) 1942 DCI.AddToWorklist(SH.getNode()); 1943 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 1944 } 1945 } 1946 } 1947 1948 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 1949 // Note that where y is variable and is known to have at most 1950 // one bit set (for example, if it is z&1) we cannot do this; 1951 // the expressions are not equivalent when y==0. 1952 if (N0.getOpcode() == ISD::AND) 1953 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 1954 if (ValueHasExactlyOneBitSet(N1, DAG)) { 1955 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 1956 if (DCI.isBeforeLegalizeOps() || 1957 isCondCodeLegal(Cond, N0.getSimpleValueType())) { 1958 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 1959 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 1960 } 1961 } 1962 } 1963 if (N1.getOpcode() == ISD::AND) 1964 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 1965 if (ValueHasExactlyOneBitSet(N0, DAG)) { 1966 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 1967 if (DCI.isBeforeLegalizeOps() || 1968 isCondCodeLegal(Cond, N1.getSimpleValueType())) { 1969 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1970 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 1971 } 1972 } 1973 } 1974 } 1975 1976 // Fold away ALL boolean setcc's. 1977 SDValue Temp; 1978 if (N0.getValueType() == MVT::i1 && foldBooleans) { 1979 switch (Cond) { 1980 default: llvm_unreachable("Unknown integer setcc!"); 1981 case ISD::SETEQ: // X == Y -> ~(X^Y) 1982 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 1983 N0 = DAG.getNOT(dl, Temp, MVT::i1); 1984 if (!DCI.isCalledByLegalizer()) 1985 DCI.AddToWorklist(Temp.getNode()); 1986 break; 1987 case ISD::SETNE: // X != Y --> (X^Y) 1988 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 1989 break; 1990 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 1991 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 1992 Temp = DAG.getNOT(dl, N0, MVT::i1); 1993 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 1994 if (!DCI.isCalledByLegalizer()) 1995 DCI.AddToWorklist(Temp.getNode()); 1996 break; 1997 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 1998 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 1999 Temp = DAG.getNOT(dl, N1, MVT::i1); 2000 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2001 if (!DCI.isCalledByLegalizer()) 2002 DCI.AddToWorklist(Temp.getNode()); 2003 break; 2004 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2005 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2006 Temp = DAG.getNOT(dl, N0, MVT::i1); 2007 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2008 if (!DCI.isCalledByLegalizer()) 2009 DCI.AddToWorklist(Temp.getNode()); 2010 break; 2011 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2012 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2013 Temp = DAG.getNOT(dl, N1, MVT::i1); 2014 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2015 break; 2016 } 2017 if (VT != MVT::i1) { 2018 if (!DCI.isCalledByLegalizer()) 2019 DCI.AddToWorklist(N0.getNode()); 2020 // FIXME: If running after legalize, we probably can't do this. 2021 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2022 } 2023 return N0; 2024 } 2025 2026 // Could not fold it. 2027 return SDValue(); 2028 } 2029 2030 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2031 /// node is a GlobalAddress + offset. 2032 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA, 2033 int64_t &Offset) const { 2034 if (isa<GlobalAddressSDNode>(N)) { 2035 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2036 GA = GASD->getGlobal(); 2037 Offset += GASD->getOffset(); 2038 return true; 2039 } 2040 2041 if (N->getOpcode() == ISD::ADD) { 2042 SDValue N1 = N->getOperand(0); 2043 SDValue N2 = N->getOperand(1); 2044 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2045 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2046 if (V) { 2047 Offset += V->getSExtValue(); 2048 return true; 2049 } 2050 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2051 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2052 if (V) { 2053 Offset += V->getSExtValue(); 2054 return true; 2055 } 2056 } 2057 } 2058 2059 return false; 2060 } 2061 2062 2063 SDValue TargetLowering:: 2064 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2065 // Default implementation: no optimization. 2066 return SDValue(); 2067 } 2068 2069 //===----------------------------------------------------------------------===// 2070 // Inline Assembler Implementation Methods 2071 //===----------------------------------------------------------------------===// 2072 2073 2074 TargetLowering::ConstraintType 2075 TargetLowering::getConstraintType(const std::string &Constraint) const { 2076 unsigned S = Constraint.size(); 2077 2078 if (S == 1) { 2079 switch (Constraint[0]) { 2080 default: break; 2081 case 'r': return C_RegisterClass; 2082 case 'm': // memory 2083 case 'o': // offsetable 2084 case 'V': // not offsetable 2085 return C_Memory; 2086 case 'i': // Simple Integer or Relocatable Constant 2087 case 'n': // Simple Integer 2088 case 'E': // Floating Point Constant 2089 case 'F': // Floating Point Constant 2090 case 's': // Relocatable Constant 2091 case 'p': // Address. 2092 case 'X': // Allow ANY value. 2093 case 'I': // Target registers. 2094 case 'J': 2095 case 'K': 2096 case 'L': 2097 case 'M': 2098 case 'N': 2099 case 'O': 2100 case 'P': 2101 case '<': 2102 case '>': 2103 return C_Other; 2104 } 2105 } 2106 2107 if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') { 2108 if (S == 8 && !Constraint.compare(1, 6, "memory", 6)) // "{memory}" 2109 return C_Memory; 2110 return C_Register; 2111 } 2112 return C_Unknown; 2113 } 2114 2115 /// LowerXConstraint - try to replace an X constraint, which matches anything, 2116 /// with another that has more specific requirements based on the type of the 2117 /// corresponding operand. 2118 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2119 if (ConstraintVT.isInteger()) 2120 return "r"; 2121 if (ConstraintVT.isFloatingPoint()) 2122 return "f"; // works for many targets 2123 return nullptr; 2124 } 2125 2126 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2127 /// vector. If it is invalid, don't add anything to Ops. 2128 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2129 std::string &Constraint, 2130 std::vector<SDValue> &Ops, 2131 SelectionDAG &DAG) const { 2132 2133 if (Constraint.length() > 1) return; 2134 2135 char ConstraintLetter = Constraint[0]; 2136 switch (ConstraintLetter) { 2137 default: break; 2138 case 'X': // Allows any operand; labels (basic block) use this. 2139 if (Op.getOpcode() == ISD::BasicBlock) { 2140 Ops.push_back(Op); 2141 return; 2142 } 2143 // fall through 2144 case 'i': // Simple Integer or Relocatable Constant 2145 case 'n': // Simple Integer 2146 case 's': { // Relocatable Constant 2147 // These operands are interested in values of the form (GV+C), where C may 2148 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2149 // is possible and fine if either GV or C are missing. 2150 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2151 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2152 2153 // If we have "(add GV, C)", pull out GV/C 2154 if (Op.getOpcode() == ISD::ADD) { 2155 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2156 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2157 if (!C || !GA) { 2158 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2159 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2160 } 2161 if (!C || !GA) 2162 C = nullptr, GA = nullptr; 2163 } 2164 2165 // If we find a valid operand, map to the TargetXXX version so that the 2166 // value itself doesn't get selected. 2167 if (GA) { // Either &GV or &GV+C 2168 if (ConstraintLetter != 'n') { 2169 int64_t Offs = GA->getOffset(); 2170 if (C) Offs += C->getZExtValue(); 2171 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2172 C ? SDLoc(C) : SDLoc(), 2173 Op.getValueType(), Offs)); 2174 return; 2175 } 2176 } 2177 if (C) { // just C, no GV. 2178 // Simple constants are not allowed for 's'. 2179 if (ConstraintLetter != 's') { 2180 // gcc prints these as sign extended. Sign extend value to 64 bits 2181 // now; without this it would get ZExt'd later in 2182 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2183 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2184 MVT::i64)); 2185 return; 2186 } 2187 } 2188 break; 2189 } 2190 } 2191 } 2192 2193 std::pair<unsigned, const TargetRegisterClass *> 2194 TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI, 2195 const std::string &Constraint, 2196 MVT VT) const { 2197 if (Constraint.empty() || Constraint[0] != '{') 2198 return std::make_pair(0u, static_cast<TargetRegisterClass*>(nullptr)); 2199 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2200 2201 // Remove the braces from around the name. 2202 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2203 2204 std::pair<unsigned, const TargetRegisterClass*> R = 2205 std::make_pair(0u, static_cast<const TargetRegisterClass*>(nullptr)); 2206 2207 // Figure out which register class contains this reg. 2208 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2209 E = RI->regclass_end(); RCI != E; ++RCI) { 2210 const TargetRegisterClass *RC = *RCI; 2211 2212 // If none of the value types for this register class are valid, we 2213 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2214 if (!isLegalRC(RC)) 2215 continue; 2216 2217 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2218 I != E; ++I) { 2219 if (RegName.equals_lower(RI->getName(*I))) { 2220 std::pair<unsigned, const TargetRegisterClass*> S = 2221 std::make_pair(*I, RC); 2222 2223 // If this register class has the requested value type, return it, 2224 // otherwise keep searching and return the first class found 2225 // if no other is found which explicitly has the requested type. 2226 if (RC->hasType(VT)) 2227 return S; 2228 else if (!R.second) 2229 R = S; 2230 } 2231 } 2232 } 2233 2234 return R; 2235 } 2236 2237 //===----------------------------------------------------------------------===// 2238 // Constraint Selection. 2239 2240 /// isMatchingInputConstraint - Return true of this is an input operand that is 2241 /// a matching constraint like "4". 2242 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2243 assert(!ConstraintCode.empty() && "No known constraint!"); 2244 return isdigit(static_cast<unsigned char>(ConstraintCode[0])); 2245 } 2246 2247 /// getMatchedOperand - If this is an input matching constraint, this method 2248 /// returns the output operand it matches. 2249 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2250 assert(!ConstraintCode.empty() && "No known constraint!"); 2251 return atoi(ConstraintCode.c_str()); 2252 } 2253 2254 2255 /// ParseConstraints - Split up the constraint string from the inline 2256 /// assembly value into the specific constraints and their prefixes, 2257 /// and also tie in the associated operand values. 2258 /// If this returns an empty vector, and if the constraint string itself 2259 /// isn't empty, there was an error parsing. 2260 TargetLowering::AsmOperandInfoVector 2261 TargetLowering::ParseConstraints(const TargetRegisterInfo *TRI, 2262 ImmutableCallSite CS) const { 2263 /// ConstraintOperands - Information about all of the constraints. 2264 AsmOperandInfoVector ConstraintOperands; 2265 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 2266 unsigned maCount = 0; // Largest number of multiple alternative constraints. 2267 2268 // Do a prepass over the constraints, canonicalizing them, and building up the 2269 // ConstraintOperands list. 2270 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 2271 unsigned ResNo = 0; // ResNo - The result number of the next output. 2272 2273 for (InlineAsm::ConstraintInfo &CI : IA->ParseConstraints()) { 2274 ConstraintOperands.emplace_back(std::move(CI)); 2275 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 2276 2277 // Update multiple alternative constraint count. 2278 if (OpInfo.multipleAlternatives.size() > maCount) 2279 maCount = OpInfo.multipleAlternatives.size(); 2280 2281 OpInfo.ConstraintVT = MVT::Other; 2282 2283 // Compute the value type for each operand. 2284 switch (OpInfo.Type) { 2285 case InlineAsm::isOutput: 2286 // Indirect outputs just consume an argument. 2287 if (OpInfo.isIndirect) { 2288 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2289 break; 2290 } 2291 2292 // The return value of the call is this value. As such, there is no 2293 // corresponding argument. 2294 assert(!CS.getType()->isVoidTy() && 2295 "Bad inline asm!"); 2296 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 2297 OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo)); 2298 } else { 2299 assert(ResNo == 0 && "Asm only has one result!"); 2300 OpInfo.ConstraintVT = getSimpleValueType(CS.getType()); 2301 } 2302 ++ResNo; 2303 break; 2304 case InlineAsm::isInput: 2305 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2306 break; 2307 case InlineAsm::isClobber: 2308 // Nothing to do. 2309 break; 2310 } 2311 2312 if (OpInfo.CallOperandVal) { 2313 llvm::Type *OpTy = OpInfo.CallOperandVal->getType(); 2314 if (OpInfo.isIndirect) { 2315 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 2316 if (!PtrTy) 2317 report_fatal_error("Indirect operand for inline asm not a pointer!"); 2318 OpTy = PtrTy->getElementType(); 2319 } 2320 2321 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 2322 if (StructType *STy = dyn_cast<StructType>(OpTy)) 2323 if (STy->getNumElements() == 1) 2324 OpTy = STy->getElementType(0); 2325 2326 // If OpTy is not a single value, it may be a struct/union that we 2327 // can tile with integers. 2328 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 2329 unsigned BitSize = getDataLayout()->getTypeSizeInBits(OpTy); 2330 switch (BitSize) { 2331 default: break; 2332 case 1: 2333 case 8: 2334 case 16: 2335 case 32: 2336 case 64: 2337 case 128: 2338 OpInfo.ConstraintVT = 2339 MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true); 2340 break; 2341 } 2342 } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) { 2343 unsigned PtrSize 2344 = getDataLayout()->getPointerSizeInBits(PT->getAddressSpace()); 2345 OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize); 2346 } else { 2347 OpInfo.ConstraintVT = MVT::getVT(OpTy, true); 2348 } 2349 } 2350 } 2351 2352 // If we have multiple alternative constraints, select the best alternative. 2353 if (!ConstraintOperands.empty()) { 2354 if (maCount) { 2355 unsigned bestMAIndex = 0; 2356 int bestWeight = -1; 2357 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match. 2358 int weight = -1; 2359 unsigned maIndex; 2360 // Compute the sums of the weights for each alternative, keeping track 2361 // of the best (highest weight) one so far. 2362 for (maIndex = 0; maIndex < maCount; ++maIndex) { 2363 int weightSum = 0; 2364 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2365 cIndex != eIndex; ++cIndex) { 2366 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2367 if (OpInfo.Type == InlineAsm::isClobber) 2368 continue; 2369 2370 // If this is an output operand with a matching input operand, 2371 // look up the matching input. If their types mismatch, e.g. one 2372 // is an integer, the other is floating point, or their sizes are 2373 // different, flag it as an maCantMatch. 2374 if (OpInfo.hasMatchingInput()) { 2375 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2376 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2377 if ((OpInfo.ConstraintVT.isInteger() != 2378 Input.ConstraintVT.isInteger()) || 2379 (OpInfo.ConstraintVT.getSizeInBits() != 2380 Input.ConstraintVT.getSizeInBits())) { 2381 weightSum = -1; // Can't match. 2382 break; 2383 } 2384 } 2385 } 2386 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex); 2387 if (weight == -1) { 2388 weightSum = -1; 2389 break; 2390 } 2391 weightSum += weight; 2392 } 2393 // Update best. 2394 if (weightSum > bestWeight) { 2395 bestWeight = weightSum; 2396 bestMAIndex = maIndex; 2397 } 2398 } 2399 2400 // Now select chosen alternative in each constraint. 2401 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2402 cIndex != eIndex; ++cIndex) { 2403 AsmOperandInfo& cInfo = ConstraintOperands[cIndex]; 2404 if (cInfo.Type == InlineAsm::isClobber) 2405 continue; 2406 cInfo.selectAlternative(bestMAIndex); 2407 } 2408 } 2409 } 2410 2411 // Check and hook up tied operands, choose constraint code to use. 2412 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2413 cIndex != eIndex; ++cIndex) { 2414 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2415 2416 // If this is an output operand with a matching input operand, look up the 2417 // matching input. If their types mismatch, e.g. one is an integer, the 2418 // other is floating point, or their sizes are different, flag it as an 2419 // error. 2420 if (OpInfo.hasMatchingInput()) { 2421 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2422 2423 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2424 std::pair<unsigned, const TargetRegisterClass *> MatchRC = 2425 getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode, 2426 OpInfo.ConstraintVT); 2427 std::pair<unsigned, const TargetRegisterClass *> InputRC = 2428 getRegForInlineAsmConstraint(TRI, Input.ConstraintCode, 2429 Input.ConstraintVT); 2430 if ((OpInfo.ConstraintVT.isInteger() != 2431 Input.ConstraintVT.isInteger()) || 2432 (MatchRC.second != InputRC.second)) { 2433 report_fatal_error("Unsupported asm: input constraint" 2434 " with a matching output constraint of" 2435 " incompatible type!"); 2436 } 2437 } 2438 2439 } 2440 } 2441 2442 return ConstraintOperands; 2443 } 2444 2445 2446 /// getConstraintGenerality - Return an integer indicating how general CT 2447 /// is. 2448 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2449 switch (CT) { 2450 case TargetLowering::C_Other: 2451 case TargetLowering::C_Unknown: 2452 return 0; 2453 case TargetLowering::C_Register: 2454 return 1; 2455 case TargetLowering::C_RegisterClass: 2456 return 2; 2457 case TargetLowering::C_Memory: 2458 return 3; 2459 } 2460 llvm_unreachable("Invalid constraint type"); 2461 } 2462 2463 /// Examine constraint type and operand type and determine a weight value. 2464 /// This object must already have been set up with the operand type 2465 /// and the current alternative constraint selected. 2466 TargetLowering::ConstraintWeight 2467 TargetLowering::getMultipleConstraintMatchWeight( 2468 AsmOperandInfo &info, int maIndex) const { 2469 InlineAsm::ConstraintCodeVector *rCodes; 2470 if (maIndex >= (int)info.multipleAlternatives.size()) 2471 rCodes = &info.Codes; 2472 else 2473 rCodes = &info.multipleAlternatives[maIndex].Codes; 2474 ConstraintWeight BestWeight = CW_Invalid; 2475 2476 // Loop over the options, keeping track of the most general one. 2477 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) { 2478 ConstraintWeight weight = 2479 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str()); 2480 if (weight > BestWeight) 2481 BestWeight = weight; 2482 } 2483 2484 return BestWeight; 2485 } 2486 2487 /// Examine constraint type and operand type and determine a weight value. 2488 /// This object must already have been set up with the operand type 2489 /// and the current alternative constraint selected. 2490 TargetLowering::ConstraintWeight 2491 TargetLowering::getSingleConstraintMatchWeight( 2492 AsmOperandInfo &info, const char *constraint) const { 2493 ConstraintWeight weight = CW_Invalid; 2494 Value *CallOperandVal = info.CallOperandVal; 2495 // If we don't have a value, we can't do a match, 2496 // but allow it at the lowest weight. 2497 if (!CallOperandVal) 2498 return CW_Default; 2499 // Look at the constraint type. 2500 switch (*constraint) { 2501 case 'i': // immediate integer. 2502 case 'n': // immediate integer with a known value. 2503 if (isa<ConstantInt>(CallOperandVal)) 2504 weight = CW_Constant; 2505 break; 2506 case 's': // non-explicit intregal immediate. 2507 if (isa<GlobalValue>(CallOperandVal)) 2508 weight = CW_Constant; 2509 break; 2510 case 'E': // immediate float if host format. 2511 case 'F': // immediate float. 2512 if (isa<ConstantFP>(CallOperandVal)) 2513 weight = CW_Constant; 2514 break; 2515 case '<': // memory operand with autodecrement. 2516 case '>': // memory operand with autoincrement. 2517 case 'm': // memory operand. 2518 case 'o': // offsettable memory operand 2519 case 'V': // non-offsettable memory operand 2520 weight = CW_Memory; 2521 break; 2522 case 'r': // general register. 2523 case 'g': // general register, memory operand or immediate integer. 2524 // note: Clang converts "g" to "imr". 2525 if (CallOperandVal->getType()->isIntegerTy()) 2526 weight = CW_Register; 2527 break; 2528 case 'X': // any operand. 2529 default: 2530 weight = CW_Default; 2531 break; 2532 } 2533 return weight; 2534 } 2535 2536 /// ChooseConstraint - If there are multiple different constraints that we 2537 /// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2538 /// This is somewhat tricky: constraints fall into four classes: 2539 /// Other -> immediates and magic values 2540 /// Register -> one specific register 2541 /// RegisterClass -> a group of regs 2542 /// Memory -> memory 2543 /// Ideally, we would pick the most specific constraint possible: if we have 2544 /// something that fits into a register, we would pick it. The problem here 2545 /// is that if we have something that could either be in a register or in 2546 /// memory that use of the register could cause selection of *other* 2547 /// operands to fail: they might only succeed if we pick memory. Because of 2548 /// this the heuristic we use is: 2549 /// 2550 /// 1) If there is an 'other' constraint, and if the operand is valid for 2551 /// that constraint, use it. This makes us take advantage of 'i' 2552 /// constraints when available. 2553 /// 2) Otherwise, pick the most general constraint present. This prefers 2554 /// 'm' over 'r', for example. 2555 /// 2556 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2557 const TargetLowering &TLI, 2558 SDValue Op, SelectionDAG *DAG) { 2559 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2560 unsigned BestIdx = 0; 2561 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2562 int BestGenerality = -1; 2563 2564 // Loop over the options, keeping track of the most general one. 2565 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2566 TargetLowering::ConstraintType CType = 2567 TLI.getConstraintType(OpInfo.Codes[i]); 2568 2569 // If this is an 'other' constraint, see if the operand is valid for it. 2570 // For example, on X86 we might have an 'rI' constraint. If the operand 2571 // is an integer in the range [0..31] we want to use I (saving a load 2572 // of a register), otherwise we must use 'r'. 2573 if (CType == TargetLowering::C_Other && Op.getNode()) { 2574 assert(OpInfo.Codes[i].size() == 1 && 2575 "Unhandled multi-letter 'other' constraint"); 2576 std::vector<SDValue> ResultOps; 2577 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i], 2578 ResultOps, *DAG); 2579 if (!ResultOps.empty()) { 2580 BestType = CType; 2581 BestIdx = i; 2582 break; 2583 } 2584 } 2585 2586 // Things with matching constraints can only be registers, per gcc 2587 // documentation. This mainly affects "g" constraints. 2588 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) 2589 continue; 2590 2591 // This constraint letter is more general than the previous one, use it. 2592 int Generality = getConstraintGenerality(CType); 2593 if (Generality > BestGenerality) { 2594 BestType = CType; 2595 BestIdx = i; 2596 BestGenerality = Generality; 2597 } 2598 } 2599 2600 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2601 OpInfo.ConstraintType = BestType; 2602 } 2603 2604 /// ComputeConstraintToUse - Determines the constraint code and constraint 2605 /// type to use for the specific AsmOperandInfo, setting 2606 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2607 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2608 SDValue Op, 2609 SelectionDAG *DAG) const { 2610 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2611 2612 // Single-letter constraints ('r') are very common. 2613 if (OpInfo.Codes.size() == 1) { 2614 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2615 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2616 } else { 2617 ChooseConstraint(OpInfo, *this, Op, DAG); 2618 } 2619 2620 // 'X' matches anything. 2621 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2622 // Labels and constants are handled elsewhere ('X' is the only thing 2623 // that matches labels). For Functions, the type here is the type of 2624 // the result, which is not what we want to look at; leave them alone. 2625 Value *v = OpInfo.CallOperandVal; 2626 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 2627 OpInfo.CallOperandVal = v; 2628 return; 2629 } 2630 2631 // Otherwise, try to resolve it to something we know about by looking at 2632 // the actual operand type. 2633 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2634 OpInfo.ConstraintCode = Repl; 2635 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2636 } 2637 } 2638 } 2639 2640 /// \brief Given an exact SDIV by a constant, create a multiplication 2641 /// with the multiplicative inverse of the constant. 2642 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl, 2643 SelectionDAG &DAG) const { 2644 ConstantSDNode *C = cast<ConstantSDNode>(Op2); 2645 APInt d = C->getAPIntValue(); 2646 assert(d != 0 && "Division by zero!"); 2647 2648 // Shift the value upfront if it is even, so the LSB is one. 2649 unsigned ShAmt = d.countTrailingZeros(); 2650 if (ShAmt) { 2651 // TODO: For UDIV use SRL instead of SRA. 2652 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType())); 2653 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, false, false, 2654 true); 2655 d = d.ashr(ShAmt); 2656 } 2657 2658 // Calculate the multiplicative inverse, using Newton's method. 2659 APInt t, xn = d; 2660 while ((t = d*xn) != 1) 2661 xn *= APInt(d.getBitWidth(), 2) - t; 2662 2663 Op2 = DAG.getConstant(xn, Op1.getValueType()); 2664 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2); 2665 } 2666 2667 /// \brief Given an ISD::SDIV node expressing a divide by constant, 2668 /// return a DAG expression to select that will generate the same value by 2669 /// multiplying by a magic number. 2670 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide". 2671 SDValue TargetLowering::BuildSDIV(SDNode *N, const APInt &Divisor, 2672 SelectionDAG &DAG, bool IsAfterLegalization, 2673 std::vector<SDNode *> *Created) const { 2674 assert(Created && "No vector to hold sdiv ops."); 2675 2676 EVT VT = N->getValueType(0); 2677 SDLoc dl(N); 2678 2679 // Check to see if we can do this. 2680 // FIXME: We should be more aggressive here. 2681 if (!isTypeLegal(VT)) 2682 return SDValue(); 2683 2684 APInt::ms magics = Divisor.magic(); 2685 2686 // Multiply the numerator (operand 0) by the magic value 2687 // FIXME: We should support doing a MUL in a wider type 2688 SDValue Q; 2689 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) : 2690 isOperationLegalOrCustom(ISD::MULHS, VT)) 2691 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 2692 DAG.getConstant(magics.m, VT)); 2693 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) : 2694 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 2695 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 2696 N->getOperand(0), 2697 DAG.getConstant(magics.m, VT)).getNode(), 1); 2698 else 2699 return SDValue(); // No mulhs or equvialent 2700 // If d > 0 and m < 0, add the numerator 2701 if (Divisor.isStrictlyPositive() && magics.m.isNegative()) { 2702 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 2703 Created->push_back(Q.getNode()); 2704 } 2705 // If d < 0 and m > 0, subtract the numerator. 2706 if (Divisor.isNegative() && magics.m.isStrictlyPositive()) { 2707 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 2708 Created->push_back(Q.getNode()); 2709 } 2710 // Shift right algebraic if shift value is nonzero 2711 if (magics.s > 0) { 2712 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 2713 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 2714 Created->push_back(Q.getNode()); 2715 } 2716 // Extract the sign bit and add it to the quotient 2717 SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q, 2718 DAG.getConstant(VT.getScalarSizeInBits() - 1, 2719 getShiftAmountTy(Q.getValueType()))); 2720 Created->push_back(T.getNode()); 2721 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 2722 } 2723 2724 /// \brief Given an ISD::UDIV node expressing a divide by constant, 2725 /// return a DAG expression to select that will generate the same value by 2726 /// multiplying by a magic number. 2727 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide". 2728 SDValue TargetLowering::BuildUDIV(SDNode *N, const APInt &Divisor, 2729 SelectionDAG &DAG, bool IsAfterLegalization, 2730 std::vector<SDNode *> *Created) const { 2731 assert(Created && "No vector to hold udiv ops."); 2732 2733 EVT VT = N->getValueType(0); 2734 SDLoc dl(N); 2735 2736 // Check to see if we can do this. 2737 // FIXME: We should be more aggressive here. 2738 if (!isTypeLegal(VT)) 2739 return SDValue(); 2740 2741 // FIXME: We should use a narrower constant when the upper 2742 // bits are known to be zero. 2743 APInt::mu magics = Divisor.magicu(); 2744 2745 SDValue Q = N->getOperand(0); 2746 2747 // If the divisor is even, we can avoid using the expensive fixup by shifting 2748 // the divided value upfront. 2749 if (magics.a != 0 && !Divisor[0]) { 2750 unsigned Shift = Divisor.countTrailingZeros(); 2751 Q = DAG.getNode(ISD::SRL, dl, VT, Q, 2752 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType()))); 2753 Created->push_back(Q.getNode()); 2754 2755 // Get magic number for the shifted divisor. 2756 magics = Divisor.lshr(Shift).magicu(Shift); 2757 assert(magics.a == 0 && "Should use cheap fixup now"); 2758 } 2759 2760 // Multiply the numerator (operand 0) by the magic value 2761 // FIXME: We should support doing a MUL in a wider type 2762 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : 2763 isOperationLegalOrCustom(ISD::MULHU, VT)) 2764 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT)); 2765 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) : 2766 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 2767 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q, 2768 DAG.getConstant(magics.m, VT)).getNode(), 1); 2769 else 2770 return SDValue(); // No mulhu or equvialent 2771 2772 Created->push_back(Q.getNode()); 2773 2774 if (magics.a == 0) { 2775 assert(magics.s < Divisor.getBitWidth() && 2776 "We shouldn't generate an undefined shift!"); 2777 return DAG.getNode(ISD::SRL, dl, VT, Q, 2778 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 2779 } else { 2780 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 2781 Created->push_back(NPQ.getNode()); 2782 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 2783 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType()))); 2784 Created->push_back(NPQ.getNode()); 2785 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 2786 Created->push_back(NPQ.getNode()); 2787 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 2788 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType()))); 2789 } 2790 } 2791 2792 bool TargetLowering:: 2793 verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const { 2794 if (!isa<ConstantSDNode>(Op.getOperand(0))) { 2795 DAG.getContext()->emitError("argument to '__builtin_return_address' must " 2796 "be a constant integer"); 2797 return true; 2798 } 2799 2800 return false; 2801 } 2802 2803 //===----------------------------------------------------------------------===// 2804 // Legalization Utilities 2805 //===----------------------------------------------------------------------===// 2806 2807 bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, 2808 SelectionDAG &DAG, SDValue LL, SDValue LH, 2809 SDValue RL, SDValue RH) const { 2810 EVT VT = N->getValueType(0); 2811 SDLoc dl(N); 2812 2813 bool HasMULHS = isOperationLegalOrCustom(ISD::MULHS, HiLoVT); 2814 bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT); 2815 bool HasSMUL_LOHI = isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT); 2816 bool HasUMUL_LOHI = isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT); 2817 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 2818 unsigned OuterBitSize = VT.getSizeInBits(); 2819 unsigned InnerBitSize = HiLoVT.getSizeInBits(); 2820 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 2821 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 2822 2823 // LL, LH, RL, and RH must be either all NULL or all set to a value. 2824 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) || 2825 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode())); 2826 2827 if (!LL.getNode() && !RL.getNode() && 2828 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) { 2829 LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(0)); 2830 RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(1)); 2831 } 2832 2833 if (!LL.getNode()) 2834 return false; 2835 2836 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 2837 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 2838 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 2839 // The inputs are both zero-extended. 2840 if (HasUMUL_LOHI) { 2841 // We can emit a umul_lohi. 2842 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL, 2843 RL); 2844 Hi = SDValue(Lo.getNode(), 1); 2845 return true; 2846 } 2847 if (HasMULHU) { 2848 // We can emit a mulhu+mul. 2849 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL); 2850 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL); 2851 return true; 2852 } 2853 } 2854 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 2855 // The input values are both sign-extended. 2856 if (HasSMUL_LOHI) { 2857 // We can emit a smul_lohi. 2858 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL, 2859 RL); 2860 Hi = SDValue(Lo.getNode(), 1); 2861 return true; 2862 } 2863 if (HasMULHS) { 2864 // We can emit a mulhs+mul. 2865 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL); 2866 Hi = DAG.getNode(ISD::MULHS, dl, HiLoVT, LL, RL); 2867 return true; 2868 } 2869 } 2870 2871 if (!LH.getNode() && !RH.getNode() && 2872 isOperationLegalOrCustom(ISD::SRL, VT) && 2873 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) { 2874 unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits(); 2875 SDValue Shift = DAG.getConstant(ShiftAmt, getShiftAmountTy(VT)); 2876 LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift); 2877 LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH); 2878 RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift); 2879 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH); 2880 } 2881 2882 if (!LH.getNode()) 2883 return false; 2884 2885 if (HasUMUL_LOHI) { 2886 // Lo,Hi = umul LHS, RHS. 2887 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl, 2888 DAG.getVTList(HiLoVT, HiLoVT), LL, RL); 2889 Lo = UMulLOHI; 2890 Hi = UMulLOHI.getValue(1); 2891 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH); 2892 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL); 2893 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH); 2894 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH); 2895 return true; 2896 } 2897 if (HasMULHU) { 2898 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL); 2899 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL); 2900 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH); 2901 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL); 2902 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH); 2903 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH); 2904 return true; 2905 } 2906 } 2907 return false; 2908 } 2909 2910 bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result, 2911 SelectionDAG &DAG) const { 2912 EVT VT = Node->getOperand(0).getValueType(); 2913 EVT NVT = Node->getValueType(0); 2914 SDLoc dl(SDValue(Node, 0)); 2915 2916 // FIXME: Only f32 to i64 conversions are supported. 2917 if (VT != MVT::f32 || NVT != MVT::i64) 2918 return false; 2919 2920 // Expand f32 -> i64 conversion 2921 // This algorithm comes from compiler-rt's implementation of fixsfdi: 2922 // https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c 2923 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), 2924 VT.getSizeInBits()); 2925 SDValue ExponentMask = DAG.getConstant(0x7F800000, IntVT); 2926 SDValue ExponentLoBit = DAG.getConstant(23, IntVT); 2927 SDValue Bias = DAG.getConstant(127, IntVT); 2928 SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()), 2929 IntVT); 2930 SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, IntVT); 2931 SDValue MantissaMask = DAG.getConstant(0x007FFFFF, IntVT); 2932 2933 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0)); 2934 2935 SDValue ExponentBits = DAG.getNode(ISD::SRL, dl, IntVT, 2936 DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask), 2937 DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT))); 2938 SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias); 2939 2940 SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT, 2941 DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask), 2942 DAG.getZExtOrTrunc(SignLowBit, dl, getShiftAmountTy(IntVT))); 2943 Sign = DAG.getSExtOrTrunc(Sign, dl, NVT); 2944 2945 SDValue R = DAG.getNode(ISD::OR, dl, IntVT, 2946 DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask), 2947 DAG.getConstant(0x00800000, IntVT)); 2948 2949 R = DAG.getZExtOrTrunc(R, dl, NVT); 2950 2951 2952 R = DAG.getSelectCC(dl, Exponent, ExponentLoBit, 2953 DAG.getNode(ISD::SHL, dl, NVT, R, 2954 DAG.getZExtOrTrunc( 2955 DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit), 2956 dl, getShiftAmountTy(IntVT))), 2957 DAG.getNode(ISD::SRL, dl, NVT, R, 2958 DAG.getZExtOrTrunc( 2959 DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent), 2960 dl, getShiftAmountTy(IntVT))), 2961 ISD::SETGT); 2962 2963 SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT, 2964 DAG.getNode(ISD::XOR, dl, NVT, R, Sign), 2965 Sign); 2966 2967 Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, IntVT), 2968 DAG.getConstant(0, NVT), Ret, ISD::SETLT); 2969 return true; 2970 } 2971