1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PPC implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCFrameLowering.h" 15 #include "PPCInstrBuilder.h" 16 #include "PPCInstrInfo.h" 17 #include "PPCMachineFunctionInfo.h" 18 #include "PPCSubtarget.h" 19 #include "PPCTargetMachine.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineModuleInfo.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/CodeGen/RegisterScavenging.h" 26 #include "llvm/IR/Function.h" 27 #include "llvm/Target/TargetOptions.h" 28 29 using namespace llvm; 30 31 /// VRRegNo - Map from a numbered VR register to its enum value. 32 /// 33 static const uint16_t VRRegNo[] = { 34 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 35 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 36 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 37 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 38 }; 39 40 static unsigned computeReturnSaveOffset(const PPCSubtarget &STI) { 41 if (STI.isDarwinABI()) 42 return STI.isPPC64() ? 16 : 8; 43 // SVR4 ABI: 44 return STI.isPPC64() ? 16 : 4; 45 } 46 47 static unsigned computeTOCSaveOffset(const PPCSubtarget &STI) { 48 return STI.isELFv2ABI() ? 24 : 40; 49 } 50 51 static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) { 52 // For the Darwin ABI: 53 // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area 54 // for saving the frame pointer (if needed.) While the published ABI has 55 // not used this slot since at least MacOSX 10.2, there is older code 56 // around that does use it, and that needs to continue to work. 57 if (STI.isDarwinABI()) 58 return STI.isPPC64() ? -8U : -4U; 59 60 // SVR4 ABI: First slot in the general register save area. 61 return STI.isPPC64() ? -8U : -4U; 62 } 63 64 static unsigned computeLinkageSize(const PPCSubtarget &STI) { 65 if (STI.isDarwinABI() || STI.isPPC64()) 66 return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4); 67 68 // SVR4 ABI: 69 return 8; 70 } 71 72 static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) { 73 if (STI.isDarwinABI()) 74 return STI.isPPC64() ? -16U : -8U; 75 76 // SVR4 ABI: First slot in the general register save area. 77 return STI.isPPC64() 78 ? -16U 79 : (STI.getTargetMachine().getRelocationModel() == Reloc::PIC_) 80 ? -12U 81 : -8U; 82 } 83 84 PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI) 85 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 86 STI.getPlatformStackAlignment(), 0), 87 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)), 88 TOCSaveOffset(computeTOCSaveOffset(Subtarget)), 89 FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)), 90 LinkageSize(computeLinkageSize(Subtarget)), 91 BasePointerSaveOffset(computeBasePointerSaveOffset(STI)) {} 92 93 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack. 94 const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots( 95 unsigned &NumEntries) const { 96 if (Subtarget.isDarwinABI()) { 97 NumEntries = 1; 98 if (Subtarget.isPPC64()) { 99 static const SpillSlot darwin64Offsets = {PPC::X31, -8}; 100 return &darwin64Offsets; 101 } else { 102 static const SpillSlot darwinOffsets = {PPC::R31, -4}; 103 return &darwinOffsets; 104 } 105 } 106 107 // Early exit if not using the SVR4 ABI. 108 if (!Subtarget.isSVR4ABI()) { 109 NumEntries = 0; 110 return nullptr; 111 } 112 113 // Note that the offsets here overlap, but this is fixed up in 114 // processFunctionBeforeFrameFinalized. 115 116 static const SpillSlot Offsets[] = { 117 // Floating-point register save area offsets. 118 {PPC::F31, -8}, 119 {PPC::F30, -16}, 120 {PPC::F29, -24}, 121 {PPC::F28, -32}, 122 {PPC::F27, -40}, 123 {PPC::F26, -48}, 124 {PPC::F25, -56}, 125 {PPC::F24, -64}, 126 {PPC::F23, -72}, 127 {PPC::F22, -80}, 128 {PPC::F21, -88}, 129 {PPC::F20, -96}, 130 {PPC::F19, -104}, 131 {PPC::F18, -112}, 132 {PPC::F17, -120}, 133 {PPC::F16, -128}, 134 {PPC::F15, -136}, 135 {PPC::F14, -144}, 136 137 // General register save area offsets. 138 {PPC::R31, -4}, 139 {PPC::R30, -8}, 140 {PPC::R29, -12}, 141 {PPC::R28, -16}, 142 {PPC::R27, -20}, 143 {PPC::R26, -24}, 144 {PPC::R25, -28}, 145 {PPC::R24, -32}, 146 {PPC::R23, -36}, 147 {PPC::R22, -40}, 148 {PPC::R21, -44}, 149 {PPC::R20, -48}, 150 {PPC::R19, -52}, 151 {PPC::R18, -56}, 152 {PPC::R17, -60}, 153 {PPC::R16, -64}, 154 {PPC::R15, -68}, 155 {PPC::R14, -72}, 156 157 // CR save area offset. We map each of the nonvolatile CR fields 158 // to the slot for CR2, which is the first of the nonvolatile CR 159 // fields to be assigned, so that we only allocate one save slot. 160 // See PPCRegisterInfo::hasReservedSpillSlot() for more information. 161 {PPC::CR2, -4}, 162 163 // VRSAVE save area offset. 164 {PPC::VRSAVE, -4}, 165 166 // Vector register save area 167 {PPC::V31, -16}, 168 {PPC::V30, -32}, 169 {PPC::V29, -48}, 170 {PPC::V28, -64}, 171 {PPC::V27, -80}, 172 {PPC::V26, -96}, 173 {PPC::V25, -112}, 174 {PPC::V24, -128}, 175 {PPC::V23, -144}, 176 {PPC::V22, -160}, 177 {PPC::V21, -176}, 178 {PPC::V20, -192}}; 179 180 static const SpillSlot Offsets64[] = { 181 // Floating-point register save area offsets. 182 {PPC::F31, -8}, 183 {PPC::F30, -16}, 184 {PPC::F29, -24}, 185 {PPC::F28, -32}, 186 {PPC::F27, -40}, 187 {PPC::F26, -48}, 188 {PPC::F25, -56}, 189 {PPC::F24, -64}, 190 {PPC::F23, -72}, 191 {PPC::F22, -80}, 192 {PPC::F21, -88}, 193 {PPC::F20, -96}, 194 {PPC::F19, -104}, 195 {PPC::F18, -112}, 196 {PPC::F17, -120}, 197 {PPC::F16, -128}, 198 {PPC::F15, -136}, 199 {PPC::F14, -144}, 200 201 // General register save area offsets. 202 {PPC::X31, -8}, 203 {PPC::X30, -16}, 204 {PPC::X29, -24}, 205 {PPC::X28, -32}, 206 {PPC::X27, -40}, 207 {PPC::X26, -48}, 208 {PPC::X25, -56}, 209 {PPC::X24, -64}, 210 {PPC::X23, -72}, 211 {PPC::X22, -80}, 212 {PPC::X21, -88}, 213 {PPC::X20, -96}, 214 {PPC::X19, -104}, 215 {PPC::X18, -112}, 216 {PPC::X17, -120}, 217 {PPC::X16, -128}, 218 {PPC::X15, -136}, 219 {PPC::X14, -144}, 220 221 // VRSAVE save area offset. 222 {PPC::VRSAVE, -4}, 223 224 // Vector register save area 225 {PPC::V31, -16}, 226 {PPC::V30, -32}, 227 {PPC::V29, -48}, 228 {PPC::V28, -64}, 229 {PPC::V27, -80}, 230 {PPC::V26, -96}, 231 {PPC::V25, -112}, 232 {PPC::V24, -128}, 233 {PPC::V23, -144}, 234 {PPC::V22, -160}, 235 {PPC::V21, -176}, 236 {PPC::V20, -192}}; 237 238 if (Subtarget.isPPC64()) { 239 NumEntries = array_lengthof(Offsets64); 240 241 return Offsets64; 242 } else { 243 NumEntries = array_lengthof(Offsets); 244 245 return Offsets; 246 } 247 } 248 249 /// RemoveVRSaveCode - We have found that this function does not need any code 250 /// to manipulate the VRSAVE register, even though it uses vector registers. 251 /// This can happen when the only registers used are known to be live in or out 252 /// of the function. Remove all of the VRSAVE related code from the function. 253 /// FIXME: The removal of the code results in a compile failure at -O0 when the 254 /// function contains a function call, as the GPR containing original VRSAVE 255 /// contents is spilled and reloaded around the call. Without the prolog code, 256 /// the spill instruction refers to an undefined register. This code needs 257 /// to account for all uses of that GPR. 258 static void RemoveVRSaveCode(MachineInstr *MI) { 259 MachineBasicBlock *Entry = MI->getParent(); 260 MachineFunction *MF = Entry->getParent(); 261 262 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 263 MachineBasicBlock::iterator MBBI = MI; 264 ++MBBI; 265 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 266 MBBI->eraseFromParent(); 267 268 bool RemovedAllMTVRSAVEs = true; 269 // See if we can find and remove the MTVRSAVE instruction from all of the 270 // epilog blocks. 271 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 272 // If last instruction is a return instruction, add an epilogue 273 if (!I->empty() && I->back().isReturn()) { 274 bool FoundIt = false; 275 for (MBBI = I->end(); MBBI != I->begin(); ) { 276 --MBBI; 277 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 278 MBBI->eraseFromParent(); // remove it. 279 FoundIt = true; 280 break; 281 } 282 } 283 RemovedAllMTVRSAVEs &= FoundIt; 284 } 285 } 286 287 // If we found and removed all MTVRSAVE instructions, remove the read of 288 // VRSAVE as well. 289 if (RemovedAllMTVRSAVEs) { 290 MBBI = MI; 291 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 292 --MBBI; 293 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 294 MBBI->eraseFromParent(); 295 } 296 297 // Finally, nuke the UPDATE_VRSAVE. 298 MI->eraseFromParent(); 299 } 300 301 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 302 // instruction selector. Based on the vector registers that have been used, 303 // transform this into the appropriate ORI instruction. 304 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 305 MachineFunction *MF = MI->getParent()->getParent(); 306 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); 307 DebugLoc dl = MI->getDebugLoc(); 308 309 unsigned UsedRegMask = 0; 310 for (unsigned i = 0; i != 32; ++i) 311 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 312 UsedRegMask |= 1 << (31-i); 313 314 // Live in and live out values already must be in the mask, so don't bother 315 // marking them. 316 for (MachineRegisterInfo::livein_iterator 317 I = MF->getRegInfo().livein_begin(), 318 E = MF->getRegInfo().livein_end(); I != E; ++I) { 319 unsigned RegNo = TRI->getEncodingValue(I->first); 320 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 321 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 322 } 323 324 // Live out registers appear as use operands on return instructions. 325 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end(); 326 UsedRegMask != 0 && BI != BE; ++BI) { 327 const MachineBasicBlock &MBB = *BI; 328 if (MBB.empty() || !MBB.back().isReturn()) 329 continue; 330 const MachineInstr &Ret = MBB.back(); 331 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) { 332 const MachineOperand &MO = Ret.getOperand(I); 333 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg())) 334 continue; 335 unsigned RegNo = TRI->getEncodingValue(MO.getReg()); 336 UsedRegMask &= ~(1 << (31-RegNo)); 337 } 338 } 339 340 // If no registers are used, turn this into a copy. 341 if (UsedRegMask == 0) { 342 // Remove all VRSAVE code. 343 RemoveVRSaveCode(MI); 344 return; 345 } 346 347 unsigned SrcReg = MI->getOperand(1).getReg(); 348 unsigned DstReg = MI->getOperand(0).getReg(); 349 350 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 351 if (DstReg != SrcReg) 352 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 353 .addReg(SrcReg) 354 .addImm(UsedRegMask); 355 else 356 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 357 .addReg(SrcReg, RegState::Kill) 358 .addImm(UsedRegMask); 359 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 360 if (DstReg != SrcReg) 361 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 362 .addReg(SrcReg) 363 .addImm(UsedRegMask >> 16); 364 else 365 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 366 .addReg(SrcReg, RegState::Kill) 367 .addImm(UsedRegMask >> 16); 368 } else { 369 if (DstReg != SrcReg) 370 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 371 .addReg(SrcReg) 372 .addImm(UsedRegMask >> 16); 373 else 374 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 375 .addReg(SrcReg, RegState::Kill) 376 .addImm(UsedRegMask >> 16); 377 378 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 379 .addReg(DstReg, RegState::Kill) 380 .addImm(UsedRegMask & 0xFFFF); 381 } 382 383 // Remove the old UPDATE_VRSAVE instruction. 384 MI->eraseFromParent(); 385 } 386 387 static bool spillsCR(const MachineFunction &MF) { 388 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 389 return FuncInfo->isCRSpilled(); 390 } 391 392 static bool spillsVRSAVE(const MachineFunction &MF) { 393 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 394 return FuncInfo->isVRSAVESpilled(); 395 } 396 397 static bool hasSpills(const MachineFunction &MF) { 398 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 399 return FuncInfo->hasSpills(); 400 } 401 402 static bool hasNonRISpills(const MachineFunction &MF) { 403 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 404 return FuncInfo->hasNonRISpills(); 405 } 406 407 /// MustSaveLR - Return true if this function requires that we save the LR 408 /// register onto the stack in the prolog and restore it in the epilog of the 409 /// function. 410 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 411 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 412 413 // We need a save/restore of LR if there is any def of LR (which is 414 // defined by calls, including the PIC setup sequence), or if there is 415 // some use of the LR stack slot (e.g. for builtin_return_address). 416 // (LR comes in 32 and 64 bit versions.) 417 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 418 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 419 } 420 421 /// determineFrameLayout - Determine the size of the frame and maximum call 422 /// frame size. 423 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF, 424 bool UpdateMF, 425 bool UseEstimate) const { 426 MachineFrameInfo *MFI = MF.getFrameInfo(); 427 428 // Get the number of bytes to allocate from the FrameInfo 429 unsigned FrameSize = 430 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize(); 431 432 // Get stack alignments. The frame must be aligned to the greatest of these: 433 unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI 434 unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame 435 unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1; 436 437 const PPCRegisterInfo *RegInfo = 438 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 439 440 // If we are a leaf function, and use up to 224 bytes of stack space, 441 // don't have a frame pointer, calls, or dynamic alloca then we do not need 442 // to adjust the stack pointer (we fit in the Red Zone). 443 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate 444 // stackless code if all local vars are reg-allocated. 445 bool DisableRedZone = MF.getFunction()->hasFnAttribute(Attribute::NoRedZone); 446 unsigned LR = RegInfo->getRARegister(); 447 if (!DisableRedZone && 448 (Subtarget.isPPC64() || // 32-bit SVR4, no stack- 449 !Subtarget.isSVR4ABI() || // allocated locals. 450 FrameSize == 0) && 451 FrameSize <= 224 && // Fits in red zone. 452 !MFI->hasVarSizedObjects() && // No dynamic alloca. 453 !MFI->adjustsStack() && // No calls. 454 !MustSaveLR(MF, LR) && 455 !RegInfo->hasBasePointer(MF)) { // No special alignment. 456 // No need for frame 457 if (UpdateMF) 458 MFI->setStackSize(0); 459 return 0; 460 } 461 462 // Get the maximum call frame size of all the calls. 463 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 464 465 // Maximum call frame needs to be at least big enough for linkage area. 466 unsigned minCallFrameSize = getLinkageSize(); 467 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 468 469 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 470 // that allocations will be aligned. 471 if (MFI->hasVarSizedObjects()) 472 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 473 474 // Update maximum call frame size. 475 if (UpdateMF) 476 MFI->setMaxCallFrameSize(maxCallFrameSize); 477 478 // Include call frame size in total. 479 FrameSize += maxCallFrameSize; 480 481 // Make sure the frame is aligned. 482 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 483 484 // Update frame info. 485 if (UpdateMF) 486 MFI->setStackSize(FrameSize); 487 488 return FrameSize; 489 } 490 491 // hasFP - Return true if the specified function actually has a dedicated frame 492 // pointer register. 493 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const { 494 const MachineFrameInfo *MFI = MF.getFrameInfo(); 495 // FIXME: This is pretty much broken by design: hasFP() might be called really 496 // early, before the stack layout was calculated and thus hasFP() might return 497 // true or false here depending on the time of call. 498 return (MFI->getStackSize()) && needsFP(MF); 499 } 500 501 // needsFP - Return true if the specified function should have a dedicated frame 502 // pointer register. This is true if the function has variable sized allocas or 503 // if frame pointer elimination is disabled. 504 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const { 505 const MachineFrameInfo *MFI = MF.getFrameInfo(); 506 507 // Naked functions have no stack frame pushed, so we don't have a frame 508 // pointer. 509 if (MF.getFunction()->hasFnAttribute(Attribute::Naked)) 510 return false; 511 512 return MF.getTarget().Options.DisableFramePointerElim(MF) || 513 MFI->hasVarSizedObjects() || 514 MFI->hasStackMap() || MFI->hasPatchPoint() || 515 (MF.getTarget().Options.GuaranteedTailCallOpt && 516 MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 517 } 518 519 void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const { 520 bool is31 = needsFP(MF); 521 unsigned FPReg = is31 ? PPC::R31 : PPC::R1; 522 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1; 523 524 const PPCRegisterInfo *RegInfo = 525 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 526 bool HasBP = RegInfo->hasBasePointer(MF); 527 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg; 528 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg; 529 530 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); 531 BI != BE; ++BI) 532 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) { 533 --MBBI; 534 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) { 535 MachineOperand &MO = MBBI->getOperand(I); 536 if (!MO.isReg()) 537 continue; 538 539 switch (MO.getReg()) { 540 case PPC::FP: 541 MO.setReg(FPReg); 542 break; 543 case PPC::FP8: 544 MO.setReg(FP8Reg); 545 break; 546 case PPC::BP: 547 MO.setReg(BPReg); 548 break; 549 case PPC::BP8: 550 MO.setReg(BP8Reg); 551 break; 552 553 } 554 } 555 } 556 } 557 558 void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { 559 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 560 MachineBasicBlock::iterator MBBI = MBB.begin(); 561 MachineFrameInfo *MFI = MF.getFrameInfo(); 562 const PPCInstrInfo &TII = 563 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 564 const PPCRegisterInfo *RegInfo = 565 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 566 567 MachineModuleInfo &MMI = MF.getMMI(); 568 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); 569 DebugLoc dl; 570 bool needsCFI = MMI.hasDebugInfo() || 571 MF.getFunction()->needsUnwindTableEntry(); 572 573 // Get processor type. 574 bool isPPC64 = Subtarget.isPPC64(); 575 // Get the ABI. 576 bool isSVR4ABI = Subtarget.isSVR4ABI(); 577 bool isELFv2ABI = Subtarget.isELFv2ABI(); 578 assert((Subtarget.isDarwinABI() || isSVR4ABI) && 579 "Currently only Darwin and SVR4 ABIs are supported for PowerPC."); 580 581 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 582 // process it. 583 if (!isSVR4ABI) 584 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 585 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 586 HandleVRSaveUpdate(MBBI, TII); 587 break; 588 } 589 } 590 591 // Move MBBI back to the beginning of the function. 592 MBBI = MBB.begin(); 593 594 // Work out frame sizes. 595 unsigned FrameSize = determineFrameLayout(MF); 596 int NegFrameSize = -FrameSize; 597 if (!isInt<32>(NegFrameSize)) 598 llvm_unreachable("Unhandled stack size!"); 599 600 if (MFI->isFrameAddressTaken()) 601 replaceFPWithRealFP(MF); 602 603 // Check if the link register (LR) must be saved. 604 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 605 bool MustSaveLR = FI->mustSaveLR(); 606 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs(); 607 // Do we have a frame pointer and/or base pointer for this function? 608 bool HasFP = hasFP(MF); 609 bool HasBP = RegInfo->hasBasePointer(MF); 610 611 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1; 612 unsigned BPReg = RegInfo->getBaseRegister(MF); 613 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 614 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR; 615 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0; 616 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg 617 // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.) 618 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8 619 : PPC::MFLR ); 620 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD 621 : PPC::STW ); 622 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU 623 : PPC::STWU ); 624 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX 625 : PPC::STWUX); 626 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8 627 : PPC::LIS ); 628 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8 629 : PPC::ORI ); 630 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8 631 : PPC::OR ); 632 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8 633 : PPC::SUBFC); 634 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8 635 : PPC::SUBFIC); 636 637 // Regarding this assert: Even though LR is saved in the caller's frame (i.e., 638 // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no 639 // Red Zone, an asynchronous event (a form of "callee") could claim a frame & 640 // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR. 641 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) && 642 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4."); 643 644 int LROffset = getReturnSaveOffset(); 645 646 int FPOffset = 0; 647 if (HasFP) { 648 if (isSVR4ABI) { 649 MachineFrameInfo *FFI = MF.getFrameInfo(); 650 int FPIndex = FI->getFramePointerSaveIndex(); 651 assert(FPIndex && "No Frame Pointer Save Slot!"); 652 FPOffset = FFI->getObjectOffset(FPIndex); 653 } else { 654 FPOffset = getFramePointerSaveOffset(); 655 } 656 } 657 658 int BPOffset = 0; 659 if (HasBP) { 660 if (isSVR4ABI) { 661 MachineFrameInfo *FFI = MF.getFrameInfo(); 662 int BPIndex = FI->getBasePointerSaveIndex(); 663 assert(BPIndex && "No Base Pointer Save Slot!"); 664 BPOffset = FFI->getObjectOffset(BPIndex); 665 } else { 666 BPOffset = getBasePointerSaveOffset(); 667 } 668 } 669 670 int PBPOffset = 0; 671 if (FI->usesPICBase()) { 672 MachineFrameInfo *FFI = MF.getFrameInfo(); 673 int PBPIndex = FI->getPICBasePointerSaveIndex(); 674 assert(PBPIndex && "No PIC Base Pointer Save Slot!"); 675 PBPOffset = FFI->getObjectOffset(PBPIndex); 676 } 677 678 // Get stack alignments. 679 unsigned MaxAlign = MFI->getMaxAlignment(); 680 if (HasBP && MaxAlign > 1) 681 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 682 "Invalid alignment!"); 683 684 // Frames of 32KB & larger require special handling because they cannot be 685 // indexed into with a simple STDU/STWU/STD/STW immediate offset operand. 686 bool isLargeFrame = !isInt<16>(NegFrameSize); 687 688 if (MustSaveLR) 689 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg); 690 691 assert((isPPC64 || MustSaveCRs.empty()) && 692 "Prologue CR saving supported only in 64-bit mode"); 693 694 if (!MustSaveCRs.empty()) { // will only occur for PPC64 695 // FIXME: In the ELFv2 ABI, we are not required to save all CR fields. 696 // If only one or two CR fields are clobbered, it could be more 697 // efficient to use mfocrf to selectively save just those fields. 698 MachineInstrBuilder MIB = 699 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg); 700 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 701 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill); 702 } 703 704 if (HasFP) 705 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 706 BuildMI(MBB, MBBI, dl, StoreInst) 707 .addReg(FPReg) 708 .addImm(FPOffset) 709 .addReg(SPReg); 710 711 if (FI->usesPICBase()) 712 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 713 BuildMI(MBB, MBBI, dl, StoreInst) 714 .addReg(PPC::R30) 715 .addImm(PBPOffset) 716 .addReg(SPReg); 717 718 if (HasBP) 719 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 720 BuildMI(MBB, MBBI, dl, StoreInst) 721 .addReg(BPReg) 722 .addImm(BPOffset) 723 .addReg(SPReg); 724 725 if (MustSaveLR) 726 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 727 BuildMI(MBB, MBBI, dl, StoreInst) 728 .addReg(ScratchReg) 729 .addImm(LROffset) 730 .addReg(SPReg); 731 732 if (!MustSaveCRs.empty()) // will only occur for PPC64 733 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8)) 734 .addReg(TempReg, getKillRegState(true)) 735 .addImm(8) 736 .addReg(SPReg); 737 738 // Skip the rest if this is a leaf function & all spills fit in the Red Zone. 739 if (!FrameSize) return; 740 741 // Adjust stack pointer: r1 += NegFrameSize. 742 // If there is a preferred stack alignment, align R1 now 743 744 if (HasBP) { 745 // Save a copy of r1 as the base pointer. 746 BuildMI(MBB, MBBI, dl, OrInst, BPReg) 747 .addReg(SPReg) 748 .addReg(SPReg); 749 } 750 751 if (HasBP && MaxAlign > 1) { 752 if (isPPC64) 753 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg) 754 .addReg(SPReg) 755 .addImm(0) 756 .addImm(64 - Log2_32(MaxAlign)); 757 else // PPC32... 758 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg) 759 .addReg(SPReg) 760 .addImm(0) 761 .addImm(32 - Log2_32(MaxAlign)) 762 .addImm(31); 763 if (!isLargeFrame) { 764 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg) 765 .addReg(ScratchReg, RegState::Kill) 766 .addImm(NegFrameSize); 767 } else { 768 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg) 769 .addImm(NegFrameSize >> 16); 770 BuildMI(MBB, MBBI, dl, OrImmInst, TempReg) 771 .addReg(TempReg, RegState::Kill) 772 .addImm(NegFrameSize & 0xFFFF); 773 BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg) 774 .addReg(ScratchReg, RegState::Kill) 775 .addReg(TempReg, RegState::Kill); 776 } 777 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg) 778 .addReg(SPReg, RegState::Kill) 779 .addReg(SPReg) 780 .addReg(ScratchReg); 781 782 } else if (!isLargeFrame) { 783 BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg) 784 .addReg(SPReg) 785 .addImm(NegFrameSize) 786 .addReg(SPReg); 787 788 } else { 789 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 790 .addImm(NegFrameSize >> 16); 791 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 792 .addReg(ScratchReg, RegState::Kill) 793 .addImm(NegFrameSize & 0xFFFF); 794 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg) 795 .addReg(SPReg, RegState::Kill) 796 .addReg(SPReg) 797 .addReg(ScratchReg); 798 } 799 800 // Add Call Frame Information for the instructions we generated above. 801 if (needsCFI) { 802 unsigned CFIIndex; 803 804 if (HasBP) { 805 // Define CFA in terms of BP. Do this in preference to using FP/SP, 806 // because if the stack needed aligning then CFA won't be at a fixed 807 // offset from FP/SP. 808 unsigned Reg = MRI->getDwarfRegNum(BPReg, true); 809 CFIIndex = MMI.addFrameInst( 810 MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); 811 } else { 812 // Adjust the definition of CFA to account for the change in SP. 813 assert(NegFrameSize); 814 CFIIndex = MMI.addFrameInst( 815 MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize)); 816 } 817 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 818 .addCFIIndex(CFIIndex); 819 820 if (HasFP) { 821 // Describe where FP was saved, at a fixed offset from CFA. 822 unsigned Reg = MRI->getDwarfRegNum(FPReg, true); 823 CFIIndex = MMI.addFrameInst( 824 MCCFIInstruction::createOffset(nullptr, Reg, FPOffset)); 825 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 826 .addCFIIndex(CFIIndex); 827 } 828 829 if (FI->usesPICBase()) { 830 // Describe where FP was saved, at a fixed offset from CFA. 831 unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true); 832 CFIIndex = MMI.addFrameInst( 833 MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset)); 834 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 835 .addCFIIndex(CFIIndex); 836 } 837 838 if (HasBP) { 839 // Describe where BP was saved, at a fixed offset from CFA. 840 unsigned Reg = MRI->getDwarfRegNum(BPReg, true); 841 CFIIndex = MMI.addFrameInst( 842 MCCFIInstruction::createOffset(nullptr, Reg, BPOffset)); 843 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 844 .addCFIIndex(CFIIndex); 845 } 846 847 if (MustSaveLR) { 848 // Describe where LR was saved, at a fixed offset from CFA. 849 unsigned Reg = MRI->getDwarfRegNum(LRReg, true); 850 CFIIndex = MMI.addFrameInst( 851 MCCFIInstruction::createOffset(nullptr, Reg, LROffset)); 852 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 853 .addCFIIndex(CFIIndex); 854 } 855 } 856 857 // If there is a frame pointer, copy R1 into R31 858 if (HasFP) { 859 BuildMI(MBB, MBBI, dl, OrInst, FPReg) 860 .addReg(SPReg) 861 .addReg(SPReg); 862 863 if (!HasBP && needsCFI) { 864 // Change the definition of CFA from SP+offset to FP+offset, because SP 865 // will change at every alloca. 866 unsigned Reg = MRI->getDwarfRegNum(FPReg, true); 867 unsigned CFIIndex = MMI.addFrameInst( 868 MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); 869 870 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 871 .addCFIIndex(CFIIndex); 872 } 873 } 874 875 if (needsCFI) { 876 // Describe where callee saved registers were saved, at fixed offsets from 877 // CFA. 878 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 879 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 880 unsigned Reg = CSI[I].getReg(); 881 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 882 883 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just 884 // subregisters of CR2. We just need to emit a move of CR2. 885 if (PPC::CRBITRCRegClass.contains(Reg)) 886 continue; 887 888 // For SVR4, don't emit a move for the CR spill slot if we haven't 889 // spilled CRs. 890 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4) 891 && MustSaveCRs.empty()) 892 continue; 893 894 // For 64-bit SVR4 when we have spilled CRs, the spill location 895 // is SP+8, not a frame-relative slot. 896 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 897 // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for 898 // the whole CR word. In the ELFv2 ABI, every CR that was 899 // actually saved gets its own CFI record. 900 unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2; 901 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 902 nullptr, MRI->getDwarfRegNum(CRReg, true), 8)); 903 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 904 .addCFIIndex(CFIIndex); 905 continue; 906 } 907 908 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 909 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 910 nullptr, MRI->getDwarfRegNum(Reg, true), Offset)); 911 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 912 .addCFIIndex(CFIIndex); 913 } 914 } 915 } 916 917 void PPCFrameLowering::emitEpilogue(MachineFunction &MF, 918 MachineBasicBlock &MBB) const { 919 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 920 assert(MBBI != MBB.end() && "Returning block has no terminator"); 921 const PPCInstrInfo &TII = 922 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 923 const PPCRegisterInfo *RegInfo = 924 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 925 926 unsigned RetOpcode = MBBI->getOpcode(); 927 DebugLoc dl; 928 929 assert((RetOpcode == PPC::BLR || 930 RetOpcode == PPC::BLR8 || 931 RetOpcode == PPC::TCRETURNri || 932 RetOpcode == PPC::TCRETURNdi || 933 RetOpcode == PPC::TCRETURNai || 934 RetOpcode == PPC::TCRETURNri8 || 935 RetOpcode == PPC::TCRETURNdi8 || 936 RetOpcode == PPC::TCRETURNai8) && 937 "Can only insert epilog into returning blocks"); 938 939 // Get alignment info so we know how to restore the SP. 940 const MachineFrameInfo *MFI = MF.getFrameInfo(); 941 942 // Get the number of bytes allocated from the FrameInfo. 943 int FrameSize = MFI->getStackSize(); 944 945 // Get processor type. 946 bool isPPC64 = Subtarget.isPPC64(); 947 // Get the ABI. 948 bool isSVR4ABI = Subtarget.isSVR4ABI(); 949 950 // Check if the link register (LR) has been saved. 951 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 952 bool MustSaveLR = FI->mustSaveLR(); 953 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs(); 954 // Do we have a frame pointer and/or base pointer for this function? 955 bool HasFP = hasFP(MF); 956 bool HasBP = RegInfo->hasBasePointer(MF); 957 958 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1; 959 unsigned BPReg = RegInfo->getBaseRegister(MF); 960 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 961 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0; 962 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg 963 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8 964 : PPC::MTLR ); 965 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD 966 : PPC::LWZ ); 967 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8 968 : PPC::LIS ); 969 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8 970 : PPC::ORI ); 971 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8 972 : PPC::ADDI ); 973 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8 974 : PPC::ADD4 ); 975 976 int LROffset = getReturnSaveOffset(); 977 978 int FPOffset = 0; 979 if (HasFP) { 980 if (isSVR4ABI) { 981 MachineFrameInfo *FFI = MF.getFrameInfo(); 982 int FPIndex = FI->getFramePointerSaveIndex(); 983 assert(FPIndex && "No Frame Pointer Save Slot!"); 984 FPOffset = FFI->getObjectOffset(FPIndex); 985 } else { 986 FPOffset = getFramePointerSaveOffset(); 987 } 988 } 989 990 int BPOffset = 0; 991 if (HasBP) { 992 if (isSVR4ABI) { 993 MachineFrameInfo *FFI = MF.getFrameInfo(); 994 int BPIndex = FI->getBasePointerSaveIndex(); 995 assert(BPIndex && "No Base Pointer Save Slot!"); 996 BPOffset = FFI->getObjectOffset(BPIndex); 997 } else { 998 BPOffset = getBasePointerSaveOffset(); 999 } 1000 } 1001 1002 int PBPOffset = 0; 1003 if (FI->usesPICBase()) { 1004 MachineFrameInfo *FFI = MF.getFrameInfo(); 1005 int PBPIndex = FI->getPICBasePointerSaveIndex(); 1006 assert(PBPIndex && "No PIC Base Pointer Save Slot!"); 1007 PBPOffset = FFI->getObjectOffset(PBPIndex); 1008 } 1009 1010 bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 1011 RetOpcode == PPC::TCRETURNdi || 1012 RetOpcode == PPC::TCRETURNai || 1013 RetOpcode == PPC::TCRETURNri8 || 1014 RetOpcode == PPC::TCRETURNdi8 || 1015 RetOpcode == PPC::TCRETURNai8; 1016 1017 if (UsesTCRet) { 1018 int MaxTCRetDelta = FI->getTailCallSPDelta(); 1019 MachineOperand &StackAdjust = MBBI->getOperand(1); 1020 assert(StackAdjust.isImm() && "Expecting immediate value."); 1021 // Adjust stack pointer. 1022 int StackAdj = StackAdjust.getImm(); 1023 int Delta = StackAdj - MaxTCRetDelta; 1024 assert((Delta >= 0) && "Delta must be positive"); 1025 if (MaxTCRetDelta>0) 1026 FrameSize += (StackAdj +Delta); 1027 else 1028 FrameSize += StackAdj; 1029 } 1030 1031 // Frames of 32KB & larger require special handling because they cannot be 1032 // indexed into with a simple LD/LWZ immediate offset operand. 1033 bool isLargeFrame = !isInt<16>(FrameSize); 1034 1035 if (FrameSize) { 1036 // In the prologue, the loaded (or persistent) stack pointer value is offset 1037 // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now. 1038 1039 // If this function contained a fastcc call and GuaranteedTailCallOpt is 1040 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 1041 // call which invalidates the stack pointer value in SP(0). So we use the 1042 // value of R31 in this case. 1043 if (FI->hasFastCall()) { 1044 assert(HasFP && "Expecting a valid frame pointer."); 1045 if (!isLargeFrame) { 1046 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 1047 .addReg(FPReg).addImm(FrameSize); 1048 } else { 1049 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 1050 .addImm(FrameSize >> 16); 1051 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 1052 .addReg(ScratchReg, RegState::Kill) 1053 .addImm(FrameSize & 0xFFFF); 1054 BuildMI(MBB, MBBI, dl, AddInst) 1055 .addReg(SPReg) 1056 .addReg(FPReg) 1057 .addReg(ScratchReg); 1058 } 1059 } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) { 1060 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 1061 .addReg(SPReg) 1062 .addImm(FrameSize); 1063 } else { 1064 BuildMI(MBB, MBBI, dl, LoadInst, SPReg) 1065 .addImm(0) 1066 .addReg(SPReg); 1067 } 1068 1069 } 1070 1071 if (MustSaveLR) 1072 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg) 1073 .addImm(LROffset) 1074 .addReg(SPReg); 1075 1076 assert((isPPC64 || MustSaveCRs.empty()) && 1077 "Epilogue CR restoring supported only in 64-bit mode"); 1078 1079 if (!MustSaveCRs.empty()) // will only occur for PPC64 1080 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg) 1081 .addImm(8) 1082 .addReg(SPReg); 1083 1084 if (HasFP) 1085 BuildMI(MBB, MBBI, dl, LoadInst, FPReg) 1086 .addImm(FPOffset) 1087 .addReg(SPReg); 1088 1089 if (FI->usesPICBase()) 1090 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 1091 BuildMI(MBB, MBBI, dl, LoadInst) 1092 .addReg(PPC::R30) 1093 .addImm(PBPOffset) 1094 .addReg(SPReg); 1095 1096 if (HasBP) 1097 BuildMI(MBB, MBBI, dl, LoadInst, BPReg) 1098 .addImm(BPOffset) 1099 .addReg(SPReg); 1100 1101 if (!MustSaveCRs.empty()) // will only occur for PPC64 1102 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 1103 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i]) 1104 .addReg(TempReg, getKillRegState(i == e-1)); 1105 1106 if (MustSaveLR) 1107 BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg); 1108 1109 // Callee pop calling convention. Pop parameter/linkage area. Used for tail 1110 // call optimization 1111 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1112 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) && 1113 MF.getFunction()->getCallingConv() == CallingConv::Fast) { 1114 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1115 unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 1116 1117 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 1118 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 1119 .addReg(SPReg).addImm(CallerAllocatedAmt); 1120 } else { 1121 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 1122 .addImm(CallerAllocatedAmt >> 16); 1123 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 1124 .addReg(ScratchReg, RegState::Kill) 1125 .addImm(CallerAllocatedAmt & 0xFFFF); 1126 BuildMI(MBB, MBBI, dl, AddInst) 1127 .addReg(SPReg) 1128 .addReg(FPReg) 1129 .addReg(ScratchReg); 1130 } 1131 } else if (RetOpcode == PPC::TCRETURNdi) { 1132 MBBI = MBB.getLastNonDebugInstr(); 1133 MachineOperand &JumpTarget = MBBI->getOperand(0); 1134 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 1135 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1136 } else if (RetOpcode == PPC::TCRETURNri) { 1137 MBBI = MBB.getLastNonDebugInstr(); 1138 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1139 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 1140 } else if (RetOpcode == PPC::TCRETURNai) { 1141 MBBI = MBB.getLastNonDebugInstr(); 1142 MachineOperand &JumpTarget = MBBI->getOperand(0); 1143 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 1144 } else if (RetOpcode == PPC::TCRETURNdi8) { 1145 MBBI = MBB.getLastNonDebugInstr(); 1146 MachineOperand &JumpTarget = MBBI->getOperand(0); 1147 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 1148 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1149 } else if (RetOpcode == PPC::TCRETURNri8) { 1150 MBBI = MBB.getLastNonDebugInstr(); 1151 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1152 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 1153 } else if (RetOpcode == PPC::TCRETURNai8) { 1154 MBBI = MBB.getLastNonDebugInstr(); 1155 MachineOperand &JumpTarget = MBBI->getOperand(0); 1156 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 1157 } 1158 } 1159 1160 void 1161 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 1162 RegScavenger *) const { 1163 const PPCRegisterInfo *RegInfo = 1164 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 1165 1166 // Save and clear the LR state. 1167 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1168 unsigned LR = RegInfo->getRARegister(); 1169 FI->setMustSaveLR(MustSaveLR(MF, LR)); 1170 MachineRegisterInfo &MRI = MF.getRegInfo(); 1171 MRI.setPhysRegUnused(LR); 1172 1173 // Save R31 if necessary 1174 int FPSI = FI->getFramePointerSaveIndex(); 1175 bool isPPC64 = Subtarget.isPPC64(); 1176 bool isDarwinABI = Subtarget.isDarwinABI(); 1177 MachineFrameInfo *MFI = MF.getFrameInfo(); 1178 1179 // If the frame pointer save index hasn't been defined yet. 1180 if (!FPSI && needsFP(MF)) { 1181 // Find out what the fix offset of the frame pointer save area. 1182 int FPOffset = getFramePointerSaveOffset(); 1183 // Allocate the frame index for frame pointer save area. 1184 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 1185 // Save the result. 1186 FI->setFramePointerSaveIndex(FPSI); 1187 } 1188 1189 int BPSI = FI->getBasePointerSaveIndex(); 1190 if (!BPSI && RegInfo->hasBasePointer(MF)) { 1191 int BPOffset = getBasePointerSaveOffset(); 1192 // Allocate the frame index for the base pointer save area. 1193 BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true); 1194 // Save the result. 1195 FI->setBasePointerSaveIndex(BPSI); 1196 } 1197 1198 // Reserve stack space for the PIC Base register (R30). 1199 // Only used in SVR4 32-bit. 1200 if (FI->usesPICBase()) { 1201 int PBPSI = FI->getPICBasePointerSaveIndex(); 1202 PBPSI = MFI->CreateFixedObject(4, -8, true); 1203 FI->setPICBasePointerSaveIndex(PBPSI); 1204 } 1205 1206 // Reserve stack space to move the linkage area to in case of a tail call. 1207 int TCSPDelta = 0; 1208 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1209 (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 1210 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); 1211 } 1212 1213 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the 1214 // function uses CR 2, 3, or 4. 1215 if (!isPPC64 && !isDarwinABI && 1216 (MRI.isPhysRegUsed(PPC::CR2) || 1217 MRI.isPhysRegUsed(PPC::CR3) || 1218 MRI.isPhysRegUsed(PPC::CR4))) { 1219 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true); 1220 FI->setCRSpillFrameIndex(FrameIdx); 1221 } 1222 } 1223 1224 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, 1225 RegScavenger *RS) const { 1226 // Early exit if not using the SVR4 ABI. 1227 if (!Subtarget.isSVR4ABI()) { 1228 addScavengingSpillSlot(MF, RS); 1229 return; 1230 } 1231 1232 // Get callee saved register information. 1233 MachineFrameInfo *FFI = MF.getFrameInfo(); 1234 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 1235 1236 // Early exit if no callee saved registers are modified! 1237 if (CSI.empty() && !needsFP(MF)) { 1238 addScavengingSpillSlot(MF, RS); 1239 return; 1240 } 1241 1242 unsigned MinGPR = PPC::R31; 1243 unsigned MinG8R = PPC::X31; 1244 unsigned MinFPR = PPC::F31; 1245 unsigned MinVR = PPC::V31; 1246 1247 bool HasGPSaveArea = false; 1248 bool HasG8SaveArea = false; 1249 bool HasFPSaveArea = false; 1250 bool HasVRSAVESaveArea = false; 1251 bool HasVRSaveArea = false; 1252 1253 SmallVector<CalleeSavedInfo, 18> GPRegs; 1254 SmallVector<CalleeSavedInfo, 18> G8Regs; 1255 SmallVector<CalleeSavedInfo, 18> FPRegs; 1256 SmallVector<CalleeSavedInfo, 18> VRegs; 1257 1258 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1259 unsigned Reg = CSI[i].getReg(); 1260 if (PPC::GPRCRegClass.contains(Reg)) { 1261 HasGPSaveArea = true; 1262 1263 GPRegs.push_back(CSI[i]); 1264 1265 if (Reg < MinGPR) { 1266 MinGPR = Reg; 1267 } 1268 } else if (PPC::G8RCRegClass.contains(Reg)) { 1269 HasG8SaveArea = true; 1270 1271 G8Regs.push_back(CSI[i]); 1272 1273 if (Reg < MinG8R) { 1274 MinG8R = Reg; 1275 } 1276 } else if (PPC::F8RCRegClass.contains(Reg)) { 1277 HasFPSaveArea = true; 1278 1279 FPRegs.push_back(CSI[i]); 1280 1281 if (Reg < MinFPR) { 1282 MinFPR = Reg; 1283 } 1284 } else if (PPC::CRBITRCRegClass.contains(Reg) || 1285 PPC::CRRCRegClass.contains(Reg)) { 1286 ; // do nothing, as we already know whether CRs are spilled 1287 } else if (PPC::VRSAVERCRegClass.contains(Reg)) { 1288 HasVRSAVESaveArea = true; 1289 } else if (PPC::VRRCRegClass.contains(Reg)) { 1290 HasVRSaveArea = true; 1291 1292 VRegs.push_back(CSI[i]); 1293 1294 if (Reg < MinVR) { 1295 MinVR = Reg; 1296 } 1297 } else { 1298 llvm_unreachable("Unknown RegisterClass!"); 1299 } 1300 } 1301 1302 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 1303 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 1304 1305 int64_t LowerBound = 0; 1306 1307 // Take into account stack space reserved for tail calls. 1308 int TCSPDelta = 0; 1309 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1310 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 1311 LowerBound = TCSPDelta; 1312 } 1313 1314 // The Floating-point register save area is right below the back chain word 1315 // of the previous stack frame. 1316 if (HasFPSaveArea) { 1317 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 1318 int FI = FPRegs[i].getFrameIdx(); 1319 1320 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1321 } 1322 1323 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8; 1324 } 1325 1326 // Check whether the frame pointer register is allocated. If so, make sure it 1327 // is spilled to the correct offset. 1328 if (needsFP(MF)) { 1329 HasGPSaveArea = true; 1330 1331 int FI = PFI->getFramePointerSaveIndex(); 1332 assert(FI && "No Frame Pointer Save Slot!"); 1333 1334 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1335 } 1336 1337 if (PFI->usesPICBase()) { 1338 HasGPSaveArea = true; 1339 1340 int FI = PFI->getPICBasePointerSaveIndex(); 1341 assert(FI && "No PIC Base Pointer Save Slot!"); 1342 1343 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1344 } 1345 1346 const PPCRegisterInfo *RegInfo = 1347 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 1348 if (RegInfo->hasBasePointer(MF)) { 1349 HasGPSaveArea = true; 1350 1351 int FI = PFI->getBasePointerSaveIndex(); 1352 assert(FI && "No Base Pointer Save Slot!"); 1353 1354 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1355 } 1356 1357 // General register save area starts right below the Floating-point 1358 // register save area. 1359 if (HasGPSaveArea || HasG8SaveArea) { 1360 // Move general register save area spill slots down, taking into account 1361 // the size of the Floating-point register save area. 1362 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 1363 int FI = GPRegs[i].getFrameIdx(); 1364 1365 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1366 } 1367 1368 // Move general register save area spill slots down, taking into account 1369 // the size of the Floating-point register save area. 1370 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 1371 int FI = G8Regs[i].getFrameIdx(); 1372 1373 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1374 } 1375 1376 unsigned MinReg = 1377 std::min<unsigned>(TRI->getEncodingValue(MinGPR), 1378 TRI->getEncodingValue(MinG8R)); 1379 1380 if (Subtarget.isPPC64()) { 1381 LowerBound -= (31 - MinReg + 1) * 8; 1382 } else { 1383 LowerBound -= (31 - MinReg + 1) * 4; 1384 } 1385 } 1386 1387 // For 32-bit only, the CR save area is below the general register 1388 // save area. For 64-bit SVR4, the CR save area is addressed relative 1389 // to the stack pointer and hence does not need an adjustment here. 1390 // Only CR2 (the first nonvolatile spilled) has an associated frame 1391 // index so that we have a single uniform save area. 1392 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) { 1393 // Adjust the frame index of the CR spill slot. 1394 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1395 unsigned Reg = CSI[i].getReg(); 1396 1397 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2) 1398 // Leave Darwin logic as-is. 1399 || (!Subtarget.isSVR4ABI() && 1400 (PPC::CRBITRCRegClass.contains(Reg) || 1401 PPC::CRRCRegClass.contains(Reg)))) { 1402 int FI = CSI[i].getFrameIdx(); 1403 1404 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1405 } 1406 } 1407 1408 LowerBound -= 4; // The CR save area is always 4 bytes long. 1409 } 1410 1411 if (HasVRSAVESaveArea) { 1412 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1413 // which have the VRSAVE register class? 1414 // Adjust the frame index of the VRSAVE spill slot. 1415 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1416 unsigned Reg = CSI[i].getReg(); 1417 1418 if (PPC::VRSAVERCRegClass.contains(Reg)) { 1419 int FI = CSI[i].getFrameIdx(); 1420 1421 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1422 } 1423 } 1424 1425 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 1426 } 1427 1428 if (HasVRSaveArea) { 1429 // Insert alignment padding, we need 16-byte alignment. 1430 LowerBound = (LowerBound - 15) & ~(15); 1431 1432 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 1433 int FI = VRegs[i].getFrameIdx(); 1434 1435 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1436 } 1437 } 1438 1439 addScavengingSpillSlot(MF, RS); 1440 } 1441 1442 void 1443 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF, 1444 RegScavenger *RS) const { 1445 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 1446 // a large stack, which will require scavenging a register to materialize a 1447 // large offset. 1448 1449 // We need to have a scavenger spill slot for spills if the frame size is 1450 // large. In case there is no free register for large-offset addressing, 1451 // this slot is used for the necessary emergency spill. Also, we need the 1452 // slot for dynamic stack allocations. 1453 1454 // The scavenger might be invoked if the frame offset does not fit into 1455 // the 16-bit immediate. We don't know the complete frame size here 1456 // because we've not yet computed callee-saved register spills or the 1457 // needed alignment padding. 1458 unsigned StackSize = determineFrameLayout(MF, false, true); 1459 MachineFrameInfo *MFI = MF.getFrameInfo(); 1460 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) || 1461 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) { 1462 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 1463 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 1464 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 1465 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1466 RC->getAlignment(), 1467 false)); 1468 1469 // Might we have over-aligned allocas? 1470 bool HasAlVars = MFI->hasVarSizedObjects() && 1471 MFI->getMaxAlignment() > getStackAlignment(); 1472 1473 // These kinds of spills might need two registers. 1474 if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars) 1475 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1476 RC->getAlignment(), 1477 false)); 1478 1479 } 1480 } 1481 1482 bool 1483 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1484 MachineBasicBlock::iterator MI, 1485 const std::vector<CalleeSavedInfo> &CSI, 1486 const TargetRegisterInfo *TRI) const { 1487 1488 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1489 // Return false otherwise to maintain pre-existing behavior. 1490 if (!Subtarget.isSVR4ABI()) 1491 return false; 1492 1493 MachineFunction *MF = MBB.getParent(); 1494 const PPCInstrInfo &TII = 1495 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 1496 DebugLoc DL; 1497 bool CRSpilled = false; 1498 MachineInstrBuilder CRMIB; 1499 1500 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1501 unsigned Reg = CSI[i].getReg(); 1502 // Only Darwin actually uses the VRSAVE register, but it can still appear 1503 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on 1504 // Darwin, ignore it. 1505 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI()) 1506 continue; 1507 1508 // CR2 through CR4 are the nonvolatile CR fields. 1509 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; 1510 1511 // Add the callee-saved register as live-in; it's killed at the spill. 1512 MBB.addLiveIn(Reg); 1513 1514 if (CRSpilled && IsCRField) { 1515 CRMIB.addReg(Reg, RegState::ImplicitKill); 1516 continue; 1517 } 1518 1519 // Insert the spill to the stack frame. 1520 if (IsCRField) { 1521 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>(); 1522 if (Subtarget.isPPC64()) { 1523 // The actual spill will happen at the start of the prologue. 1524 FuncInfo->addMustSaveCR(Reg); 1525 } else { 1526 CRSpilled = true; 1527 FuncInfo->setSpillsCR(); 1528 1529 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have 1530 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot. 1531 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12) 1532 .addReg(Reg, RegState::ImplicitKill); 1533 1534 MBB.insert(MI, CRMIB); 1535 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW)) 1536 .addReg(PPC::R12, 1537 getKillRegState(true)), 1538 CSI[i].getFrameIdx())); 1539 } 1540 } else { 1541 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1542 TII.storeRegToStackSlot(MBB, MI, Reg, true, 1543 CSI[i].getFrameIdx(), RC, TRI); 1544 } 1545 } 1546 return true; 1547 } 1548 1549 static void 1550 restoreCRs(bool isPPC64, bool is31, 1551 bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, 1552 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 1553 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) { 1554 1555 MachineFunction *MF = MBB.getParent(); 1556 const PPCInstrInfo &TII = *MF->getSubtarget<PPCSubtarget>().getInstrInfo(); 1557 DebugLoc DL; 1558 unsigned RestoreOp, MoveReg; 1559 1560 if (isPPC64) 1561 // This is handled during epilogue generation. 1562 return; 1563 else { 1564 // 32-bit: FP-relative 1565 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), 1566 PPC::R12), 1567 CSI[CSIIndex].getFrameIdx())); 1568 RestoreOp = PPC::MTOCRF; 1569 MoveReg = PPC::R12; 1570 } 1571 1572 if (CR2Spilled) 1573 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2) 1574 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled))); 1575 1576 if (CR3Spilled) 1577 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3) 1578 .addReg(MoveReg, getKillRegState(!CR4Spilled))); 1579 1580 if (CR4Spilled) 1581 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4) 1582 .addReg(MoveReg, getKillRegState(true))); 1583 } 1584 1585 void PPCFrameLowering:: 1586 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1587 MachineBasicBlock::iterator I) const { 1588 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1589 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1590 I->getOpcode() == PPC::ADJCALLSTACKUP) { 1591 // Add (actually subtract) back the amount the callee popped on return. 1592 if (int CalleeAmt = I->getOperand(1).getImm()) { 1593 bool is64Bit = Subtarget.isPPC64(); 1594 CalleeAmt *= -1; 1595 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 1596 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 1597 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 1598 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 1599 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 1600 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 1601 MachineInstr *MI = I; 1602 DebugLoc dl = MI->getDebugLoc(); 1603 1604 if (isInt<16>(CalleeAmt)) { 1605 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg) 1606 .addReg(StackReg, RegState::Kill) 1607 .addImm(CalleeAmt); 1608 } else { 1609 MachineBasicBlock::iterator MBBI = I; 1610 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 1611 .addImm(CalleeAmt >> 16); 1612 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 1613 .addReg(TmpReg, RegState::Kill) 1614 .addImm(CalleeAmt & 0xFFFF); 1615 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg) 1616 .addReg(StackReg, RegState::Kill) 1617 .addReg(TmpReg); 1618 } 1619 } 1620 } 1621 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 1622 MBB.erase(I); 1623 } 1624 1625 bool 1626 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1627 MachineBasicBlock::iterator MI, 1628 const std::vector<CalleeSavedInfo> &CSI, 1629 const TargetRegisterInfo *TRI) const { 1630 1631 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1632 // Return false otherwise to maintain pre-existing behavior. 1633 if (!Subtarget.isSVR4ABI()) 1634 return false; 1635 1636 MachineFunction *MF = MBB.getParent(); 1637 const PPCInstrInfo &TII = 1638 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 1639 bool CR2Spilled = false; 1640 bool CR3Spilled = false; 1641 bool CR4Spilled = false; 1642 unsigned CSIIndex = 0; 1643 1644 // Initialize insertion-point logic; we will be restoring in reverse 1645 // order of spill. 1646 MachineBasicBlock::iterator I = MI, BeforeI = I; 1647 bool AtStart = I == MBB.begin(); 1648 1649 if (!AtStart) 1650 --BeforeI; 1651 1652 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1653 unsigned Reg = CSI[i].getReg(); 1654 1655 // Only Darwin actually uses the VRSAVE register, but it can still appear 1656 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on 1657 // Darwin, ignore it. 1658 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI()) 1659 continue; 1660 1661 if (Reg == PPC::CR2) { 1662 CR2Spilled = true; 1663 // The spill slot is associated only with CR2, which is the 1664 // first nonvolatile spilled. Save it here. 1665 CSIIndex = i; 1666 continue; 1667 } else if (Reg == PPC::CR3) { 1668 CR3Spilled = true; 1669 continue; 1670 } else if (Reg == PPC::CR4) { 1671 CR4Spilled = true; 1672 continue; 1673 } else { 1674 // When we first encounter a non-CR register after seeing at 1675 // least one CR register, restore all spilled CRs together. 1676 if ((CR2Spilled || CR3Spilled || CR4Spilled) 1677 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 1678 bool is31 = needsFP(*MF); 1679 restoreCRs(Subtarget.isPPC64(), is31, 1680 CR2Spilled, CR3Spilled, CR4Spilled, 1681 MBB, I, CSI, CSIIndex); 1682 CR2Spilled = CR3Spilled = CR4Spilled = false; 1683 } 1684 1685 // Default behavior for non-CR saves. 1686 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1687 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(), 1688 RC, TRI); 1689 assert(I != MBB.begin() && 1690 "loadRegFromStackSlot didn't insert any code!"); 1691 } 1692 1693 // Insert in reverse order. 1694 if (AtStart) 1695 I = MBB.begin(); 1696 else { 1697 I = BeforeI; 1698 ++I; 1699 } 1700 } 1701 1702 // If we haven't yet spilled the CRs, do so now. 1703 if (CR2Spilled || CR3Spilled || CR4Spilled) { 1704 bool is31 = needsFP(*MF); 1705 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled, 1706 MBB, I, CSI, CSIIndex); 1707 } 1708 1709 return true; 1710 } 1711