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      1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 //
     11 //===----------------------------------------------------------------------===//
     12 
     13 #include "AArch64.h"
     14 #include "AArch64TargetMachine.h"
     15 #include "AArch64TargetObjectFile.h"
     16 #include "AArch64TargetTransformInfo.h"
     17 #include "llvm/CodeGen/Passes.h"
     18 #include "llvm/CodeGen/RegAllocRegistry.h"
     19 #include "llvm/IR/Function.h"
     20 #include "llvm/IR/LegacyPassManager.h"
     21 #include "llvm/Support/CommandLine.h"
     22 #include "llvm/Support/TargetRegistry.h"
     23 #include "llvm/Target/TargetOptions.h"
     24 #include "llvm/Transforms/Scalar.h"
     25 using namespace llvm;
     26 
     27 static cl::opt<bool>
     28 EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
     29            cl::init(true), cl::Hidden);
     30 
     31 static cl::opt<bool> EnableMCR("aarch64-mcr",
     32                                cl::desc("Enable the machine combiner pass"),
     33                                cl::init(true), cl::Hidden);
     34 
     35 static cl::opt<bool>
     36 EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
     37                      cl::init(true), cl::Hidden);
     38 
     39 static cl::opt<bool>
     40 EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
     41                     " integer instructions"), cl::init(false), cl::Hidden);
     42 
     43 static cl::opt<bool>
     44 EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
     45                       "constant pass"), cl::init(true), cl::Hidden);
     46 
     47 static cl::opt<bool>
     48 EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
     49                  " linker optimization hints (LOH)"), cl::init(true),
     50                  cl::Hidden);
     51 
     52 static cl::opt<bool>
     53 EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
     54                               cl::desc("Enable the pass that removes dead"
     55                                        " definitons and replaces stores to"
     56                                        " them with stores to the zero"
     57                                        " register"),
     58                               cl::init(true));
     59 
     60 static cl::opt<bool>
     61 EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
     62                    " optimization pass"), cl::init(true), cl::Hidden);
     63 
     64 static cl::opt<bool>
     65 EnableAtomicTidy("aarch64-atomic-cfg-tidy", cl::Hidden,
     66                  cl::desc("Run SimplifyCFG after expanding atomic operations"
     67                           " to make use of cmpxchg flow-based information"),
     68                  cl::init(true));
     69 
     70 static cl::opt<bool>
     71 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
     72                         cl::desc("Run early if-conversion"),
     73                         cl::init(true));
     74 
     75 static cl::opt<bool>
     76 EnableCondOpt("aarch64-condopt",
     77               cl::desc("Enable the condition optimizer pass"),
     78               cl::init(true), cl::Hidden);
     79 
     80 static cl::opt<bool>
     81 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
     82                 cl::desc("Work around Cortex-A53 erratum 835769"),
     83                 cl::init(false));
     84 
     85 static cl::opt<bool>
     86 EnableGEPOpt("aarch64-gep-opt", cl::Hidden,
     87              cl::desc("Enable optimizations on complex GEPs"),
     88              cl::init(true));
     89 
     90 // FIXME: Unify control over GlobalMerge.
     91 static cl::opt<cl::boolOrDefault>
     92 EnableGlobalMerge("aarch64-global-merge", cl::Hidden,
     93                   cl::desc("Enable the global merge pass"));
     94 
     95 extern "C" void LLVMInitializeAArch64Target() {
     96   // Register the target.
     97   RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
     98   RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
     99   RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64Target);
    100 }
    101 
    102 //===----------------------------------------------------------------------===//
    103 // AArch64 Lowering public interface.
    104 //===----------------------------------------------------------------------===//
    105 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
    106   if (TT.isOSBinFormatMachO())
    107     return make_unique<AArch64_MachoTargetObjectFile>();
    108 
    109   return make_unique<AArch64_ELFTargetObjectFile>();
    110 }
    111 
    112 // Helper function to build a DataLayout string
    113 static std::string computeDataLayout(StringRef TT, bool LittleEndian) {
    114   Triple Triple(TT);
    115   if (Triple.isOSBinFormatMachO())
    116     return "e-m:o-i64:64-i128:128-n32:64-S128";
    117   if (LittleEndian)
    118     return "e-m:e-i64:64-i128:128-n32:64-S128";
    119   return "E-m:e-i64:64-i128:128-n32:64-S128";
    120 }
    121 
    122 /// TargetMachine ctor - Create an AArch64 architecture model.
    123 ///
    124 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
    125                                            StringRef CPU, StringRef FS,
    126                                            const TargetOptions &Options,
    127                                            Reloc::Model RM, CodeModel::Model CM,
    128                                            CodeGenOpt::Level OL,
    129                                            bool LittleEndian)
    130     // This nested ternary is horrible, but DL needs to be properly
    131     // initialized before TLInfo is constructed.
    132     : LLVMTargetMachine(T, computeDataLayout(TT, LittleEndian), TT, CPU, FS,
    133                         Options, RM, CM, OL),
    134       TLOF(createTLOF(Triple(getTargetTriple()))),
    135       isLittle(LittleEndian) {
    136   initAsmInfo();
    137 }
    138 
    139 AArch64TargetMachine::~AArch64TargetMachine() {}
    140 
    141 const AArch64Subtarget *
    142 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
    143   Attribute CPUAttr = F.getFnAttribute("target-cpu");
    144   Attribute FSAttr = F.getFnAttribute("target-features");
    145 
    146   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
    147                         ? CPUAttr.getValueAsString().str()
    148                         : TargetCPU;
    149   std::string FS = !FSAttr.hasAttribute(Attribute::None)
    150                        ? FSAttr.getValueAsString().str()
    151                        : TargetFS;
    152 
    153   auto &I = SubtargetMap[CPU + FS];
    154   if (!I) {
    155     // This needs to be done before we create a new subtarget since any
    156     // creation will depend on the TM and the code generation flags on the
    157     // function that reside in TargetOptions.
    158     resetTargetOptions(F);
    159     I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this, isLittle);
    160   }
    161   return I.get();
    162 }
    163 
    164 void AArch64leTargetMachine::anchor() { }
    165 
    166 AArch64leTargetMachine::
    167 AArch64leTargetMachine(const Target &T, StringRef TT,
    168                        StringRef CPU, StringRef FS, const TargetOptions &Options,
    169                        Reloc::Model RM, CodeModel::Model CM,
    170                        CodeGenOpt::Level OL)
    171   : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
    172 
    173 void AArch64beTargetMachine::anchor() { }
    174 
    175 AArch64beTargetMachine::
    176 AArch64beTargetMachine(const Target &T, StringRef TT,
    177                        StringRef CPU, StringRef FS, const TargetOptions &Options,
    178                        Reloc::Model RM, CodeModel::Model CM,
    179                        CodeGenOpt::Level OL)
    180   : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
    181 
    182 namespace {
    183 /// AArch64 Code Generator Pass Configuration Options.
    184 class AArch64PassConfig : public TargetPassConfig {
    185 public:
    186   AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
    187       : TargetPassConfig(TM, PM) {
    188     if (TM->getOptLevel() != CodeGenOpt::None)
    189       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
    190   }
    191 
    192   AArch64TargetMachine &getAArch64TargetMachine() const {
    193     return getTM<AArch64TargetMachine>();
    194   }
    195 
    196   void addIRPasses()  override;
    197   bool addPreISel() override;
    198   bool addInstSelector() override;
    199   bool addILPOpts() override;
    200   void addPreRegAlloc() override;
    201   void addPostRegAlloc() override;
    202   void addPreSched2() override;
    203   void addPreEmitPass() override;
    204 };
    205 } // namespace
    206 
    207 TargetIRAnalysis AArch64TargetMachine::getTargetIRAnalysis() {
    208   return TargetIRAnalysis([this](Function &F) {
    209     return TargetTransformInfo(AArch64TTIImpl(this, F));
    210   });
    211 }
    212 
    213 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
    214   return new AArch64PassConfig(this, PM);
    215 }
    216 
    217 void AArch64PassConfig::addIRPasses() {
    218   // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
    219   // ourselves.
    220   addPass(createAtomicExpandPass(TM));
    221 
    222   // Cmpxchg instructions are often used with a subsequent comparison to
    223   // determine whether it succeeded. We can exploit existing control-flow in
    224   // ldrex/strex loops to simplify this, but it needs tidying up.
    225   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
    226     addPass(createCFGSimplificationPass());
    227 
    228   TargetPassConfig::addIRPasses();
    229 
    230   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
    231     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
    232     // and lower a GEP with multiple indices to either arithmetic operations or
    233     // multiple GEPs with single index.
    234     addPass(createSeparateConstOffsetFromGEPPass(TM, true));
    235     // Call EarlyCSE pass to find and remove subexpressions in the lowered
    236     // result.
    237     addPass(createEarlyCSEPass());
    238     // Do loop invariant code motion in case part of the lowered result is
    239     // invariant.
    240     addPass(createLICMPass());
    241   }
    242 }
    243 
    244 // Pass Pipeline Configuration
    245 bool AArch64PassConfig::addPreISel() {
    246   // Run promote constant before global merge, so that the promoted constants
    247   // get a chance to be merged
    248   if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
    249     addPass(createAArch64PromoteConstantPass());
    250   // FIXME: On AArch64, this depends on the type.
    251   // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
    252   // and the offset has to be a multiple of the related size in bytes.
    253   if ((TM->getOptLevel() == CodeGenOpt::Aggressive &&
    254        EnableGlobalMerge == cl::BOU_UNSET) ||
    255       EnableGlobalMerge == cl::BOU_TRUE)
    256     addPass(createGlobalMergePass(TM, 4095));
    257   if (TM->getOptLevel() != CodeGenOpt::None)
    258     addPass(createAArch64AddressTypePromotionPass());
    259 
    260   return false;
    261 }
    262 
    263 bool AArch64PassConfig::addInstSelector() {
    264   addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
    265 
    266   // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
    267   // references to _TLS_MODULE_BASE_ as possible.
    268   if (Triple(TM->getTargetTriple()).isOSBinFormatELF() &&
    269       getOptLevel() != CodeGenOpt::None)
    270     addPass(createAArch64CleanupLocalDynamicTLSPass());
    271 
    272   return false;
    273 }
    274 
    275 bool AArch64PassConfig::addILPOpts() {
    276   if (EnableCondOpt)
    277     addPass(createAArch64ConditionOptimizerPass());
    278   if (EnableCCMP)
    279     addPass(createAArch64ConditionalCompares());
    280   if (EnableMCR)
    281     addPass(&MachineCombinerID);
    282   if (EnableEarlyIfConversion)
    283     addPass(&EarlyIfConverterID);
    284   if (EnableStPairSuppress)
    285     addPass(createAArch64StorePairSuppressPass());
    286   return true;
    287 }
    288 
    289 void AArch64PassConfig::addPreRegAlloc() {
    290   // Use AdvSIMD scalar instructions whenever profitable.
    291   if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
    292     addPass(createAArch64AdvSIMDScalar());
    293     // The AdvSIMD pass may produce copies that can be rewritten to
    294     // be register coaleascer friendly.
    295     addPass(&PeepholeOptimizerID);
    296   }
    297 }
    298 
    299 void AArch64PassConfig::addPostRegAlloc() {
    300   // Change dead register definitions to refer to the zero register.
    301   if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
    302     addPass(createAArch64DeadRegisterDefinitions());
    303   if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
    304     // Improve performance for some FP/SIMD code for A57.
    305     addPass(createAArch64A57FPLoadBalancing());
    306 }
    307 
    308 void AArch64PassConfig::addPreSched2() {
    309   // Expand some pseudo instructions to allow proper scheduling.
    310   addPass(createAArch64ExpandPseudoPass());
    311   // Use load/store pair instructions when possible.
    312   if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
    313     addPass(createAArch64LoadStoreOptimizationPass());
    314 }
    315 
    316 void AArch64PassConfig::addPreEmitPass() {
    317   if (EnableA53Fix835769)
    318     addPass(createAArch64A53Fix835769());
    319   // Relax conditional branch instructions if they're otherwise out of
    320   // range of their destination.
    321   addPass(createAArch64BranchRelaxation());
    322   if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
    323       Triple(TM->getTargetTriple()).isOSBinFormatMachO())
    324     addPass(createAArch64CollectLOHPass());
    325 }
    326