| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 512 unsigned Opcode = Instruction::UserOp1;
518 Opcode = I->getOpcode();
522 Opcode = C->getOpcode();
532 switch (Opcode) {
861 unsigned Opcode = Instruction::UserOp1;
865 Opcode = I->getOpcode();
869 Opcode = C->getOpcode();
873 switch (Opcode) {
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 65 uint16_t MLxOpc; // MLA / MLS opcode
66 uint16_t MulOpc; // Expanded multiplication opcode
67 uint16_t AddSubOpc; // Expanded add / sub opcode
[all...] |
| ARMFastISel.cpp | 759 unsigned Opcode = Instruction::UserOp1;
765 Opcode = I->getOpcode();
769 Opcode = C->getOpcode();
779 switch (Opcode) {
[all...] |
| ARMISelDAGToDAG.cpp | 209 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
217 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
225 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
232 /// should be 2, 3 or 4. The opcode array specifies the instructions used
310 // opcode and that it has a immediate integer right operand.
449 unsigned Opcode = MCID.getOpcode();
450 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
465 return TII->isFpMLxInstruction(Opcode);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 279 /// First entry is always the opcode of the branching instruction, except when
281 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
289 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
1012 unsigned opcode = Cond[0].getImm(); local
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 117 /// rotate and mask opcode and mask operation.
188 /// Reg in an asm, because the load or store opcode would have to change.
456 // opcode and that it has a immediate integer right operand.
485 unsigned Opcode = N->getOpcode();
490 if (Opcode == ISD::SHL) {
495 } else if (Opcode == ISD::SRL) {
502 } else if (Opcode == ISD::ROTL) {
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 350 // Get opcode and regclass of the output for the given load instruction.
441 // Get opcode and regclass of the output for the given store instruction.
567 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
693 unsigned Opcode = Instruction::UserOp1;
700 Opcode = I->getOpcode();
704 Opcode = C->getOpcode();
714 switch (Opcode) {
853 unsigned Opcode = Instruction::UserOp1;
880 Opcode = I->getOpcode();
884 Opcode = C->getOpcode()
[all...] |
| X86ISelLowering.cpp | 2314 X86ISD::NodeType opcode = X86ISD::RET_FLAG; local
[all...] |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstructionCombining.cpp | 128 Instruction::BinaryOps Opcode = I.getOpcode();
129 if (Opcode != Instruction::Add &&
130 Opcode != Instruction::Sub) {
145 if (Opcode == Instruction::Add) {
190 Instruction::BinaryOps Opcode = I.getOpcode();
206 if (Op0 && Op0->getOpcode() == Opcode) {
212 if (Value *V = SimplifyBinOp(Opcode, B, C, DL)) {
235 if (Op1 && Op1->getOpcode() == Opcode) {
241 if (Value *V = SimplifyBinOp(Opcode, A, B, DL)) {
257 if (Op0 && Op0->getOpcode() == Opcode) {
[all...] |
| /external/v8/src/arm/ |
| constants-arm.h | 140 enum Opcode {
561 return static_cast<Opcode>(Bits(24, 21));
563 inline Opcode OpcodeField() const {
564 return static_cast<Opcode>(BitField(24, 21));
|
| /external/v8/src/crankshaft/arm/ |
| lithium-arm.h | 164 Opcode opcode() const final { return LInstruction::k##type; } \
195 enum Opcode {
203 virtual Opcode opcode() const = 0;
207 bool Is##type() const { return opcode() == k##type; }
212 // an opcode.
[all...] |
| /external/v8/src/crankshaft/arm64/ |
| lithium-arm64.h | 176 Opcode opcode() const final { return LInstruction::k##type; } \
206 enum Opcode {
214 virtual Opcode opcode() const = 0;
218 bool Is##type() const { return opcode() == k##type; }
223 // an opcode.
689 Opcode opcode() const override { return LInstruction::kArithmeticD; }
715 Opcode opcode() const override { return LInstruction::kArithmeticT;
[all...] |
| /external/v8/src/crankshaft/ia32/ |
| lithium-ia32.h | 165 Opcode opcode() const final { return LInstruction::k##type; } \
196 enum Opcode {
204 virtual Opcode opcode() const = 0;
208 bool Is##type() const { return opcode() == k##type; }
213 // an opcode.
[all...] |
| /external/v8/src/crankshaft/mips/ |
| lithium-mips.h | 161 Opcode opcode() const final { return LInstruction::k##type; } \
192 enum Opcode {
200 virtual Opcode opcode() const = 0;
204 bool Is##type() const { return opcode() == k##type; }
209 // an opcode.
[all...] |
| /external/v8/src/crankshaft/mips64/ |
| lithium-mips64.h | 164 Opcode opcode() const final { return LInstruction::k##type; } \
195 enum Opcode {
203 virtual Opcode opcode() const = 0;
207 bool Is##type() const { return opcode() == k##type; }
212 // an opcode.
[all...] |
| /external/v8/src/crankshaft/ppc/ |
| lithium-ppc.h | 164 Opcode opcode() const final { return LInstruction::k##type; } \
192 enum Opcode {
199 virtual Opcode opcode() const = 0;
203 bool Is##type() const { return opcode() == k##type; }
208 // an opcode.
[all...] |
| /external/v8/src/crankshaft/x64/ |
| lithium-x64.h | 161 Opcode opcode() const final { return LInstruction::k##type; } \
192 enum Opcode {
200 virtual Opcode opcode() const = 0;
204 bool Is##type() const { return opcode() == k##type; }
209 // an opcode.
[all...] |
| /external/v8/src/crankshaft/x87/ |
| lithium-x87.h | 166 Opcode opcode() const final { return LInstruction::k##type; } \
197 enum Opcode {
205 virtual Opcode opcode() const = 0;
209 bool Is##type() const { return opcode() == k##type; }
214 // an opcode.
[all...] |
| /external/v8/src/ppc/ |
| constants-ppc.h | 97 enum Opcode {
265 // Some use Bits 10-1 and other only 5-1 for the opcode
552 inline int OpcodeValue() const { return static_cast<Opcode>(Bits(31, 26)); }
553 inline Opcode OpcodeField() const {
554 return static_cast<Opcode>(BitField(24, 21));
|
| /external/clang/lib/CodeGen/ |
| CGExprScalar.cpp | 48 BinaryOperator::Opcode Opcode; // Opcode of BinOp to perform
[all...] |
| /external/llvm/bindings/ocaml/llvm/ |
| llvm.mli | 206 module Opcode : sig
310 (** The opcode of an [atomicrmw] instruction.
352 | Instruction of Opcode.t
785 (** [constexpr_opcode v] returns an [Opcode.t] corresponding to constexpr
786 value [v], or [Opcode.Invalid] if [v] is not a constexpr. *)
787 val constexpr_opcode : llvalue -> Opcode.t
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 546 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
547 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
739 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
740 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
[all...] |
| LegalizeVectorTypes.cpp | 712 unsigned Opcode = N->getOpcode();
713 Lo = DAG.getNode(Opcode, dl, LHSLo.getValueType(), LHSLo, RHSLo, Flags);
714 Hi = DAG.getNode(Opcode, dl, LHSHi.getValueType(), LHSHi, RHSHi, Flags);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 110 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
111 switch ((MipsISD::NodeType)Opcode) {
[all...] |
