| /external/v8/src/regexp/ |
| regexp-macro-assembler-irregexp.cc | 73 Emit(BC_POP_REGISTER, register_index);
82 Emit(BC_PUSH_REGISTER, register_index);
90 Emit(BC_SET_REGISTER_TO_CP, register_index);
107 Emit(BC_SET_CP_TO_REGISTER, register_index);
115 Emit(BC_SET_REGISTER_TO_SP, register_index);
123 Emit(BC_SET_SP_TO_REGISTER, register_index);
129 Emit(BC_SET_CURRENT_POSITION_FROM_END, by);
136 Emit(BC_SET_REGISTER, register_index);
144 Emit(BC_ADVANCE_REGISTER, register_index);
150 Emit(BC_POP_CP, 0)
[all...] |
| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 56 void Emit(uint32_t value, raw_ostream &OS) const;
57 void Emit(uint64_t value, raw_ostream &OS) const;
105 Emit(InstWord01, OS);
106 Emit(InstWord2, OS);
107 Emit((uint32_t) 0, OS);
129 Emit(Word01, OS);
130 Emit(Word2, OS);
131 Emit((uint32_t) 0, OS);
141 Emit(Inst, OS);
149 void R600MCCodeEmitter::Emit(uint32_t Value, raw_ostream &OS) const
[all...] |
| /external/v8/src/compiler/x87/ |
| instruction-selector-x87.cc | 204 Emit(code, 1, outputs, input_count, inputs);
252 Emit(code, 0, nullptr, input_count, inputs, temp_count, temps);
297 Emit(code, 0, static_cast<InstructionOperand*>(nullptr), input_count,
338 Emit(opcode | AddressingModeField::encode(kMode_MRI),
342 Emit(opcode | AddressingModeField::encode(kMode_MR1),
391 Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(),
395 Emit(opcode | AddressingModeField::encode(kMode_MR1), g.NoOutput(),
459 selector->Emit(opcode, output_count, outputs, input_count, inputs);
487 Emit(kX87Not, g.DefineSameAsFirst(node), g.UseRegister(m.left().node()));
502 selector->Emit(opcode, g.DefineSameAsFirst(node), g.UseRegister(left)
[all...] |
| /external/clang/utils/TableGen/ |
| ClangCommentHTMLTagsEmitter.cpp | 33 StringMatcher("Name", Matches, OS).Emit();
55 StringMatcher("Name", MatchesEndTagOptional, OS).Emit();
60 StringMatcher("Name", MatchesEndTagForbidden, OS).Emit();
|
| /external/vixl/src/vixl/ |
| code-buffer.h | 64 // A code buffer can emit:
68 void Emit32(uint32_t data) { Emit(data); }
70 void Emit64(uint64_t data) { Emit(data); }
89 void Emit(T value) {
|
| /external/v8/src/compiler/mips/ |
| instruction-selector-mips.cc | 67 selector->Emit(opcode, g.DefineAsRegister(node),
76 selector->Emit(opcode, g.DefineAsRegister(node),
84 selector->Emit(opcode, g.DefineAsRegister(node),
122 selector->Emit(opcode, output_count, outputs, input_count, inputs);
167 Emit(opcode | AddressingModeField::encode(kMode_MRI),
171 Emit(kMipsAdd | AddressingModeField::encode(kMode_None), addr_reg,
173 // Emit desired load opcode, using temp addr_reg.
174 Emit(opcode | AddressingModeField::encode(kMode_MRI),
217 Emit(code, 0, nullptr, input_count, inputs, temp_count, temps);
246 Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput()
[all...] |
| /external/v8/src/compiler/mips64/ |
| instruction-selector-mips64.cc | 72 selector->Emit(opcode, g.DefineAsRegister(node),
80 selector->Emit(opcode, g.DefineAsRegister(node),
89 selector->Emit(opcode, g.DefineAsRegister(node),
127 selector->Emit(opcode, output_count, outputs, input_count, inputs);
174 Emit(opcode | AddressingModeField::encode(kMode_MRI),
178 Emit(kMips64Dadd | AddressingModeField::encode(kMode_None), addr_reg,
180 // Emit desired load opcode, using temp addr_reg.
181 Emit(opcode | AddressingModeField::encode(kMode_MRI),
224 Emit(code, 0, nullptr, input_count, inputs, temp_count, temps);
255 Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput()
[all...] |
| /external/llvm/include/llvm/TableGen/ |
| StringMatcher.h | 45 void Emit(unsigned Indent = 0) const;
|
| /external/v8/src/compiler/x64/ |
| instruction-selector-x64.cc | 181 Emit(code, 1, outputs, input_count, inputs);
229 Emit(code, 0, nullptr, input_count, inputs, temp_count, temps);
267 Emit(code, 0, static_cast<InstructionOperand*>(nullptr), input_count,
312 Emit(opcode, g.DefineAsRegister(node), g.UseRegister(buffer),
320 Emit(opcode, g.DefineAsRegister(node), g.UseRegister(buffer),
367 Emit(opcode, g.NoOutput(), g.UseRegister(buffer),
376 Emit(opcode, g.NoOutput(), g.UseRegister(buffer), g.UseRegister(offset),
437 selector->Emit(opcode, output_count, outputs, input_count, inputs);
454 Emit(kX64Movzxbl, g.DefineAsRegister(node), g.Use(m.left().node()));
456 Emit(kX64Movzxwl, g.DefineAsRegister(node), g.Use(m.left().node()))
[all...] |
| /external/v8/src/wasm/ |
| asm-wasm-builder.cc | 183 builder_->current_function_builder_->Emit(opcode);
186 builder_->current_function_builder_->Emit(kExprEnd);
204 current_function_builder_->Emit(kExprIf);
211 current_function_builder_->Emit(kExprElse);
214 current_function_builder_->Emit(kExprEnd);
286 current_function_builder_->Emit(kExprI32LtS);
287 current_function_builder_->Emit(kExprIf);
291 current_function_builder_->Emit(kExprElse);
296 current_function_builder_->Emit(kExprI32GtS);
297 current_function_builder_->Emit(kExprIf)
[all...] |
| /external/llvm/include/llvm/Bitcode/ |
| BitstreamWriter.h | 115 void Emit(uint32_t Val, unsigned NumBits) {
136 Emit((uint32_t)Val, NumBits);
138 Emit((uint32_t)Val, 32);
139 Emit((uint32_t)(Val >> 32), NumBits-32);
152 assert(NumBits <= 32 && "Too many bits to emit!");
155 // Emit the bits with VBR encoding, NumBits-1 bits at a time.
157 Emit((Val & ((1 << (NumBits-1))-1)) | (1 << (NumBits-1)), NumBits);
161 Emit(Val, NumBits);
165 assert(NumBits <= 32 && "Too many bits to emit!");
171 // Emit the bits with VBR encoding, NumBits-1 bits at a time
[all...] |
| /external/v8/src/compiler/arm/ |
| instruction-selector-arm.cc | 83 selector->Emit(opcode, g.DefineAsRegister(node),
90 selector->Emit(opcode, g.DefineAsRegister(node),
278 selector->Emit(opcode, output_count, outputs, input_count, inputs);
296 selector->Emit(div_opcode, result_operand, left_operand, right_operand);
302 selector->Emit(f64i32_opcode, left_double_operand, left_operand);
303 selector->Emit(f64i32_opcode, right_double_operand, right_operand);
304 selector->Emit(kArmVdivF64, result_double_operand, left_double_operand,
306 selector->Emit(i32f64_opcode, result_operand, result_double_operand);
331 selector->Emit(kArmMls, result_operand, div_operand, right_operand,
335 selector->Emit(kArmMul, mul_operand, div_operand, right_operand)
[all...] |
| /external/v8/src/compiler/ |
| instruction-selector.h | 70 Instruction* Emit(InstructionCode opcode, InstructionOperand output,
72 Instruction* Emit(InstructionCode opcode, InstructionOperand output,
75 Instruction* Emit(InstructionCode opcode, InstructionOperand output,
78 Instruction* Emit(InstructionCode opcode, InstructionOperand output,
82 Instruction* Emit(InstructionCode opcode, InstructionOperand output,
86 Instruction* Emit(InstructionCode opcode, InstructionOperand output,
91 Instruction* Emit(InstructionCode opcode, InstructionOperand output,
96 Instruction* Emit(InstructionCode opcode, size_t output_count,
100 Instruction* Emit(Instruction* instr);
|
| instruction-selector.cc | 123 Instruction* InstructionSelector::Emit(InstructionCode opcode,
128 return Emit(opcode, output_count, &output, 0, nullptr, temp_count, temps);
132 Instruction* InstructionSelector::Emit(InstructionCode opcode,
137 return Emit(opcode, output_count, &output, 1, &a, temp_count, temps);
141 Instruction* InstructionSelector::Emit(InstructionCode opcode,
149 return Emit(opcode, output_count, &output, input_count, inputs, temp_count,
154 Instruction* InstructionSelector::Emit(InstructionCode opcode,
163 return Emit(opcode, output_count, &output, input_count, inputs, temp_count,
168 Instruction* InstructionSelector::Emit(
175 return Emit(opcode, output_count, &output, input_count, inputs, temp_count
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86WinCOFFStreamer.cpp | 32 // We have to emit the unwind info now, because this directive
40 EHStreamer.Emit(*this);
|
| /external/v8/test/mjsunit/regress/ |
| regress-460917.js | 10 // Emit a load that transitions a1 to FAST_ELEMENTS.
12 // Emit a store to a2 that assumes DOUBLE_ELEMENTS.
|
| /external/vixl/src/vixl/a64/ |
| assembler-a64.cc | 648 Emit(BR | Rn(xn));
654 Emit(BLR | Rn(xn));
660 Emit(RET | Rn(xn));
665 Emit(B | ImmUncondBranch(imm26));
670 Emit(B_cond | ImmCondBranch(imm19) | cond);
689 Emit(BL | ImmUncondBranch(imm26));
702 Emit(SF(rt) | CBZ | ImmCmpBranch(imm19) | Rt(rt));
716 Emit(SF(rt) | CBNZ | ImmCmpBranch(imm19) | Rt(rt));
735 Emit(op | (vd.IsQ() ? NEON_Q : 0) | Rm(vm) | Rn(vn) | Rd(vd));
841 Emit(TBZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt))
[all...] |
| /external/v8/src/compiler/ppc/ |
| instruction-selector-ppc.cc | 77 selector->Emit(opcode, g.DefineAsRegister(node),
84 selector->Emit(opcode, g.DefineAsRegister(node),
92 selector->Emit(opcode, g.DefineAsRegister(node),
112 selector->Emit(opcode, output_count, outputs, 1, inputs);
152 selector->Emit(opcode, output_count, outputs, input_count, inputs);
210 Emit(opcode | AddressingModeField::encode(kMode_MRI),
213 Emit(opcode | AddressingModeField::encode(kMode_MRI),
216 Emit(opcode | AddressingModeField::encode(kMode_MRR),
272 Emit(code, 0, nullptr, input_count, inputs, temp_count, temps);
311 Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput()
[all...] |
| /external/v8/src/compiler/ia32/ |
| instruction-selector-ia32.cc | 167 selector->Emit(opcode, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
174 selector->Emit(opcode, g.DefineAsRegister(node),
185 selector->Emit(avx_opcode, g.DefineAsRegister(node), operand0, operand1);
187 selector->Emit(sse_opcode, g.DefineSameAsFirst(node), operand0, operand1);
196 selector->Emit(avx_opcode, g.DefineAsRegister(node), g.Use(input));
198 selector->Emit(sse_opcode, g.DefineSameAsFirst(node), g.UseRegister(input));
243 Emit(code, 1, outputs, input_count, inputs);
291 Emit(code, 0, nullptr, input_count, inputs, temp_count, temps);
336 Emit(code, 0, static_cast<InstructionOperand*>(nullptr), input_count,
377 Emit(opcode | AddressingModeField::encode(kMode_MRI)
[all...] |
| /external/v8/src/compiler/s390/ |
| instruction-selector-s390.cc | 74 selector->Emit(opcode, g.DefineAsRegister(node),
80 selector->Emit(opcode, g.DefineAsRegister(node),
88 selector->Emit(opcode, g.DefineAsRegister(node),
107 selector->Emit(opcode, output_count, outputs, 1, inputs);
146 selector->Emit(opcode, output_count, outputs, input_count, inputs);
202 Emit(opcode | AddressingModeField::encode(kMode_MRI),
205 Emit(opcode | AddressingModeField::encode(kMode_MRI),
208 Emit(opcode | AddressingModeField::encode(kMode_MRR),
263 Emit(code, 0, nullptr, input_count, inputs, temp_count, temps);
302 Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput()
[all...] |
| /external/v8/src/compiler/arm64/ |
| instruction-selector-arm64.cc | 143 selector->Emit(opcode, g.DefineAsRegister(node),
150 selector->Emit(opcode, g.DefineAsRegister(node),
159 selector->Emit(opcode, g.DefineAsRegister(node),
401 selector->Emit(opcode, output_count, outputs, input_count, inputs);
422 selector->Emit(negate_opcode, g.DefineAsRegister(node),
510 Emit(opcode, arraysize(outputs), outputs, input_count, inputs);
562 Emit(code, 0, nullptr, input_count, inputs, temp_count, temps);
618 Emit(opcode, 0, nullptr, input_count, inputs);
662 Emit(opcode, g.DefineAsRegister(node), g.UseRegister(buffer),
667 Emit(opcode, g.DefineAsRegister(node), g.UseRegister(buffer)
[all...] |
| /external/v8/src/arm64/ |
| assembler-arm64.cc | 383 void ConstPool::Emit(bool require_jump) {
393 // Emit the constant pool. It is preceded by an optional branch if
411 // Emit branch if required
417 // Emit the header.
423 // Emit constant pool entries.
463 assm_->Emit(LDR_x_lit |
533 // Emit unique entries.
591 // Emit constant pool if necessary.
898 // * no_const_pool_before_ < next_constant_pool_check_ and the next emit
956 Emit(BLR | Rn(xzr))
[all...] |
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-mips-elf/ |
| emit-relocs-1.d | 1 #name: Emit relocs 1
2 #source: emit-relocs-1a.s -march=from-abi -mabi=n32 -EB
3 #source: emit-relocs-1b.s -march=from-abi -mabi=n32 -EB
4 #ld: -q -T emit-relocs-1.ld -melf32btsmipn32
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-nios2/ |
| emit-relocs-1.d | 1 #name: Emit relocs 1
2 #source: emit-relocs-1a.s
3 #source: emit-relocs-1b.s
4 #ld: -q -T emit-relocs-1.ld
|
| /art/compiler/utils/arm/ |
| assembler_arm32.cc | 212 Emit(encoding);
228 Emit(encoding);
247 Emit(encoding);
266 Emit(encoding);
567 void Arm32Assembler::Emit(int32_t value) {
569 buffer_.Emit<int32_t>(value);
589 Emit(encoding);
598 Emit(Arm32Assembler::EncodeBranchOffset(offset, encoding));
637 Emit(encoding);
653 Emit(encoding)
[all...] |
