| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinInstrInfo.cpp | 106 .addReg(SrcReg, getKillRegState(KillSrc));
112 .addReg(SrcReg, getKillRegState(KillSrc))
120 .addReg(SrcReg, getKillRegState(KillSrc));
126 .addReg(SrcReg, getKillRegState(KillSrc));
134 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(0);
139 .addReg(SrcReg, getKillRegState(KillSrc));
147 .addReg(SrcReg, getKillRegState(KillSrc));
153 .addReg(SrcReg, getKillRegState(KillSrc));
181 .addReg(SrcReg, getKillRegState(isKill))
189 .addReg(SrcReg, getKillRegState(isKill)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZInstrBuilder.h | 77 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
85 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(0)
86 .addReg(Reg2, getKillRegState(isKill2));
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 54 .addReg(SrcReg, getKillRegState(KillSrc)));
64 .addReg(SrcReg, getKillRegState(KillSrc));
91 .addReg(SrcReg, getKillRegState(isKill))
|
| MLxExpansionPass.cpp | 294 .addReg(Src1Reg, getKillRegState(Src1Kill))
295 .addReg(Src2Reg, getKillRegState(Src2Kill));
305 MIB.addReg(TmpReg, getKillRegState(true))
306 .addReg(AccReg, getKillRegState(AccKill));
308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
|
| ARMLoadStoreOptimizer.cpp | 707 .addReg(Base, getKillRegState(KillOldBase));
710 .addReg(Base, getKillRegState(KillOldBase))
720 .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset/4)
725 .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset)
729 .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset)
769 .addReg(Base, getKillRegState(BaseKill));
779 MIB.addReg(Base, getKillRegState(BaseKill));
785 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second));
806 MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second))
807 .addReg(Regs[1].first, getKillRegState(Regs[1].second))
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 320 .addReg(SrcReg, getKillRegState(KillSrc));
328 .addReg(SrcReg, getKillRegState(KillSrc));
332 .addReg(SrcReg, getKillRegState(KillSrc));
343 .addReg(SrcReg, getKillRegState(KillSrc));
360 .addReg(SrcReg, getKillRegState(KillSrc));
364 .addReg(SrcReg, getKillRegState(KillSrc));
408 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
411 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
414 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
417 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86InstrBuilder.h | 110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 40 .addReg(SrcReg, getKillRegState(KillSrc)));
69 .addReg(SrcReg, getKillRegState(isKill))
|
| MLxExpansionPass.cpp | 226 .addReg(Src1Reg, getKillRegState(Src1Kill))
227 .addReg(Src2Reg, getKillRegState(Src2Kill));
237 MIB.addReg(TmpReg, getKillRegState(true))
238 .addReg(AccReg, getKillRegState(AccKill));
240 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIInstrInfo.cpp | 49 .addReg(SrcReg, getKillRegState(KillSrc));
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 143 .addReg(Reg2, getKillRegState(Reg2IsKill))
144 .addReg(Reg1, getKillRegState(Reg1IsKill))
325 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
327 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
341 getKillRegState(isKill)),
350 getKillRegState(isKill)),
357 getKillRegState(isKill)),
366 getKillRegState(isKill)),
372 getKillRegState(isKill)),
377 getKillRegState(isKill))
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| AlphaInstrInfo.cpp | 128 .addReg(SrcReg, getKillRegState(KillSrc));
132 .addReg(SrcReg, getKillRegState(KillSrc));
136 .addReg(SrcReg, getKillRegState(KillSrc));
157 .addReg(SrcReg, getKillRegState(isKill))
161 .addReg(SrcReg, getKillRegState(isKill))
165 .addReg(SrcReg, getKillRegState(isKill))
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 275 .addReg(SrcReg, getKillRegState(KillSrc));
278 .addReg(SrcReg, getKillRegState(KillSrc));
281 .addReg(SrcReg, getKillRegState(KillSrc));
297 .addReg(SrcReg, getKillRegState(isKill));
300 .addReg(SrcReg, getKillRegState(isKill));
303 .addReg(SrcReg, getKillRegState(isKill));
|
| /external/llvm/lib/Target/BPF/ |
| BPFInstrInfo.cpp | 40 .addReg(SrcReg, getKillRegState(KillSrc));
56 .addReg(SrcReg, getKillRegState(IsKill))
|
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 138 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
146 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
147 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 286 .addReg(Src, getKillRegState(IsKill));
371 .addReg(Src0, getKillRegState(KillSrc0), SubReg0)
372 .addReg(Src1, getKillRegState(KillSrc1), SubReg1);
|
| AArch64InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 55 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
59 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
104 .addReg(SrcReg, getKillRegState(KillSrc));
|
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 55 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
59 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
104 .addReg(SrcReg, getKillRegState(KillSrc));
|
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 343 .addReg(SrcReg, getKillRegState(KillSrc))
355 .addReg(SrcReg, getKillRegState(KillSrc));
371 .addReg(SrcReg, getKillRegState(isKill))
|
| XCoreRegisterInfo.cpp | 245 .addReg(Reg, getKillRegState(isKill))
266 .addReg(Reg, getKillRegState(isKill))
295 .addReg(Reg, getKillRegState(isKill))
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonNewValueJump.cpp | 646 .addReg(cmpReg1, getKillRegState(MO1IsKill))
647 .addReg(cmpOp2, getKillRegState(MO2IsKill))
657 .addReg(cmpReg1, getKillRegState(MO1IsKill))
663 .addReg(cmpReg1, getKillRegState(MO1IsKill))
|
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 78 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
114 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
148 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
191 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| TargetInstrInfoImpl.cpp | 101 .addReg(Reg2, getKillRegState(Reg2IsKill))
102 .addReg(Reg1, getKillRegState(Reg2IsKill));
105 .addReg(Reg2, getKillRegState(Reg2IsKill))
106 .addReg(Reg1, getKillRegState(Reg2IsKill));
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | [all...] |
