| /external/llvm/utils/TableGen/ |
| CallingConvEmitter.cpp | 223 MVT::SimpleValueType DestVT = getValueType(DestTy);
224 O << IndentStr << "LocVT = " << getEnumName(DestVT) <<";\n";
225 if (MVT(DestVT).isFloatingPoint()) {
237 MVT::SimpleValueType DestVT = getValueType(DestTy);
238 O << IndentStr << "LocVT = " << getEnumName(DestVT) << ";\n";
239 if (MVT(DestVT).isFloatingPoint()) {
|
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 139 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
140 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
143 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
145 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
146 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
148 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
953 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
955 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 164 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
911 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
913 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 691 EVT DestVT = TLI->getRegisterType(NewVT);
692 RegisterVT = DestVT;
693 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
694 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
[all...] |
| LegalizeVectorTypes.cpp | 207 EVT DestVT = N->getValueType(0).getVectorElementType();
209 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
[all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 188 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
189 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
[all...] |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 175 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | 246 EVT DestVT = N->getValueType(0).getVectorElementType();
265 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 624 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
631 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
