1 //===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the TargetLoweringBase class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetLowering.h" 15 #include "llvm/ADT/BitVector.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/Triple.h" 18 #include "llvm/CodeGen/Analysis.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineJumpTableInfo.h" 23 #include "llvm/CodeGen/StackMaps.h" 24 #include "llvm/IR/DataLayout.h" 25 #include "llvm/IR/DerivedTypes.h" 26 #include "llvm/IR/GlobalVariable.h" 27 #include "llvm/IR/Mangler.h" 28 #include "llvm/MC/MCAsmInfo.h" 29 #include "llvm/MC/MCContext.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/Support/BranchProbability.h" 32 #include "llvm/Support/CommandLine.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include "llvm/Support/MathExtras.h" 35 #include "llvm/Target/TargetLoweringObjectFile.h" 36 #include "llvm/Target/TargetMachine.h" 37 #include "llvm/Target/TargetRegisterInfo.h" 38 #include "llvm/Target/TargetSubtargetInfo.h" 39 #include <cctype> 40 using namespace llvm; 41 42 static cl::opt<bool> JumpIsExpensiveOverride( 43 "jump-is-expensive", cl::init(false), 44 cl::desc("Do not create extra branches to split comparison logic."), 45 cl::Hidden); 46 47 // Although this default value is arbitrary, it is not random. It is assumed 48 // that a condition that evaluates the same way by a higher percentage than this 49 // is best represented as control flow. Therefore, the default value N should be 50 // set such that the win from N% correct executions is greater than the loss 51 // from (100 - N)% mispredicted executions for the majority of intended targets. 52 static cl::opt<int> MinPercentageForPredictableBranch( 53 "min-predictable-branch", cl::init(99), 54 cl::desc("Minimum percentage (0-100) that a condition must be either true " 55 "or false to assume that the condition is predictable"), 56 cl::Hidden); 57 58 /// InitLibcallNames - Set default libcall names. 59 /// 60 static void InitLibcallNames(const char **Names, const Triple &TT) { 61 Names[RTLIB::SHL_I16] = "__ashlhi3"; 62 Names[RTLIB::SHL_I32] = "__ashlsi3"; 63 Names[RTLIB::SHL_I64] = "__ashldi3"; 64 Names[RTLIB::SHL_I128] = "__ashlti3"; 65 Names[RTLIB::SRL_I16] = "__lshrhi3"; 66 Names[RTLIB::SRL_I32] = "__lshrsi3"; 67 Names[RTLIB::SRL_I64] = "__lshrdi3"; 68 Names[RTLIB::SRL_I128] = "__lshrti3"; 69 Names[RTLIB::SRA_I16] = "__ashrhi3"; 70 Names[RTLIB::SRA_I32] = "__ashrsi3"; 71 Names[RTLIB::SRA_I64] = "__ashrdi3"; 72 Names[RTLIB::SRA_I128] = "__ashrti3"; 73 Names[RTLIB::MUL_I8] = "__mulqi3"; 74 Names[RTLIB::MUL_I16] = "__mulhi3"; 75 Names[RTLIB::MUL_I32] = "__mulsi3"; 76 Names[RTLIB::MUL_I64] = "__muldi3"; 77 Names[RTLIB::MUL_I128] = "__multi3"; 78 Names[RTLIB::MULO_I32] = "__mulosi4"; 79 Names[RTLIB::MULO_I64] = "__mulodi4"; 80 Names[RTLIB::MULO_I128] = "__muloti4"; 81 Names[RTLIB::SDIV_I8] = "__divqi3"; 82 Names[RTLIB::SDIV_I16] = "__divhi3"; 83 Names[RTLIB::SDIV_I32] = "__divsi3"; 84 Names[RTLIB::SDIV_I64] = "__divdi3"; 85 Names[RTLIB::SDIV_I128] = "__divti3"; 86 Names[RTLIB::UDIV_I8] = "__udivqi3"; 87 Names[RTLIB::UDIV_I16] = "__udivhi3"; 88 Names[RTLIB::UDIV_I32] = "__udivsi3"; 89 Names[RTLIB::UDIV_I64] = "__udivdi3"; 90 Names[RTLIB::UDIV_I128] = "__udivti3"; 91 Names[RTLIB::SREM_I8] = "__modqi3"; 92 Names[RTLIB::SREM_I16] = "__modhi3"; 93 Names[RTLIB::SREM_I32] = "__modsi3"; 94 Names[RTLIB::SREM_I64] = "__moddi3"; 95 Names[RTLIB::SREM_I128] = "__modti3"; 96 Names[RTLIB::UREM_I8] = "__umodqi3"; 97 Names[RTLIB::UREM_I16] = "__umodhi3"; 98 Names[RTLIB::UREM_I32] = "__umodsi3"; 99 Names[RTLIB::UREM_I64] = "__umoddi3"; 100 Names[RTLIB::UREM_I128] = "__umodti3"; 101 102 Names[RTLIB::NEG_I32] = "__negsi2"; 103 Names[RTLIB::NEG_I64] = "__negdi2"; 104 Names[RTLIB::ADD_F32] = "__addsf3"; 105 Names[RTLIB::ADD_F64] = "__adddf3"; 106 Names[RTLIB::ADD_F80] = "__addxf3"; 107 Names[RTLIB::ADD_F128] = "__addtf3"; 108 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 109 Names[RTLIB::SUB_F32] = "__subsf3"; 110 Names[RTLIB::SUB_F64] = "__subdf3"; 111 Names[RTLIB::SUB_F80] = "__subxf3"; 112 Names[RTLIB::SUB_F128] = "__subtf3"; 113 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 114 Names[RTLIB::MUL_F32] = "__mulsf3"; 115 Names[RTLIB::MUL_F64] = "__muldf3"; 116 Names[RTLIB::MUL_F80] = "__mulxf3"; 117 Names[RTLIB::MUL_F128] = "__multf3"; 118 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 119 Names[RTLIB::DIV_F32] = "__divsf3"; 120 Names[RTLIB::DIV_F64] = "__divdf3"; 121 Names[RTLIB::DIV_F80] = "__divxf3"; 122 Names[RTLIB::DIV_F128] = "__divtf3"; 123 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 124 Names[RTLIB::REM_F32] = "fmodf"; 125 Names[RTLIB::REM_F64] = "fmod"; 126 Names[RTLIB::REM_F80] = "fmodl"; 127 Names[RTLIB::REM_F128] = "fmodl"; 128 Names[RTLIB::REM_PPCF128] = "fmodl"; 129 Names[RTLIB::FMA_F32] = "fmaf"; 130 Names[RTLIB::FMA_F64] = "fma"; 131 Names[RTLIB::FMA_F80] = "fmal"; 132 Names[RTLIB::FMA_F128] = "fmal"; 133 Names[RTLIB::FMA_PPCF128] = "fmal"; 134 Names[RTLIB::POWI_F32] = "__powisf2"; 135 Names[RTLIB::POWI_F64] = "__powidf2"; 136 Names[RTLIB::POWI_F80] = "__powixf2"; 137 Names[RTLIB::POWI_F128] = "__powitf2"; 138 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 139 Names[RTLIB::SQRT_F32] = "sqrtf"; 140 Names[RTLIB::SQRT_F64] = "sqrt"; 141 Names[RTLIB::SQRT_F80] = "sqrtl"; 142 Names[RTLIB::SQRT_F128] = "sqrtl"; 143 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 144 Names[RTLIB::LOG_F32] = "logf"; 145 Names[RTLIB::LOG_F64] = "log"; 146 Names[RTLIB::LOG_F80] = "logl"; 147 Names[RTLIB::LOG_F128] = "logl"; 148 Names[RTLIB::LOG_PPCF128] = "logl"; 149 Names[RTLIB::LOG2_F32] = "log2f"; 150 Names[RTLIB::LOG2_F64] = "log2"; 151 Names[RTLIB::LOG2_F80] = "log2l"; 152 Names[RTLIB::LOG2_F128] = "log2l"; 153 Names[RTLIB::LOG2_PPCF128] = "log2l"; 154 Names[RTLIB::LOG10_F32] = "log10f"; 155 Names[RTLIB::LOG10_F64] = "log10"; 156 Names[RTLIB::LOG10_F80] = "log10l"; 157 Names[RTLIB::LOG10_F128] = "log10l"; 158 Names[RTLIB::LOG10_PPCF128] = "log10l"; 159 Names[RTLIB::EXP_F32] = "expf"; 160 Names[RTLIB::EXP_F64] = "exp"; 161 Names[RTLIB::EXP_F80] = "expl"; 162 Names[RTLIB::EXP_F128] = "expl"; 163 Names[RTLIB::EXP_PPCF128] = "expl"; 164 Names[RTLIB::EXP2_F32] = "exp2f"; 165 Names[RTLIB::EXP2_F64] = "exp2"; 166 Names[RTLIB::EXP2_F80] = "exp2l"; 167 Names[RTLIB::EXP2_F128] = "exp2l"; 168 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 169 Names[RTLIB::SIN_F32] = "sinf"; 170 Names[RTLIB::SIN_F64] = "sin"; 171 Names[RTLIB::SIN_F80] = "sinl"; 172 Names[RTLIB::SIN_F128] = "sinl"; 173 Names[RTLIB::SIN_PPCF128] = "sinl"; 174 Names[RTLIB::COS_F32] = "cosf"; 175 Names[RTLIB::COS_F64] = "cos"; 176 Names[RTLIB::COS_F80] = "cosl"; 177 Names[RTLIB::COS_F128] = "cosl"; 178 Names[RTLIB::COS_PPCF128] = "cosl"; 179 Names[RTLIB::POW_F32] = "powf"; 180 Names[RTLIB::POW_F64] = "pow"; 181 Names[RTLIB::POW_F80] = "powl"; 182 Names[RTLIB::POW_F128] = "powl"; 183 Names[RTLIB::POW_PPCF128] = "powl"; 184 Names[RTLIB::CEIL_F32] = "ceilf"; 185 Names[RTLIB::CEIL_F64] = "ceil"; 186 Names[RTLIB::CEIL_F80] = "ceill"; 187 Names[RTLIB::CEIL_F128] = "ceill"; 188 Names[RTLIB::CEIL_PPCF128] = "ceill"; 189 Names[RTLIB::TRUNC_F32] = "truncf"; 190 Names[RTLIB::TRUNC_F64] = "trunc"; 191 Names[RTLIB::TRUNC_F80] = "truncl"; 192 Names[RTLIB::TRUNC_F128] = "truncl"; 193 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 194 Names[RTLIB::RINT_F32] = "rintf"; 195 Names[RTLIB::RINT_F64] = "rint"; 196 Names[RTLIB::RINT_F80] = "rintl"; 197 Names[RTLIB::RINT_F128] = "rintl"; 198 Names[RTLIB::RINT_PPCF128] = "rintl"; 199 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 200 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 201 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 202 Names[RTLIB::NEARBYINT_F128] = "nearbyintl"; 203 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 204 Names[RTLIB::ROUND_F32] = "roundf"; 205 Names[RTLIB::ROUND_F64] = "round"; 206 Names[RTLIB::ROUND_F80] = "roundl"; 207 Names[RTLIB::ROUND_F128] = "roundl"; 208 Names[RTLIB::ROUND_PPCF128] = "roundl"; 209 Names[RTLIB::FLOOR_F32] = "floorf"; 210 Names[RTLIB::FLOOR_F64] = "floor"; 211 Names[RTLIB::FLOOR_F80] = "floorl"; 212 Names[RTLIB::FLOOR_F128] = "floorl"; 213 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 214 Names[RTLIB::FMIN_F32] = "fminf"; 215 Names[RTLIB::FMIN_F64] = "fmin"; 216 Names[RTLIB::FMIN_F80] = "fminl"; 217 Names[RTLIB::FMIN_F128] = "fminl"; 218 Names[RTLIB::FMIN_PPCF128] = "fminl"; 219 Names[RTLIB::FMAX_F32] = "fmaxf"; 220 Names[RTLIB::FMAX_F64] = "fmax"; 221 Names[RTLIB::FMAX_F80] = "fmaxl"; 222 Names[RTLIB::FMAX_F128] = "fmaxl"; 223 Names[RTLIB::FMAX_PPCF128] = "fmaxl"; 224 Names[RTLIB::ROUND_F32] = "roundf"; 225 Names[RTLIB::ROUND_F64] = "round"; 226 Names[RTLIB::ROUND_F80] = "roundl"; 227 Names[RTLIB::ROUND_F128] = "roundl"; 228 Names[RTLIB::ROUND_PPCF128] = "roundl"; 229 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 230 Names[RTLIB::COPYSIGN_F64] = "copysign"; 231 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 232 Names[RTLIB::COPYSIGN_F128] = "copysignl"; 233 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 234 Names[RTLIB::FPEXT_F32_PPCF128] = "__gcc_stoq"; 235 Names[RTLIB::FPEXT_F64_PPCF128] = "__gcc_dtoq"; 236 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2"; 237 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2"; 238 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 239 if (TT.isOSDarwin()) { 240 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead 241 // of the gnueabi-style __gnu_*_ieee. 242 // FIXME: What about other targets? 243 Names[RTLIB::FPEXT_F16_F32] = "__extendhfsf2"; 244 Names[RTLIB::FPROUND_F32_F16] = "__truncsfhf2"; 245 } else { 246 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 247 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 248 } 249 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2"; 250 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2"; 251 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2"; 252 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2"; 253 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 254 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 255 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2"; 256 Names[RTLIB::FPROUND_PPCF128_F32] = "__gcc_qtos"; 257 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 258 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2"; 259 Names[RTLIB::FPROUND_PPCF128_F64] = "__gcc_qtod"; 260 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 261 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 262 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 263 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 264 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 265 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 266 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 267 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 268 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 269 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi"; 270 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi"; 271 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti"; 272 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__gcc_qtou"; 273 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 274 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 275 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 276 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 277 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 278 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 279 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 280 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 281 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 282 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 283 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 284 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi"; 285 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi"; 286 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti"; 287 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 288 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 289 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 290 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 291 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 292 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 293 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf"; 294 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__gcc_itoq"; 295 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 296 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 297 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 298 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf"; 299 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 300 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 301 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 302 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 303 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf"; 304 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 305 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 306 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 307 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 308 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf"; 309 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__gcc_utoq"; 310 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 311 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 312 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 313 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf"; 314 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 315 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 316 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 317 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 318 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf"; 319 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 320 Names[RTLIB::OEQ_F32] = "__eqsf2"; 321 Names[RTLIB::OEQ_F64] = "__eqdf2"; 322 Names[RTLIB::OEQ_F128] = "__eqtf2"; 323 Names[RTLIB::OEQ_PPCF128] = "__gcc_qeq"; 324 Names[RTLIB::UNE_F32] = "__nesf2"; 325 Names[RTLIB::UNE_F64] = "__nedf2"; 326 Names[RTLIB::UNE_F128] = "__netf2"; 327 Names[RTLIB::UNE_PPCF128] = "__gcc_qne"; 328 Names[RTLIB::OGE_F32] = "__gesf2"; 329 Names[RTLIB::OGE_F64] = "__gedf2"; 330 Names[RTLIB::OGE_F128] = "__getf2"; 331 Names[RTLIB::OGE_PPCF128] = "__gcc_qge"; 332 Names[RTLIB::OLT_F32] = "__ltsf2"; 333 Names[RTLIB::OLT_F64] = "__ltdf2"; 334 Names[RTLIB::OLT_F128] = "__lttf2"; 335 Names[RTLIB::OLT_PPCF128] = "__gcc_qlt"; 336 Names[RTLIB::OLE_F32] = "__lesf2"; 337 Names[RTLIB::OLE_F64] = "__ledf2"; 338 Names[RTLIB::OLE_F128] = "__letf2"; 339 Names[RTLIB::OLE_PPCF128] = "__gcc_qle"; 340 Names[RTLIB::OGT_F32] = "__gtsf2"; 341 Names[RTLIB::OGT_F64] = "__gtdf2"; 342 Names[RTLIB::OGT_F128] = "__gttf2"; 343 Names[RTLIB::OGT_PPCF128] = "__gcc_qgt"; 344 Names[RTLIB::UO_F32] = "__unordsf2"; 345 Names[RTLIB::UO_F64] = "__unorddf2"; 346 Names[RTLIB::UO_F128] = "__unordtf2"; 347 Names[RTLIB::UO_PPCF128] = "__gcc_qunord"; 348 Names[RTLIB::O_F32] = "__unordsf2"; 349 Names[RTLIB::O_F64] = "__unorddf2"; 350 Names[RTLIB::O_F128] = "__unordtf2"; 351 Names[RTLIB::O_PPCF128] = "__gcc_qunord"; 352 Names[RTLIB::MEMCPY] = "memcpy"; 353 Names[RTLIB::MEMMOVE] = "memmove"; 354 Names[RTLIB::MEMSET] = "memset"; 355 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 356 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 357 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 358 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 359 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 360 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16"; 361 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 362 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 363 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 364 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 365 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16"; 366 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 367 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 368 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 369 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 370 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16"; 371 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 372 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 373 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 374 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 375 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16"; 376 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 377 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 378 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 379 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 380 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16"; 381 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 382 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 383 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 384 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 385 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16"; 386 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 387 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 388 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 389 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 390 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16"; 391 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 392 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 393 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 394 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 395 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16"; 396 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1"; 397 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2"; 398 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4"; 399 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8"; 400 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16"; 401 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1"; 402 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2"; 403 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4"; 404 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8"; 405 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16"; 406 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1"; 407 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2"; 408 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4"; 409 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8"; 410 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16"; 411 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1"; 412 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2"; 413 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4"; 414 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8"; 415 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16"; 416 417 Names[RTLIB::ATOMIC_LOAD] = "__atomic_load"; 418 Names[RTLIB::ATOMIC_LOAD_1] = "__atomic_load_1"; 419 Names[RTLIB::ATOMIC_LOAD_2] = "__atomic_load_2"; 420 Names[RTLIB::ATOMIC_LOAD_4] = "__atomic_load_4"; 421 Names[RTLIB::ATOMIC_LOAD_8] = "__atomic_load_8"; 422 Names[RTLIB::ATOMIC_LOAD_16] = "__atomic_load_16"; 423 424 Names[RTLIB::ATOMIC_STORE] = "__atomic_store"; 425 Names[RTLIB::ATOMIC_STORE_1] = "__atomic_store_1"; 426 Names[RTLIB::ATOMIC_STORE_2] = "__atomic_store_2"; 427 Names[RTLIB::ATOMIC_STORE_4] = "__atomic_store_4"; 428 Names[RTLIB::ATOMIC_STORE_8] = "__atomic_store_8"; 429 Names[RTLIB::ATOMIC_STORE_16] = "__atomic_store_16"; 430 431 Names[RTLIB::ATOMIC_EXCHANGE] = "__atomic_exchange"; 432 Names[RTLIB::ATOMIC_EXCHANGE_1] = "__atomic_exchange_1"; 433 Names[RTLIB::ATOMIC_EXCHANGE_2] = "__atomic_exchange_2"; 434 Names[RTLIB::ATOMIC_EXCHANGE_4] = "__atomic_exchange_4"; 435 Names[RTLIB::ATOMIC_EXCHANGE_8] = "__atomic_exchange_8"; 436 Names[RTLIB::ATOMIC_EXCHANGE_16] = "__atomic_exchange_16"; 437 438 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE] = "__atomic_compare_exchange"; 439 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_1] = "__atomic_compare_exchange_1"; 440 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_2] = "__atomic_compare_exchange_2"; 441 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_4] = "__atomic_compare_exchange_4"; 442 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_8] = "__atomic_compare_exchange_8"; 443 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_16] = "__atomic_compare_exchange_16"; 444 445 Names[RTLIB::ATOMIC_FETCH_ADD_1] = "__atomic_fetch_add_1"; 446 Names[RTLIB::ATOMIC_FETCH_ADD_2] = "__atomic_fetch_add_2"; 447 Names[RTLIB::ATOMIC_FETCH_ADD_4] = "__atomic_fetch_add_4"; 448 Names[RTLIB::ATOMIC_FETCH_ADD_8] = "__atomic_fetch_add_8"; 449 Names[RTLIB::ATOMIC_FETCH_ADD_16] = "__atomic_fetch_add_16"; 450 Names[RTLIB::ATOMIC_FETCH_SUB_1] = "__atomic_fetch_sub_1"; 451 Names[RTLIB::ATOMIC_FETCH_SUB_2] = "__atomic_fetch_sub_2"; 452 Names[RTLIB::ATOMIC_FETCH_SUB_4] = "__atomic_fetch_sub_4"; 453 Names[RTLIB::ATOMIC_FETCH_SUB_8] = "__atomic_fetch_sub_8"; 454 Names[RTLIB::ATOMIC_FETCH_SUB_16] = "__atomic_fetch_sub_16"; 455 Names[RTLIB::ATOMIC_FETCH_AND_1] = "__atomic_fetch_and_1"; 456 Names[RTLIB::ATOMIC_FETCH_AND_2] = "__atomic_fetch_and_2"; 457 Names[RTLIB::ATOMIC_FETCH_AND_4] = "__atomic_fetch_and_4"; 458 Names[RTLIB::ATOMIC_FETCH_AND_8] = "__atomic_fetch_and_8"; 459 Names[RTLIB::ATOMIC_FETCH_AND_16] = "__atomic_fetch_and_16"; 460 Names[RTLIB::ATOMIC_FETCH_OR_1] = "__atomic_fetch_or_1"; 461 Names[RTLIB::ATOMIC_FETCH_OR_2] = "__atomic_fetch_or_2"; 462 Names[RTLIB::ATOMIC_FETCH_OR_4] = "__atomic_fetch_or_4"; 463 Names[RTLIB::ATOMIC_FETCH_OR_8] = "__atomic_fetch_or_8"; 464 Names[RTLIB::ATOMIC_FETCH_OR_16] = "__atomic_fetch_or_16"; 465 Names[RTLIB::ATOMIC_FETCH_XOR_1] = "__atomic_fetch_xor_1"; 466 Names[RTLIB::ATOMIC_FETCH_XOR_2] = "__atomic_fetch_xor_2"; 467 Names[RTLIB::ATOMIC_FETCH_XOR_4] = "__atomic_fetch_xor_4"; 468 Names[RTLIB::ATOMIC_FETCH_XOR_8] = "__atomic_fetch_xor_8"; 469 Names[RTLIB::ATOMIC_FETCH_XOR_16] = "__atomic_fetch_xor_16"; 470 Names[RTLIB::ATOMIC_FETCH_NAND_1] = "__atomic_fetch_nand_1"; 471 Names[RTLIB::ATOMIC_FETCH_NAND_2] = "__atomic_fetch_nand_2"; 472 Names[RTLIB::ATOMIC_FETCH_NAND_4] = "__atomic_fetch_nand_4"; 473 Names[RTLIB::ATOMIC_FETCH_NAND_8] = "__atomic_fetch_nand_8"; 474 Names[RTLIB::ATOMIC_FETCH_NAND_16] = "__atomic_fetch_nand_16"; 475 476 if (TT.isGNUEnvironment()) { 477 Names[RTLIB::SINCOS_F32] = "sincosf"; 478 Names[RTLIB::SINCOS_F64] = "sincos"; 479 Names[RTLIB::SINCOS_F80] = "sincosl"; 480 Names[RTLIB::SINCOS_F128] = "sincosl"; 481 Names[RTLIB::SINCOS_PPCF128] = "sincosl"; 482 } 483 484 if (!TT.isOSOpenBSD()) { 485 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail"; 486 } 487 488 Names[RTLIB::DEOPTIMIZE] = "__llvm_deoptimize"; 489 } 490 491 /// InitLibcallCallingConvs - Set default libcall CallingConvs. 492 /// 493 static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 494 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 495 CCs[i] = CallingConv::C; 496 } 497 } 498 499 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 500 /// UNKNOWN_LIBCALL if there is none. 501 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 502 if (OpVT == MVT::f16) { 503 if (RetVT == MVT::f32) 504 return FPEXT_F16_F32; 505 } else if (OpVT == MVT::f32) { 506 if (RetVT == MVT::f64) 507 return FPEXT_F32_F64; 508 if (RetVT == MVT::f128) 509 return FPEXT_F32_F128; 510 if (RetVT == MVT::ppcf128) 511 return FPEXT_F32_PPCF128; 512 } else if (OpVT == MVT::f64) { 513 if (RetVT == MVT::f128) 514 return FPEXT_F64_F128; 515 else if (RetVT == MVT::ppcf128) 516 return FPEXT_F64_PPCF128; 517 } 518 519 return UNKNOWN_LIBCALL; 520 } 521 522 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 523 /// UNKNOWN_LIBCALL if there is none. 524 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 525 if (RetVT == MVT::f16) { 526 if (OpVT == MVT::f32) 527 return FPROUND_F32_F16; 528 if (OpVT == MVT::f64) 529 return FPROUND_F64_F16; 530 if (OpVT == MVT::f80) 531 return FPROUND_F80_F16; 532 if (OpVT == MVT::f128) 533 return FPROUND_F128_F16; 534 if (OpVT == MVT::ppcf128) 535 return FPROUND_PPCF128_F16; 536 } else if (RetVT == MVT::f32) { 537 if (OpVT == MVT::f64) 538 return FPROUND_F64_F32; 539 if (OpVT == MVT::f80) 540 return FPROUND_F80_F32; 541 if (OpVT == MVT::f128) 542 return FPROUND_F128_F32; 543 if (OpVT == MVT::ppcf128) 544 return FPROUND_PPCF128_F32; 545 } else if (RetVT == MVT::f64) { 546 if (OpVT == MVT::f80) 547 return FPROUND_F80_F64; 548 if (OpVT == MVT::f128) 549 return FPROUND_F128_F64; 550 if (OpVT == MVT::ppcf128) 551 return FPROUND_PPCF128_F64; 552 } 553 554 return UNKNOWN_LIBCALL; 555 } 556 557 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 558 /// UNKNOWN_LIBCALL if there is none. 559 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 560 if (OpVT == MVT::f32) { 561 if (RetVT == MVT::i32) 562 return FPTOSINT_F32_I32; 563 if (RetVT == MVT::i64) 564 return FPTOSINT_F32_I64; 565 if (RetVT == MVT::i128) 566 return FPTOSINT_F32_I128; 567 } else if (OpVT == MVT::f64) { 568 if (RetVT == MVT::i32) 569 return FPTOSINT_F64_I32; 570 if (RetVT == MVT::i64) 571 return FPTOSINT_F64_I64; 572 if (RetVT == MVT::i128) 573 return FPTOSINT_F64_I128; 574 } else if (OpVT == MVT::f80) { 575 if (RetVT == MVT::i32) 576 return FPTOSINT_F80_I32; 577 if (RetVT == MVT::i64) 578 return FPTOSINT_F80_I64; 579 if (RetVT == MVT::i128) 580 return FPTOSINT_F80_I128; 581 } else if (OpVT == MVT::f128) { 582 if (RetVT == MVT::i32) 583 return FPTOSINT_F128_I32; 584 if (RetVT == MVT::i64) 585 return FPTOSINT_F128_I64; 586 if (RetVT == MVT::i128) 587 return FPTOSINT_F128_I128; 588 } else if (OpVT == MVT::ppcf128) { 589 if (RetVT == MVT::i32) 590 return FPTOSINT_PPCF128_I32; 591 if (RetVT == MVT::i64) 592 return FPTOSINT_PPCF128_I64; 593 if (RetVT == MVT::i128) 594 return FPTOSINT_PPCF128_I128; 595 } 596 return UNKNOWN_LIBCALL; 597 } 598 599 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 600 /// UNKNOWN_LIBCALL if there is none. 601 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 602 if (OpVT == MVT::f32) { 603 if (RetVT == MVT::i32) 604 return FPTOUINT_F32_I32; 605 if (RetVT == MVT::i64) 606 return FPTOUINT_F32_I64; 607 if (RetVT == MVT::i128) 608 return FPTOUINT_F32_I128; 609 } else if (OpVT == MVT::f64) { 610 if (RetVT == MVT::i32) 611 return FPTOUINT_F64_I32; 612 if (RetVT == MVT::i64) 613 return FPTOUINT_F64_I64; 614 if (RetVT == MVT::i128) 615 return FPTOUINT_F64_I128; 616 } else if (OpVT == MVT::f80) { 617 if (RetVT == MVT::i32) 618 return FPTOUINT_F80_I32; 619 if (RetVT == MVT::i64) 620 return FPTOUINT_F80_I64; 621 if (RetVT == MVT::i128) 622 return FPTOUINT_F80_I128; 623 } else if (OpVT == MVT::f128) { 624 if (RetVT == MVT::i32) 625 return FPTOUINT_F128_I32; 626 if (RetVT == MVT::i64) 627 return FPTOUINT_F128_I64; 628 if (RetVT == MVT::i128) 629 return FPTOUINT_F128_I128; 630 } else if (OpVT == MVT::ppcf128) { 631 if (RetVT == MVT::i32) 632 return FPTOUINT_PPCF128_I32; 633 if (RetVT == MVT::i64) 634 return FPTOUINT_PPCF128_I64; 635 if (RetVT == MVT::i128) 636 return FPTOUINT_PPCF128_I128; 637 } 638 return UNKNOWN_LIBCALL; 639 } 640 641 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 642 /// UNKNOWN_LIBCALL if there is none. 643 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 644 if (OpVT == MVT::i32) { 645 if (RetVT == MVT::f32) 646 return SINTTOFP_I32_F32; 647 if (RetVT == MVT::f64) 648 return SINTTOFP_I32_F64; 649 if (RetVT == MVT::f80) 650 return SINTTOFP_I32_F80; 651 if (RetVT == MVT::f128) 652 return SINTTOFP_I32_F128; 653 if (RetVT == MVT::ppcf128) 654 return SINTTOFP_I32_PPCF128; 655 } else if (OpVT == MVT::i64) { 656 if (RetVT == MVT::f32) 657 return SINTTOFP_I64_F32; 658 if (RetVT == MVT::f64) 659 return SINTTOFP_I64_F64; 660 if (RetVT == MVT::f80) 661 return SINTTOFP_I64_F80; 662 if (RetVT == MVT::f128) 663 return SINTTOFP_I64_F128; 664 if (RetVT == MVT::ppcf128) 665 return SINTTOFP_I64_PPCF128; 666 } else if (OpVT == MVT::i128) { 667 if (RetVT == MVT::f32) 668 return SINTTOFP_I128_F32; 669 if (RetVT == MVT::f64) 670 return SINTTOFP_I128_F64; 671 if (RetVT == MVT::f80) 672 return SINTTOFP_I128_F80; 673 if (RetVT == MVT::f128) 674 return SINTTOFP_I128_F128; 675 if (RetVT == MVT::ppcf128) 676 return SINTTOFP_I128_PPCF128; 677 } 678 return UNKNOWN_LIBCALL; 679 } 680 681 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 682 /// UNKNOWN_LIBCALL if there is none. 683 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 684 if (OpVT == MVT::i32) { 685 if (RetVT == MVT::f32) 686 return UINTTOFP_I32_F32; 687 if (RetVT == MVT::f64) 688 return UINTTOFP_I32_F64; 689 if (RetVT == MVT::f80) 690 return UINTTOFP_I32_F80; 691 if (RetVT == MVT::f128) 692 return UINTTOFP_I32_F128; 693 if (RetVT == MVT::ppcf128) 694 return UINTTOFP_I32_PPCF128; 695 } else if (OpVT == MVT::i64) { 696 if (RetVT == MVT::f32) 697 return UINTTOFP_I64_F32; 698 if (RetVT == MVT::f64) 699 return UINTTOFP_I64_F64; 700 if (RetVT == MVT::f80) 701 return UINTTOFP_I64_F80; 702 if (RetVT == MVT::f128) 703 return UINTTOFP_I64_F128; 704 if (RetVT == MVT::ppcf128) 705 return UINTTOFP_I64_PPCF128; 706 } else if (OpVT == MVT::i128) { 707 if (RetVT == MVT::f32) 708 return UINTTOFP_I128_F32; 709 if (RetVT == MVT::f64) 710 return UINTTOFP_I128_F64; 711 if (RetVT == MVT::f80) 712 return UINTTOFP_I128_F80; 713 if (RetVT == MVT::f128) 714 return UINTTOFP_I128_F128; 715 if (RetVT == MVT::ppcf128) 716 return UINTTOFP_I128_PPCF128; 717 } 718 return UNKNOWN_LIBCALL; 719 } 720 721 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { 722 #define OP_TO_LIBCALL(Name, Enum) \ 723 case Name: \ 724 switch (VT.SimpleTy) { \ 725 default: \ 726 return UNKNOWN_LIBCALL; \ 727 case MVT::i8: \ 728 return Enum##_1; \ 729 case MVT::i16: \ 730 return Enum##_2; \ 731 case MVT::i32: \ 732 return Enum##_4; \ 733 case MVT::i64: \ 734 return Enum##_8; \ 735 case MVT::i128: \ 736 return Enum##_16; \ 737 } 738 739 switch (Opc) { 740 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET) 741 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) 742 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD) 743 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB) 744 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND) 745 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR) 746 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR) 747 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND) 748 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX) 749 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX) 750 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN) 751 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN) 752 } 753 754 #undef OP_TO_LIBCALL 755 756 return UNKNOWN_LIBCALL; 757 } 758 759 /// InitCmpLibcallCCs - Set default comparison libcall CC. 760 /// 761 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 762 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 763 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 764 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 765 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 766 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ; 767 CCs[RTLIB::UNE_F32] = ISD::SETNE; 768 CCs[RTLIB::UNE_F64] = ISD::SETNE; 769 CCs[RTLIB::UNE_F128] = ISD::SETNE; 770 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE; 771 CCs[RTLIB::OGE_F32] = ISD::SETGE; 772 CCs[RTLIB::OGE_F64] = ISD::SETGE; 773 CCs[RTLIB::OGE_F128] = ISD::SETGE; 774 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE; 775 CCs[RTLIB::OLT_F32] = ISD::SETLT; 776 CCs[RTLIB::OLT_F64] = ISD::SETLT; 777 CCs[RTLIB::OLT_F128] = ISD::SETLT; 778 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT; 779 CCs[RTLIB::OLE_F32] = ISD::SETLE; 780 CCs[RTLIB::OLE_F64] = ISD::SETLE; 781 CCs[RTLIB::OLE_F128] = ISD::SETLE; 782 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE; 783 CCs[RTLIB::OGT_F32] = ISD::SETGT; 784 CCs[RTLIB::OGT_F64] = ISD::SETGT; 785 CCs[RTLIB::OGT_F128] = ISD::SETGT; 786 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT; 787 CCs[RTLIB::UO_F32] = ISD::SETNE; 788 CCs[RTLIB::UO_F64] = ISD::SETNE; 789 CCs[RTLIB::UO_F128] = ISD::SETNE; 790 CCs[RTLIB::UO_PPCF128] = ISD::SETNE; 791 CCs[RTLIB::O_F32] = ISD::SETEQ; 792 CCs[RTLIB::O_F64] = ISD::SETEQ; 793 CCs[RTLIB::O_F128] = ISD::SETEQ; 794 CCs[RTLIB::O_PPCF128] = ISD::SETEQ; 795 } 796 797 /// NOTE: The TargetMachine owns TLOF. 798 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) { 799 initActions(); 800 801 // Perform these initializations only once. 802 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8; 803 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize 804 = MaxStoresPerMemmoveOptSize = 4; 805 UseUnderscoreSetJmp = false; 806 UseUnderscoreLongJmp = false; 807 SelectIsExpensive = false; 808 HasMultipleConditionRegisters = false; 809 HasExtractBitsInsn = false; 810 FsqrtIsCheap = false; 811 JumpIsExpensive = JumpIsExpensiveOverride; 812 PredictableSelectIsExpensive = false; 813 MaskAndBranchFoldingIsLegal = false; 814 EnableExtLdPromotion = false; 815 HasFloatingPointExceptions = true; 816 StackPointerRegisterToSaveRestore = 0; 817 BooleanContents = UndefinedBooleanContent; 818 BooleanFloatContents = UndefinedBooleanContent; 819 BooleanVectorContents = UndefinedBooleanContent; 820 SchedPreferenceInfo = Sched::ILP; 821 JumpBufSize = 0; 822 JumpBufAlignment = 0; 823 MinFunctionAlignment = 0; 824 PrefFunctionAlignment = 0; 825 PrefLoopAlignment = 0; 826 GatherAllAliasesMaxDepth = 6; 827 MinStackArgumentAlignment = 1; 828 MinimumJumpTableEntries = 4; 829 // TODO: the default will be switched to 0 in the next commit, along 830 // with the Target-specific changes necessary. 831 MaxAtomicSizeInBitsSupported = 1024; 832 833 MinCmpXchgSizeInBits = 0; 834 835 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr); 836 837 InitLibcallNames(LibcallRoutineNames, TM.getTargetTriple()); 838 InitCmpLibcallCCs(CmpLibcallCCs); 839 InitLibcallCallingConvs(LibcallCallingConvs); 840 } 841 842 void TargetLoweringBase::initActions() { 843 // All operations default to being supported. 844 memset(OpActions, 0, sizeof(OpActions)); 845 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 846 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 847 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 848 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 849 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr); 850 std::fill(std::begin(TargetDAGCombineArray), 851 std::end(TargetDAGCombineArray), 0); 852 853 // Set default actions for various operations. 854 for (MVT VT : MVT::all_valuetypes()) { 855 // Default all indexed load / store to expand. 856 for (unsigned IM = (unsigned)ISD::PRE_INC; 857 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 858 setIndexedLoadAction(IM, VT, Expand); 859 setIndexedStoreAction(IM, VT, Expand); 860 } 861 862 // Most backends expect to see the node which just returns the value loaded. 863 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); 864 865 // These operations default to expand. 866 setOperationAction(ISD::FGETSIGN, VT, Expand); 867 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); 868 setOperationAction(ISD::FMINNUM, VT, Expand); 869 setOperationAction(ISD::FMAXNUM, VT, Expand); 870 setOperationAction(ISD::FMINNAN, VT, Expand); 871 setOperationAction(ISD::FMAXNAN, VT, Expand); 872 setOperationAction(ISD::FMAD, VT, Expand); 873 setOperationAction(ISD::SMIN, VT, Expand); 874 setOperationAction(ISD::SMAX, VT, Expand); 875 setOperationAction(ISD::UMIN, VT, Expand); 876 setOperationAction(ISD::UMAX, VT, Expand); 877 878 // Overflow operations default to expand 879 setOperationAction(ISD::SADDO, VT, Expand); 880 setOperationAction(ISD::SSUBO, VT, Expand); 881 setOperationAction(ISD::UADDO, VT, Expand); 882 setOperationAction(ISD::USUBO, VT, Expand); 883 setOperationAction(ISD::SMULO, VT, Expand); 884 setOperationAction(ISD::UMULO, VT, Expand); 885 886 // These default to Expand so they will be expanded to CTLZ/CTTZ by default. 887 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); 888 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); 889 890 setOperationAction(ISD::BITREVERSE, VT, Expand); 891 892 // These library functions default to expand. 893 setOperationAction(ISD::FROUND, VT, Expand); 894 895 // These operations default to expand for vector types. 896 if (VT.isVector()) { 897 setOperationAction(ISD::FCOPYSIGN, VT, Expand); 898 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand); 899 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); 900 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); 901 } 902 903 // For most targets @llvm.get.dynamic.area.offset just returns 0. 904 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand); 905 } 906 907 // Most targets ignore the @llvm.prefetch intrinsic. 908 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 909 910 // Most targets also ignore the @llvm.readcyclecounter intrinsic. 911 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand); 912 913 // ConstantFP nodes default to expand. Targets can either change this to 914 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 915 // to optimize expansions for certain constants. 916 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 917 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 918 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 919 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 920 setOperationAction(ISD::ConstantFP, MVT::f128, Expand); 921 922 // These library functions default to expand. 923 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) { 924 setOperationAction(ISD::FLOG , VT, Expand); 925 setOperationAction(ISD::FLOG2, VT, Expand); 926 setOperationAction(ISD::FLOG10, VT, Expand); 927 setOperationAction(ISD::FEXP , VT, Expand); 928 setOperationAction(ISD::FEXP2, VT, Expand); 929 setOperationAction(ISD::FFLOOR, VT, Expand); 930 setOperationAction(ISD::FNEARBYINT, VT, Expand); 931 setOperationAction(ISD::FCEIL, VT, Expand); 932 setOperationAction(ISD::FRINT, VT, Expand); 933 setOperationAction(ISD::FTRUNC, VT, Expand); 934 setOperationAction(ISD::FROUND, VT, Expand); 935 } 936 937 // Default ISD::TRAP to expand (which turns it into abort). 938 setOperationAction(ISD::TRAP, MVT::Other, Expand); 939 940 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 941 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 942 // 943 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 944 } 945 946 MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL, 947 EVT) const { 948 return MVT::getIntegerVT(8 * DL.getPointerSize(0)); 949 } 950 951 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy, 952 const DataLayout &DL) const { 953 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 954 if (LHSTy.isVector()) 955 return LHSTy; 956 return getScalarShiftAmountTy(DL, LHSTy); 957 } 958 959 /// canOpTrap - Returns true if the operation can trap for the value type. 960 /// VT must be a legal type. 961 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 962 assert(isTypeLegal(VT)); 963 switch (Op) { 964 default: 965 return false; 966 case ISD::FDIV: 967 case ISD::FREM: 968 case ISD::SDIV: 969 case ISD::UDIV: 970 case ISD::SREM: 971 case ISD::UREM: 972 return true; 973 } 974 } 975 976 void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) { 977 // If the command-line option was specified, ignore this request. 978 if (!JumpIsExpensiveOverride.getNumOccurrences()) 979 JumpIsExpensive = isExpensive; 980 } 981 982 TargetLoweringBase::LegalizeKind 983 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const { 984 // If this is a simple type, use the ComputeRegisterProp mechanism. 985 if (VT.isSimple()) { 986 MVT SVT = VT.getSimpleVT(); 987 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); 988 MVT NVT = TransformToType[SVT.SimpleTy]; 989 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); 990 991 assert((LA == TypeLegal || LA == TypeSoftenFloat || 992 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) && 993 "Promote may not follow Expand or Promote"); 994 995 if (LA == TypeSplitVector) 996 return LegalizeKind(LA, 997 EVT::getVectorVT(Context, SVT.getVectorElementType(), 998 SVT.getVectorNumElements() / 2)); 999 if (LA == TypeScalarizeVector) 1000 return LegalizeKind(LA, SVT.getVectorElementType()); 1001 return LegalizeKind(LA, NVT); 1002 } 1003 1004 // Handle Extended Scalar Types. 1005 if (!VT.isVector()) { 1006 assert(VT.isInteger() && "Float types must be simple"); 1007 unsigned BitSize = VT.getSizeInBits(); 1008 // First promote to a power-of-two size, then expand if necessary. 1009 if (BitSize < 8 || !isPowerOf2_32(BitSize)) { 1010 EVT NVT = VT.getRoundIntegerType(Context); 1011 assert(NVT != VT && "Unable to round integer VT"); 1012 LegalizeKind NextStep = getTypeConversion(Context, NVT); 1013 // Avoid multi-step promotion. 1014 if (NextStep.first == TypePromoteInteger) 1015 return NextStep; 1016 // Return rounded integer type. 1017 return LegalizeKind(TypePromoteInteger, NVT); 1018 } 1019 1020 return LegalizeKind(TypeExpandInteger, 1021 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2)); 1022 } 1023 1024 // Handle vector types. 1025 unsigned NumElts = VT.getVectorNumElements(); 1026 EVT EltVT = VT.getVectorElementType(); 1027 1028 // Vectors with only one element are always scalarized. 1029 if (NumElts == 1) 1030 return LegalizeKind(TypeScalarizeVector, EltVT); 1031 1032 // Try to widen vector elements until the element type is a power of two and 1033 // promote it to a legal type later on, for example: 1034 // <3 x i8> -> <4 x i8> -> <4 x i32> 1035 if (EltVT.isInteger()) { 1036 // Vectors with a number of elements that is not a power of two are always 1037 // widened, for example <3 x i8> -> <4 x i8>. 1038 if (!VT.isPow2VectorType()) { 1039 NumElts = (unsigned)NextPowerOf2(NumElts); 1040 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); 1041 return LegalizeKind(TypeWidenVector, NVT); 1042 } 1043 1044 // Examine the element type. 1045 LegalizeKind LK = getTypeConversion(Context, EltVT); 1046 1047 // If type is to be expanded, split the vector. 1048 // <4 x i140> -> <2 x i140> 1049 if (LK.first == TypeExpandInteger) 1050 return LegalizeKind(TypeSplitVector, 1051 EVT::getVectorVT(Context, EltVT, NumElts / 2)); 1052 1053 // Promote the integer element types until a legal vector type is found 1054 // or until the element integer type is too big. If a legal type was not 1055 // found, fallback to the usual mechanism of widening/splitting the 1056 // vector. 1057 EVT OldEltVT = EltVT; 1058 while (1) { 1059 // Increase the bitwidth of the element to the next pow-of-two 1060 // (which is greater than 8 bits). 1061 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()) 1062 .getRoundIntegerType(Context); 1063 1064 // Stop trying when getting a non-simple element type. 1065 // Note that vector elements may be greater than legal vector element 1066 // types. Example: X86 XMM registers hold 64bit element on 32bit 1067 // systems. 1068 if (!EltVT.isSimple()) 1069 break; 1070 1071 // Build a new vector type and check if it is legal. 1072 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1073 // Found a legal promoted vector type. 1074 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) 1075 return LegalizeKind(TypePromoteInteger, 1076 EVT::getVectorVT(Context, EltVT, NumElts)); 1077 } 1078 1079 // Reset the type to the unexpanded type if we did not find a legal vector 1080 // type with a promoted vector element type. 1081 EltVT = OldEltVT; 1082 } 1083 1084 // Try to widen the vector until a legal type is found. 1085 // If there is no wider legal type, split the vector. 1086 while (1) { 1087 // Round up to the next power of 2. 1088 NumElts = (unsigned)NextPowerOf2(NumElts); 1089 1090 // If there is no simple vector type with this many elements then there 1091 // cannot be a larger legal vector type. Note that this assumes that 1092 // there are no skipped intermediate vector types in the simple types. 1093 if (!EltVT.isSimple()) 1094 break; 1095 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1096 if (LargerVector == MVT()) 1097 break; 1098 1099 // If this type is legal then widen the vector. 1100 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) 1101 return LegalizeKind(TypeWidenVector, LargerVector); 1102 } 1103 1104 // Widen odd vectors to next power of two. 1105 if (!VT.isPow2VectorType()) { 1106 EVT NVT = VT.getPow2VectorType(Context); 1107 return LegalizeKind(TypeWidenVector, NVT); 1108 } 1109 1110 // Vectors with illegal element types are expanded. 1111 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); 1112 return LegalizeKind(TypeSplitVector, NVT); 1113 } 1114 1115 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 1116 unsigned &NumIntermediates, 1117 MVT &RegisterVT, 1118 TargetLoweringBase *TLI) { 1119 // Figure out the right, legal destination reg to copy into. 1120 unsigned NumElts = VT.getVectorNumElements(); 1121 MVT EltTy = VT.getVectorElementType(); 1122 1123 unsigned NumVectorRegs = 1; 1124 1125 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1126 // could break down into LHS/RHS like LegalizeDAG does. 1127 if (!isPowerOf2_32(NumElts)) { 1128 NumVectorRegs = NumElts; 1129 NumElts = 1; 1130 } 1131 1132 // Divide the input until we get to a supported size. This will always 1133 // end with a scalar if the target doesn't support vectors. 1134 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 1135 NumElts >>= 1; 1136 NumVectorRegs <<= 1; 1137 } 1138 1139 NumIntermediates = NumVectorRegs; 1140 1141 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 1142 if (!TLI->isTypeLegal(NewVT)) 1143 NewVT = EltTy; 1144 IntermediateVT = NewVT; 1145 1146 unsigned NewVTSize = NewVT.getSizeInBits(); 1147 1148 // Convert sizes such as i33 to i64. 1149 if (!isPowerOf2_32(NewVTSize)) 1150 NewVTSize = NextPowerOf2(NewVTSize); 1151 1152 MVT DestVT = TLI->getRegisterType(NewVT); 1153 RegisterVT = DestVT; 1154 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1155 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1156 1157 // Otherwise, promotion or legal types use the same number of registers as 1158 // the vector decimated to the appropriate level. 1159 return NumVectorRegs; 1160 } 1161 1162 /// isLegalRC - Return true if the value types that can be represented by the 1163 /// specified register class are all legal. 1164 bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const { 1165 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 1166 I != E; ++I) { 1167 if (isTypeLegal(*I)) 1168 return true; 1169 } 1170 return false; 1171 } 1172 1173 /// Replace/modify any TargetFrameIndex operands with a targte-dependent 1174 /// sequence of memory operands that is recognized by PrologEpilogInserter. 1175 MachineBasicBlock * 1176 TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI, 1177 MachineBasicBlock *MBB) const { 1178 MachineInstr *MI = &InitialMI; 1179 MachineFunction &MF = *MI->getParent()->getParent(); 1180 MachineFrameInfo &MFI = *MF.getFrameInfo(); 1181 1182 // We're handling multiple types of operands here: 1183 // PATCHPOINT MetaArgs - live-in, read only, direct 1184 // STATEPOINT Deopt Spill - live-through, read only, indirect 1185 // STATEPOINT Deopt Alloca - live-through, read only, direct 1186 // (We're currently conservative and mark the deopt slots read/write in 1187 // practice.) 1188 // STATEPOINT GC Spill - live-through, read/write, indirect 1189 // STATEPOINT GC Alloca - live-through, read/write, direct 1190 // The live-in vs live-through is handled already (the live through ones are 1191 // all stack slots), but we need to handle the different type of stackmap 1192 // operands and memory effects here. 1193 1194 // MI changes inside this loop as we grow operands. 1195 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) { 1196 MachineOperand &MO = MI->getOperand(OperIdx); 1197 if (!MO.isFI()) 1198 continue; 1199 1200 // foldMemoryOperand builds a new MI after replacing a single FI operand 1201 // with the canonical set of five x86 addressing-mode operands. 1202 int FI = MO.getIndex(); 1203 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc()); 1204 1205 // Copy operands before the frame-index. 1206 for (unsigned i = 0; i < OperIdx; ++i) 1207 MIB.addOperand(MI->getOperand(i)); 1208 // Add frame index operands recognized by stackmaps.cpp 1209 if (MFI.isStatepointSpillSlotObjectIndex(FI)) { 1210 // indirect-mem-ref tag, size, #FI, offset. 1211 // Used for spills inserted by StatepointLowering. This codepath is not 1212 // used for patchpoints/stackmaps at all, for these spilling is done via 1213 // foldMemoryOperand callback only. 1214 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity"); 1215 MIB.addImm(StackMaps::IndirectMemRefOp); 1216 MIB.addImm(MFI.getObjectSize(FI)); 1217 MIB.addOperand(MI->getOperand(OperIdx)); 1218 MIB.addImm(0); 1219 } else { 1220 // direct-mem-ref tag, #FI, offset. 1221 // Used by patchpoint, and direct alloca arguments to statepoints 1222 MIB.addImm(StackMaps::DirectMemRefOp); 1223 MIB.addOperand(MI->getOperand(OperIdx)); 1224 MIB.addImm(0); 1225 } 1226 // Copy the operands after the frame index. 1227 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i) 1228 MIB.addOperand(MI->getOperand(i)); 1229 1230 // Inherit previous memory operands. 1231 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 1232 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!"); 1233 1234 // Add a new memory operand for this FI. 1235 assert(MFI.getObjectOffset(FI) != -1); 1236 1237 unsigned Flags = MachineMemOperand::MOLoad; 1238 if (MI->getOpcode() == TargetOpcode::STATEPOINT) { 1239 Flags |= MachineMemOperand::MOStore; 1240 Flags |= MachineMemOperand::MOVolatile; 1241 } 1242 MachineMemOperand *MMO = MF.getMachineMemOperand( 1243 MachinePointerInfo::getFixedStack(MF, FI), Flags, 1244 MF.getDataLayout().getPointerSize(), MFI.getObjectAlignment(FI)); 1245 MIB->addMemOperand(MF, MMO); 1246 1247 // Replace the instruction and update the operand index. 1248 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1249 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1; 1250 MI->eraseFromParent(); 1251 MI = MIB; 1252 } 1253 return MBB; 1254 } 1255 1256 /// findRepresentativeClass - Return the largest legal super-reg register class 1257 /// of the register class for the specified type and its associated "cost". 1258 // This function is in TargetLowering because it uses RegClassForVT which would 1259 // need to be moved to TargetRegisterInfo and would necessitate moving 1260 // isTypeLegal over as well - a massive change that would just require 1261 // TargetLowering having a TargetRegisterInfo class member that it would use. 1262 std::pair<const TargetRegisterClass *, uint8_t> 1263 TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI, 1264 MVT VT) const { 1265 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 1266 if (!RC) 1267 return std::make_pair(RC, 0); 1268 1269 // Compute the set of all super-register classes. 1270 BitVector SuperRegRC(TRI->getNumRegClasses()); 1271 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 1272 SuperRegRC.setBitsInMask(RCI.getMask()); 1273 1274 // Find the first legal register class with the largest spill size. 1275 const TargetRegisterClass *BestRC = RC; 1276 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) { 1277 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 1278 // We want the largest possible spill size. 1279 if (SuperRC->getSize() <= BestRC->getSize()) 1280 continue; 1281 if (!isLegalRC(SuperRC)) 1282 continue; 1283 BestRC = SuperRC; 1284 } 1285 return std::make_pair(BestRC, 1); 1286 } 1287 1288 /// computeRegisterProperties - Once all of the register classes are added, 1289 /// this allows us to compute derived properties we expose. 1290 void TargetLoweringBase::computeRegisterProperties( 1291 const TargetRegisterInfo *TRI) { 1292 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE, 1293 "Too many value types for ValueTypeActions to hold!"); 1294 1295 // Everything defaults to needing one register. 1296 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1297 NumRegistersForVT[i] = 1; 1298 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 1299 } 1300 // ...except isVoid, which doesn't need any registers. 1301 NumRegistersForVT[MVT::isVoid] = 0; 1302 1303 // Find the largest integer register class. 1304 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 1305 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg) 1306 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 1307 1308 // Every integer value type larger than this largest register takes twice as 1309 // many registers to represent as the previous ValueType. 1310 for (unsigned ExpandedReg = LargestIntReg + 1; 1311 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 1312 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 1313 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 1314 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 1315 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 1316 TypeExpandInteger); 1317 } 1318 1319 // Inspect all of the ValueType's smaller than the largest integer 1320 // register to see which ones need promotion. 1321 unsigned LegalIntReg = LargestIntReg; 1322 for (unsigned IntReg = LargestIntReg - 1; 1323 IntReg >= (unsigned)MVT::i1; --IntReg) { 1324 MVT IVT = (MVT::SimpleValueType)IntReg; 1325 if (isTypeLegal(IVT)) { 1326 LegalIntReg = IntReg; 1327 } else { 1328 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 1329 (const MVT::SimpleValueType)LegalIntReg; 1330 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 1331 } 1332 } 1333 1334 // ppcf128 type is really two f64's. 1335 if (!isTypeLegal(MVT::ppcf128)) { 1336 if (isTypeLegal(MVT::f64)) { 1337 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 1338 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 1339 TransformToType[MVT::ppcf128] = MVT::f64; 1340 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 1341 } else { 1342 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128]; 1343 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128]; 1344 TransformToType[MVT::ppcf128] = MVT::i128; 1345 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat); 1346 } 1347 } 1348 1349 // Decide how to handle f128. If the target does not have native f128 support, 1350 // expand it to i128 and we will be generating soft float library calls. 1351 if (!isTypeLegal(MVT::f128)) { 1352 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128]; 1353 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128]; 1354 TransformToType[MVT::f128] = MVT::i128; 1355 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); 1356 } 1357 1358 // Decide how to handle f64. If the target does not have native f64 support, 1359 // expand it to i64 and we will be generating soft float library calls. 1360 if (!isTypeLegal(MVT::f64)) { 1361 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 1362 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 1363 TransformToType[MVT::f64] = MVT::i64; 1364 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 1365 } 1366 1367 // Decide how to handle f32. If the target does not have native f32 support, 1368 // expand it to i32 and we will be generating soft float library calls. 1369 if (!isTypeLegal(MVT::f32)) { 1370 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 1371 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 1372 TransformToType[MVT::f32] = MVT::i32; 1373 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 1374 } 1375 1376 // Decide how to handle f16. If the target does not have native f16 support, 1377 // promote it to f32, because there are no f16 library calls (except for 1378 // conversions). 1379 if (!isTypeLegal(MVT::f16)) { 1380 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32]; 1381 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32]; 1382 TransformToType[MVT::f16] = MVT::f32; 1383 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat); 1384 } 1385 1386 // Loop over all of the vector value types to see which need transformations. 1387 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 1388 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1389 MVT VT = (MVT::SimpleValueType) i; 1390 if (isTypeLegal(VT)) 1391 continue; 1392 1393 MVT EltVT = VT.getVectorElementType(); 1394 unsigned NElts = VT.getVectorNumElements(); 1395 bool IsLegalWiderType = false; 1396 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); 1397 switch (PreferredAction) { 1398 case TypePromoteInteger: { 1399 // Try to promote the elements of integer vectors. If no legal 1400 // promotion was found, fall through to the widen-vector method. 1401 for (unsigned nVT = i + 1; nVT <= MVT::LAST_INTEGER_VECTOR_VALUETYPE; ++nVT) { 1402 MVT SVT = (MVT::SimpleValueType) nVT; 1403 // Promote vectors of integers to vectors with the same number 1404 // of elements, with a wider element type. 1405 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() && 1406 SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)) { 1407 TransformToType[i] = SVT; 1408 RegisterTypeForVT[i] = SVT; 1409 NumRegistersForVT[i] = 1; 1410 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 1411 IsLegalWiderType = true; 1412 break; 1413 } 1414 } 1415 if (IsLegalWiderType) 1416 break; 1417 } 1418 case TypeWidenVector: { 1419 // Try to widen the vector. 1420 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1421 MVT SVT = (MVT::SimpleValueType) nVT; 1422 if (SVT.getVectorElementType() == EltVT 1423 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) { 1424 TransformToType[i] = SVT; 1425 RegisterTypeForVT[i] = SVT; 1426 NumRegistersForVT[i] = 1; 1427 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1428 IsLegalWiderType = true; 1429 break; 1430 } 1431 } 1432 if (IsLegalWiderType) 1433 break; 1434 } 1435 case TypeSplitVector: 1436 case TypeScalarizeVector: { 1437 MVT IntermediateVT; 1438 MVT RegisterVT; 1439 unsigned NumIntermediates; 1440 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT, 1441 NumIntermediates, RegisterVT, this); 1442 RegisterTypeForVT[i] = RegisterVT; 1443 1444 MVT NVT = VT.getPow2VectorType(); 1445 if (NVT == VT) { 1446 // Type is already a power of 2. The default action is to split. 1447 TransformToType[i] = MVT::Other; 1448 if (PreferredAction == TypeScalarizeVector) 1449 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); 1450 else if (PreferredAction == TypeSplitVector) 1451 ValueTypeActions.setTypeAction(VT, TypeSplitVector); 1452 else 1453 // Set type action according to the number of elements. 1454 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector 1455 : TypeSplitVector); 1456 } else { 1457 TransformToType[i] = NVT; 1458 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1459 } 1460 break; 1461 } 1462 default: 1463 llvm_unreachable("Unknown vector legalization action!"); 1464 } 1465 } 1466 1467 // Determine the 'representative' register class for each value type. 1468 // An representative register class is the largest (meaning one which is 1469 // not a sub-register class / subreg register class) legal register class for 1470 // a group of value types. For example, on i386, i8, i16, and i32 1471 // representative would be GR32; while on x86_64 it's GR64. 1472 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1473 const TargetRegisterClass* RRC; 1474 uint8_t Cost; 1475 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i); 1476 RepRegClassForVT[i] = RRC; 1477 RepRegClassCostForVT[i] = Cost; 1478 } 1479 } 1480 1481 EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &, 1482 EVT VT) const { 1483 assert(!VT.isVector() && "No default SetCC type for vectors!"); 1484 return getPointerTy(DL).SimpleTy; 1485 } 1486 1487 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const { 1488 return MVT::i32; // return the default value 1489 } 1490 1491 /// getVectorTypeBreakdown - Vector types are broken down into some number of 1492 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 1493 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 1494 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 1495 /// 1496 /// This method returns the number of registers needed, and the VT for each 1497 /// register. It also returns the VT and quantity of the intermediate values 1498 /// before they are promoted/expanded. 1499 /// 1500 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 1501 EVT &IntermediateVT, 1502 unsigned &NumIntermediates, 1503 MVT &RegisterVT) const { 1504 unsigned NumElts = VT.getVectorNumElements(); 1505 1506 // If there is a wider vector type with the same element type as this one, 1507 // or a promoted vector type that has the same number of elements which 1508 // are wider, then we should convert to that legal vector type. 1509 // This handles things like <2 x float> -> <4 x float> and 1510 // <4 x i1> -> <4 x i32>. 1511 LegalizeTypeAction TA = getTypeAction(Context, VT); 1512 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { 1513 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 1514 if (isTypeLegal(RegisterEVT)) { 1515 IntermediateVT = RegisterEVT; 1516 RegisterVT = RegisterEVT.getSimpleVT(); 1517 NumIntermediates = 1; 1518 return 1; 1519 } 1520 } 1521 1522 // Figure out the right, legal destination reg to copy into. 1523 EVT EltTy = VT.getVectorElementType(); 1524 1525 unsigned NumVectorRegs = 1; 1526 1527 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1528 // could break down into LHS/RHS like LegalizeDAG does. 1529 if (!isPowerOf2_32(NumElts)) { 1530 NumVectorRegs = NumElts; 1531 NumElts = 1; 1532 } 1533 1534 // Divide the input until we get to a supported size. This will always 1535 // end with a scalar if the target doesn't support vectors. 1536 while (NumElts > 1 && !isTypeLegal( 1537 EVT::getVectorVT(Context, EltTy, NumElts))) { 1538 NumElts >>= 1; 1539 NumVectorRegs <<= 1; 1540 } 1541 1542 NumIntermediates = NumVectorRegs; 1543 1544 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 1545 if (!isTypeLegal(NewVT)) 1546 NewVT = EltTy; 1547 IntermediateVT = NewVT; 1548 1549 MVT DestVT = getRegisterType(Context, NewVT); 1550 RegisterVT = DestVT; 1551 unsigned NewVTSize = NewVT.getSizeInBits(); 1552 1553 // Convert sizes such as i33 to i64. 1554 if (!isPowerOf2_32(NewVTSize)) 1555 NewVTSize = NextPowerOf2(NewVTSize); 1556 1557 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1558 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1559 1560 // Otherwise, promotion or legal types use the same number of registers as 1561 // the vector decimated to the appropriate level. 1562 return NumVectorRegs; 1563 } 1564 1565 /// Get the EVTs and ArgFlags collections that represent the legalized return 1566 /// type of the given function. This does not require a DAG or a return value, 1567 /// and is suitable for use before any DAGs for the function are constructed. 1568 /// TODO: Move this out of TargetLowering.cpp. 1569 void llvm::GetReturnInfo(Type *ReturnType, AttributeSet attr, 1570 SmallVectorImpl<ISD::OutputArg> &Outs, 1571 const TargetLowering &TLI, const DataLayout &DL) { 1572 SmallVector<EVT, 4> ValueVTs; 1573 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs); 1574 unsigned NumValues = ValueVTs.size(); 1575 if (NumValues == 0) return; 1576 1577 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1578 EVT VT = ValueVTs[j]; 1579 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1580 1581 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1582 ExtendKind = ISD::SIGN_EXTEND; 1583 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1584 ExtendKind = ISD::ZERO_EXTEND; 1585 1586 // FIXME: C calling convention requires the return type to be promoted to 1587 // at least 32-bit. But this is not necessary for non-C calling 1588 // conventions. The frontend should mark functions whose return values 1589 // require promoting with signext or zeroext attributes. 1590 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1591 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1592 if (VT.bitsLT(MinVT)) 1593 VT = MinVT; 1594 } 1595 1596 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1597 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1598 1599 // 'inreg' on function refers to return value 1600 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1601 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg)) 1602 Flags.setInReg(); 1603 1604 // Propagate extension type if any 1605 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1606 Flags.setSExt(); 1607 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1608 Flags.setZExt(); 1609 1610 for (unsigned i = 0; i < NumParts; ++i) 1611 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0)); 1612 } 1613 } 1614 1615 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1616 /// function arguments in the caller parameter area. This is the actual 1617 /// alignment, not its logarithm. 1618 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty, 1619 const DataLayout &DL) const { 1620 return DL.getABITypeAlignment(Ty); 1621 } 1622 1623 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context, 1624 const DataLayout &DL, EVT VT, 1625 unsigned AddrSpace, 1626 unsigned Alignment, 1627 bool *Fast) const { 1628 // Check if the specified alignment is sufficient based on the data layout. 1629 // TODO: While using the data layout works in practice, a better solution 1630 // would be to implement this check directly (make this a virtual function). 1631 // For example, the ABI alignment may change based on software platform while 1632 // this function should only be affected by hardware implementation. 1633 Type *Ty = VT.getTypeForEVT(Context); 1634 if (Alignment >= DL.getABITypeAlignment(Ty)) { 1635 // Assume that an access that meets the ABI-specified alignment is fast. 1636 if (Fast != nullptr) 1637 *Fast = true; 1638 return true; 1639 } 1640 1641 // This is a misaligned access. 1642 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Fast); 1643 } 1644 1645 BranchProbability TargetLoweringBase::getPredictableBranchThreshold() const { 1646 return BranchProbability(MinPercentageForPredictableBranch, 100); 1647 } 1648 1649 //===----------------------------------------------------------------------===// 1650 // TargetTransformInfo Helpers 1651 //===----------------------------------------------------------------------===// 1652 1653 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const { 1654 enum InstructionOpcodes { 1655 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1656 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1657 #include "llvm/IR/Instruction.def" 1658 }; 1659 switch (static_cast<InstructionOpcodes>(Opcode)) { 1660 case Ret: return 0; 1661 case Br: return 0; 1662 case Switch: return 0; 1663 case IndirectBr: return 0; 1664 case Invoke: return 0; 1665 case Resume: return 0; 1666 case Unreachable: return 0; 1667 case CleanupRet: return 0; 1668 case CatchRet: return 0; 1669 case CatchPad: return 0; 1670 case CatchSwitch: return 0; 1671 case CleanupPad: return 0; 1672 case Add: return ISD::ADD; 1673 case FAdd: return ISD::FADD; 1674 case Sub: return ISD::SUB; 1675 case FSub: return ISD::FSUB; 1676 case Mul: return ISD::MUL; 1677 case FMul: return ISD::FMUL; 1678 case UDiv: return ISD::UDIV; 1679 case SDiv: return ISD::SDIV; 1680 case FDiv: return ISD::FDIV; 1681 case URem: return ISD::UREM; 1682 case SRem: return ISD::SREM; 1683 case FRem: return ISD::FREM; 1684 case Shl: return ISD::SHL; 1685 case LShr: return ISD::SRL; 1686 case AShr: return ISD::SRA; 1687 case And: return ISD::AND; 1688 case Or: return ISD::OR; 1689 case Xor: return ISD::XOR; 1690 case Alloca: return 0; 1691 case Load: return ISD::LOAD; 1692 case Store: return ISD::STORE; 1693 case GetElementPtr: return 0; 1694 case Fence: return 0; 1695 case AtomicCmpXchg: return 0; 1696 case AtomicRMW: return 0; 1697 case Trunc: return ISD::TRUNCATE; 1698 case ZExt: return ISD::ZERO_EXTEND; 1699 case SExt: return ISD::SIGN_EXTEND; 1700 case FPToUI: return ISD::FP_TO_UINT; 1701 case FPToSI: return ISD::FP_TO_SINT; 1702 case UIToFP: return ISD::UINT_TO_FP; 1703 case SIToFP: return ISD::SINT_TO_FP; 1704 case FPTrunc: return ISD::FP_ROUND; 1705 case FPExt: return ISD::FP_EXTEND; 1706 case PtrToInt: return ISD::BITCAST; 1707 case IntToPtr: return ISD::BITCAST; 1708 case BitCast: return ISD::BITCAST; 1709 case AddrSpaceCast: return ISD::ADDRSPACECAST; 1710 case ICmp: return ISD::SETCC; 1711 case FCmp: return ISD::SETCC; 1712 case PHI: return 0; 1713 case Call: return 0; 1714 case Select: return ISD::SELECT; 1715 case UserOp1: return 0; 1716 case UserOp2: return 0; 1717 case VAArg: return 0; 1718 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1719 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1720 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1721 case ExtractValue: return ISD::MERGE_VALUES; 1722 case InsertValue: return ISD::MERGE_VALUES; 1723 case LandingPad: return 0; 1724 } 1725 1726 llvm_unreachable("Unknown instruction type encountered!"); 1727 } 1728 1729 std::pair<int, MVT> 1730 TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL, 1731 Type *Ty) const { 1732 LLVMContext &C = Ty->getContext(); 1733 EVT MTy = getValueType(DL, Ty); 1734 1735 int Cost = 1; 1736 // We keep legalizing the type until we find a legal kind. We assume that 1737 // the only operation that costs anything is the split. After splitting 1738 // we need to handle two types. 1739 while (true) { 1740 LegalizeKind LK = getTypeConversion(C, MTy); 1741 1742 if (LK.first == TypeLegal) 1743 return std::make_pair(Cost, MTy.getSimpleVT()); 1744 1745 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) 1746 Cost *= 2; 1747 1748 // Do not loop with f128 type. 1749 if (MTy == LK.second) 1750 return std::make_pair(Cost, MTy.getSimpleVT()); 1751 1752 // Keep legalizing the type. 1753 MTy = LK.second; 1754 } 1755 } 1756 1757 Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const { 1758 if (!TM.getTargetTriple().isAndroid()) 1759 return nullptr; 1760 1761 // Android provides a libc function to retrieve the address of the current 1762 // thread's unsafe stack pointer. 1763 Module *M = IRB.GetInsertBlock()->getParent()->getParent(); 1764 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext()); 1765 Value *Fn = M->getOrInsertFunction("__safestack_pointer_address", 1766 StackPtrTy->getPointerTo(0), nullptr); 1767 return IRB.CreateCall(Fn); 1768 } 1769 1770 //===----------------------------------------------------------------------===// 1771 // Loop Strength Reduction hooks 1772 //===----------------------------------------------------------------------===// 1773 1774 /// isLegalAddressingMode - Return true if the addressing mode represented 1775 /// by AM is legal for this target, for a load/store of the specified type. 1776 bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL, 1777 const AddrMode &AM, Type *Ty, 1778 unsigned AS) const { 1779 // The default implementation of this implements a conservative RISCy, r+r and 1780 // r+i addr mode. 1781 1782 // Allows a sign-extended 16-bit immediate field. 1783 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1784 return false; 1785 1786 // No global is ever allowed as a base. 1787 if (AM.BaseGV) 1788 return false; 1789 1790 // Only support r+r, 1791 switch (AM.Scale) { 1792 case 0: // "r+i" or just "i", depending on HasBaseReg. 1793 break; 1794 case 1: 1795 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1796 return false; 1797 // Otherwise we have r+r or r+i. 1798 break; 1799 case 2: 1800 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1801 return false; 1802 // Allow 2*r as r+r. 1803 break; 1804 default: // Don't allow n * r 1805 return false; 1806 } 1807 1808 return true; 1809 } 1810 1811 //===----------------------------------------------------------------------===// 1812 // Stack Protector 1813 //===----------------------------------------------------------------------===// 1814 1815 // For OpenBSD return its special guard variable. Otherwise return nullptr, 1816 // so that SelectionDAG handle SSP. 1817 Value *TargetLoweringBase::getIRStackGuard(IRBuilder<> &IRB) const { 1818 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) { 1819 Module &M = *IRB.GetInsertBlock()->getParent()->getParent(); 1820 PointerType *PtrTy = Type::getInt8PtrTy(M.getContext()); 1821 auto Guard = cast<GlobalValue>(M.getOrInsertGlobal("__guard_local", PtrTy)); 1822 Guard->setVisibility(GlobalValue::HiddenVisibility); 1823 return Guard; 1824 } 1825 return nullptr; 1826 } 1827 1828 // Currently only support "standard" __stack_chk_guard. 1829 // TODO: add LOAD_STACK_GUARD support. 1830 void TargetLoweringBase::insertSSPDeclarations(Module &M) const { 1831 M.getOrInsertGlobal("__stack_chk_guard", Type::getInt8PtrTy(M.getContext())); 1832 } 1833 1834 // Currently only support "standard" __stack_chk_guard. 1835 // TODO: add LOAD_STACK_GUARD support. 1836 Value *TargetLoweringBase::getSDagStackGuard(const Module &M) const { 1837 return M.getGlobalVariable("__stack_chk_guard", true); 1838 } 1839 1840 Value *TargetLoweringBase::getSSPStackGuardCheck(const Module &M) const { 1841 return nullptr; 1842 } 1843
