/prebuilts/go/darwin-x86/src/runtime/ |
vlop_arm.s | 100 #define Rs R2 // three temporary variables 110 CLZ Rq, Rs // find normalizing shift 111 MOVW.S Rq<<Rs, Ra 116 SUB.S $7, Rs 118 MOVW.PL Ra<<Rs, Rq 128 MOVW.NE $0, Rs 129 MULAL.NE Rq, Ra, (Rq,Rs) 133 MULLU Rq, Rr, (Rq,Rs) // q = (r * q) >> 32 147 DIVUHW Rq, Rr, Rs 148 MUL Rs, Rq, R [all...] |
/prebuilts/go/linux-x86/src/runtime/ |
vlop_arm.s | 100 #define Rs R2 // three temporary variables 110 CLZ Rq, Rs // find normalizing shift 111 MOVW.S Rq<<Rs, Ra 116 SUB.S $7, Rs 118 MOVW.PL Ra<<Rs, Rq 128 MOVW.NE $0, Rs 129 MULAL.NE Rq, Ra, (Rq,Rs) 133 MULLU Rq, Rr, (Rq,Rs) // q = (r * q) >> 32 147 DIVUHW Rq, Rr, Rs 148 MUL Rs, Rq, R [all...] |
/device/linaro/bootloader/edk2/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/ |
PcRtc.h | 90 UINT8 Rs : 4; // Rate Selection Bits
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/external/llvm/lib/Target/Hexagon/ |
HexagonAsmPrinter.cpp | 365 MCOperand &Rs = Inst.getOperand(1); 366 assert (Rs.isReg() && "Expected register and none was found"); 367 unsigned Reg = RI->getEncodingValue(Rs.getReg()); 372 Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI)); 435 // if ("#u5==0") Assembler mapped to: "Rd=Rs"; else Rd=asr(Rs,#u5-1):rnd 498 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
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HexagonSplitDouble.cpp | 81 void collectIndRegsForLoop(const MachineLoop *L, USet &Rs); 122 const USet &Rs = I.second; 123 if (Rs.find(Reg) != Rs.end()) 431 USet &Rs) { 514 Rs.insert(DP.begin(), End); 515 Rs.insert(CmpR1); 516 Rs.insert(CmpR2); 520 dump_partition(dbgs(), Rs, *TRI); 537 USet Rs; [all...] |
RDFGraph.cpp | [all...] |
/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
HexagonMCCompound.cpp | 113 // P0 = cmp.eq(Rs,#u2) 125 // Rd = Rs 166 // Rd=Rs ; jump #r9:2 207 MCOperand Rs, Rt; 229 Rs = L.getOperand(1); 235 CompoundInsn->addOperand(Rs); 242 Rs = L.getOperand(1); 248 CompoundInsn->addOperand(Rs); 255 Rs = L.getOperand(1); 261 CompoundInsn->addOperand(Rs); [all...] |
/external/mesa3d/src/mesa/swrast/ |
s_blend.c | 480 const GLfloat Rs = rgba[i][RCOMP]; 554 sR = Rs; 559 sR = 1.0F - Rs; 632 dR = Rs; 637 dR = 1.0F - Rs; 740 r = Rs * sR + Rd * dR; 746 r = Rs * sR - Rd * dR; 752 r = Rd * dR - Rs * sR; 758 r = MIN2( Rd, Rs ); 763 r = MAX2( Rd, Rs ); [all...] |
/frameworks/av/media/libstagefright/codecs/m4v_h263/enc/src/ |
rate_control.h | 36 Int Rs; /*bit rate for the sequence (or segment) e.g., 24000 bits/sec */
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/external/capstone/arch/Mips/ |
MipsDisassembler.c | 532 // BOVC if rs >= rt 533 // BEQZALC if rs == 0 && rt != 0 534 // BEQC if rs < rt && rs != 0 536 uint32_t Rs = fieldFromInstruction(insn, 21, 5); 541 if (Rs >= Rt) { 544 } else if (Rs != 0 && Rs < Rt) { 551 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); 568 // BNVC if rs >= r [all...] |
/external/llvm/lib/Target/AArch64/Disassembler/ |
AArch64Disassembler.cpp | [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
ARMMCCodeEmitter.cpp | [all...] |
/system/core/libpixelflinger/codeflinger/ |
GGLAssembler.cpp | 390 int Rs = scratches.obtain(); 392 CONTEXT_LOAD(Rs, state.buffers.color.stride); 394 SMLABB(AL, Rs, Ry, Rs, Rx); // Rs = Rx + Ry*Rs 395 base_offset(parts.cbPtr, parts.cbPtr, Rs); 396 scratches.recycle(Rs); 426 int Rs = dzdx; 428 CONTEXT_LOAD(Rs, state.buffers.depth.stride) [all...] |
/external/capstone/arch/AArch64/ |
AArch64Disassembler.c | [all...] |
/external/llvm/lib/Target/Mips/Disassembler/ |
MipsDisassembler.cpp | 598 // BOVC if rs >= rt 599 // BEQZALC if rs == 0 && rt != 0 600 // BEQC if rs < rt && rs != 0 602 InsnType Rs = fieldFromInstruction(insn, 21, 5); 607 if (Rs >= Rt) { 610 } else if (Rs != 0 && Rs < Rt) { 618 Rs))); 632 InsnType Rs = fieldFromInstruction(insn, 16, 5) [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
ARMCodeEmitter.cpp | [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
ARMMCCodeEmitter.cpp | [all...] |
/system/core/libpixelflinger/tests/arch-arm64/assembler/ |
arm64_assembler_test.cpp | 414 uint32_t Rn = 1, uint32_t Rm = 2, uint32_t Rs = 3) 429 regs[Rs] = test.RsValue; 455 case INSTR_MUL: a64asm->MUL(test.cond, test.setFlags, Rd,Rm,Rs); break; 456 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break; 460 case INSTR_SMULBB:a64asm->SMULBB(test.cond, Rd,Rm,Rs); break; 461 case INSTR_SMULBT:a64asm->SMULBT(test.cond, Rd,Rm,Rs); break; 462 case INSTR_SMULTB:a64asm->SMULTB(test.cond, Rd,Rm,Rs); break; 463 case INSTR_SMULTT:a64asm->SMULTT(test.cond, Rd,Rm,Rs); break; 464 case INSTR_SMULWB:a64asm->SMULWB(test.cond, Rd,Rm,Rs); break; 465 case INSTR_SMULWT:a64asm->SMULWT(test.cond, Rd,Rm,Rs); break [all...] |
/external/capstone/arch/ARM/ |
ARMDisassembler.c | [all...] |
/external/llvm/lib/Analysis/ |
ScalarEvolution.cpp | 802 SmallVector<const SCEV *, 2> Qs, Rs; 814 Rs.push_back(R); 819 Remainder = Rs[0]; 824 Remainder = SE.getAddExpr(Rs); [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
ARMDisassembler.cpp | [all...] |
/external/swiftshader/third_party/subzero/src/ |
IceAssemblerMIPS32.cpp | 209 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); 212 Opcode |= Rs << 21; 222 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); 224 Opcode |= Rs << 21; 237 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); 248 Opcode |= Rs << 21; 259 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName) [all...] |
/external/vixl/src/aarch64/ |
assembler-aarch64.h | 857 void ror(const Register& rd, const Register& rs, unsigned shift) { 858 extr(rd, rs, rs, shift); [all...] |
/external/llvm/lib/Target/ARM/Disassembler/ |
ARMDisassembler.cpp | [all...] |
/external/llvm/lib/Target/Hexagon/AsmParser/ |
HexagonAsmParser.cpp | [all...] |