/prebuilts/go/darwin-x86/src/crypto/rc4/ |
rc4_arm.s | 19 #define Rt R11 38 MOVBU Ri<<2(Rstate), Rt 39 ADD Rt, Rj 45 MOVB Rt, Rj<<2(Rstate) 48 ADD Rt2, Rt 49 AND $0xff, Rt 50 MOVBU Rt<<2(Rstate), Rt 52 EOR Rt, Rt2
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/prebuilts/go/linux-x86/src/crypto/rc4/ |
rc4_arm.s | 19 #define Rt R11 38 MOVBU Ri<<2(Rstate), Rt 39 ADD Rt, Rj 45 MOVB Rt, Rj<<2(Rstate) 48 ADD Rt2, Rt 49 AND $0xff, Rt 50 MOVBU Rt<<2(Rstate), Rt 52 EOR Rt, Rt2
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/external/eigen/Eigen/src/Geometry/ |
Umeyama.h | 134 TransformationMatrixType Rt = TransformationMatrixType::Identity(m+1,m+1); 143 Rt.block(0,0,m,m).noalias() = svd.matrixU() * S.asDiagonal() * svd.matrixV().transpose(); 151 Rt.col(m).head(m) = dst_mean; 152 Rt.col(m).head(m).noalias() -= c*Rt.topLeftCorner(m,m)*src_mean; 153 Rt.block(0,0,m,m) *= c; 157 Rt.col(m).head(m) = dst_mean; 158 Rt.col(m).head(m).noalias() -= Rt.topLeftCorner(m,m)*src_mean; 161 return Rt; [all...] |
/packages/apps/Gallery2/jni/filters/ |
saturated.c | 30 float Rt = Rf * MS; 43 float Rc = R * (Rt + S) + G * Gt + B * Bt; 44 float Gc = R * Rt + G * (Gt + S) + B * Bt; 45 float Bc = R * Rt + G * Gt + B * (Bt + S);
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vibrance.c | 32 float Rt = Rf * MS; 45 Rt = Rf * MS; 52 float Rc = R * (Rt + S) + G * Gt + B * Bt; 53 float Gc = R * Rt + G * (Gt + S) + B * Bt; 54 float Bc = R * Rt + G * Gt + B * (Bt + S);
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/external/llvm/lib/Target/Hexagon/ |
HexagonAsmPrinter.cpp | 326 // Vector reduce complex multiply by scalar, Rt & 1 map to :hi else :lo 330 MCOperand &Rt = Inst.getOperand(3); 331 assert (Rt.isReg() && "Expected register and none was found"); 332 unsigned Reg = RI->getEncodingValue(Rt.getReg()); 337 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); 341 MCOperand &Rt = Inst.getOperand(2); 342 assert (Rt.isReg() && "Expected register and none was found"); 343 unsigned Reg = RI->getEncodingValue(Rt.getReg()); 348 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)) [all...] |
/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
HexagonMCCompound.cpp | 207 MCOperand Rs, Rt; 217 Rt = L.getOperand(0); 222 CompoundInsn->addOperand(Rt); 228 Rt = L.getOperand(0); 234 CompoundInsn->addOperand(Rt); 243 Rt = L.getOperand(2); 249 CompoundInsn->addOperand(Rt); 256 Rt = L.getOperand(2); 262 CompoundInsn->addOperand(Rt); 269 Rt = L.getOperand(2) [all...] |
/device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/ |
ThumbDisassembler.c | 149 { "LDR" , 0x6800, 0xf800, LOAD_STORE_FORMAT1 }, // LDR <Rt>, [<Rn> {,#<imm>}]
150 { "LDR" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
152 { "LDR" , 0x9800, 0xf800, LOAD_STORE_FORMAT4 }, // LDR <Rt>, [SP, #<imm>]
154 { "LDRB" , 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
157 { "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
187 { "STR" , 0x6000, 0xf800, LOAD_STORE_FORMAT1 }, // STR <Rt>, [<Rn> {,#<imm>}]
188 { "STR" , 0x5000, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
189 { "STR" , 0x9000, 0xf800, LOAD_STORE_FORMAT4 }, // STR <Rt>, [SP, #<imm>]
190 { "STRB" , 0x7000, 0xf800, LOAD_STORE_FORMAT1_B }, // STRB <Rt>, [<Rn>, #<imm5>]
191 { "STRB" , 0x5400, 0xfe00, LOAD_STORE_FORMAT2 }, // STRB <Rt>, [<Rn>, <Rm>] [all...] |
/external/capstone/arch/Mips/ |
MipsDisassembler.c | 532 // BOVC if rs >= rt 533 // BEQZALC if rs == 0 && rt != 0 534 // BEQC if rs < rt && rs != 0 537 uint32_t Rt = fieldFromInstruction(insn, 16, 5); 541 if (Rs >= Rt) { 544 } else if (Rs != 0 && Rs < Rt) { 553 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); 568 // BNVC if rs >= rt 569 // BNEZALC if rs == 0 && rt != 0 570 // BNEC if rs < rt && rs != [all...] |
/external/llvm/lib/Target/AArch64/Disassembler/ |
AArch64Disassembler.cpp | [all...] |
/external/llvm/lib/Target/ARM/ |
Thumb2SizeReduction.cpp | 437 unsigned Rt = MI->getOperand(IsStore ? 1 : 0).getReg(); 442 assert(isARMLowRegister(Rt)); 455 .addReg(Rt, IsStore ? 0 : RegState::Define); [all...] |
ARMBaseInstrInfo.cpp | [all...] |
/cts/tests/sensor/src/android/hardware/cts/ |
SensorManagerStaticTest.java | 271 float [] Rt; 275 Rt = mat9T(mat9VRot(rotv)); // from world frame to phone frame 276 //Rt = mat9I(); 283 float [] gmb = mat9Mul(Rt, gm); // do not care about right most column 290 float [] n = mat9Mul(Rr, Rt); 294 i, mat9ToStr(mat9T(Rt)), mat9ToStr(Rr)),
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/external/capstone/arch/AArch64/ |
AArch64Disassembler.c | 943 unsigned Rt = fieldFromInstruction(insn, 0, 5); 951 // Rt is an immediate in prefetch. 952 MCOperand_CreateImm0(Inst, Rt); 962 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 969 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 973 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 977 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 981 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 985 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 989 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder) [all...] |
/external/llvm/lib/Target/Mips/Disassembler/ |
MipsDisassembler.cpp | 598 // BOVC if rs >= rt 599 // BEQZALC if rs == 0 && rt != 0 600 // BEQC if rs < rt && rs != 0 603 InsnType Rt = fieldFromInstruction(insn, 16, 5); 607 if (Rs >= Rt) { 610 } else if (Rs != 0 && Rs < Rt) { 621 Rt))); 631 InsnType Rt = fieldFromInstruction(insn, 21, 5); 635 if (Rs >= Rt) { 638 Rt))); [all...] |
/external/pdfium/third_party/lcms/src/ |
cmspcs.c | 500 deltaC,deltah,dc,t,g,dh,rh,rc,rt,bfd; local 539 rt = rh*rc; 541 bfd = sqrt(Sqr(deltaL)+Sqr(deltaC/dc)+Sqr(deltah/dh)+(rt*(deltaC/dc)*(deltah/dh))); 647 cmsFloat64Number Rt = -sin(2 * RADIANS(delta_ro)) * Rc; 652 Rt*(delta_C/(Sc * Kc)) * (delta_H / (Sh * Kh)));
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/external/v8/src/arm/ |
disasm-arm.cc | 280 Print("call rt redirected"); 321 } else if (format[1] == 't') { // 'rt: Rt register 766 Format(instr, "ldrex'cond 'rt, ['rn]"); 769 Format(instr, "ldrexb'cond 'rt, ['rn]"); 772 Format(instr, "ldrexh'cond 'rt, ['rn]"); 780 // The instruction is documented as strex rd, rt, [rn], but the 781 // "rt" register is using the rm bits. 1549 int rt = instr->RtValue(); local 1586 int rt = instr->RtValue(); local [all...] |
/external/capstone/arch/ARM/ |
ARMDisassembler.c | [all...] |
/external/spirv-llvm/lib/SPIRV/ |
SPIRVInternal.h | 341 const static char Rt[] = "rt"; [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
ARMDisassembler.cpp | [all...] |
/external/swiftshader/third_party/subzero/src/ |
IceAssemblerMIPS32.cpp | 210 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); 213 Opcode |= Rt << 16; 221 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); 225 Opcode |= Rt << 16; 236 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); 249 Opcode |= Rt << 16; 272 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName) [all...] |
/external/vixl/src/aarch64/ |
assembler-aarch64.h | 513 void cbz(const Register& rt, Label* label); 516 void cbz(const Register& rt, int64_t imm19); 519 void cbnz(const Register& rt, Label* label); 522 void cbnz(const Register& rt, int64_t imm19); 573 void tbz(const Register& rt, unsigned bit_pos, Label* label); 576 void tbz(const Register& rt, unsigned bit_pos, int64_t imm14); 579 void tbnz(const Register& rt, unsigned bit_pos, Label* label); 582 void tbnz(const Register& rt, unsigned bit_pos, int64_t imm14); [all...] |
/external/llvm/lib/Target/ARM/Disassembler/ |
ARMDisassembler.cpp | [all...] |
/external/llvm/lib/Target/Hexagon/AsmParser/ |
HexagonAsmParser.cpp | [all...] |
/external/llvm/lib/Target/AArch64/AsmParser/ |
AArch64AsmParser.cpp | [all...] |