1 /* 2 * Copyright 2014 Broadcom 3 * Copyright (C) 2012 Rob Clark <robclark (at) freedesktop.org> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 22 * IN THE SOFTWARE. 23 */ 24 25 #ifndef VC4_CONTEXT_H 26 #define VC4_CONTEXT_H 27 28 #include <stdio.h> 29 30 #include "pipe/p_context.h" 31 #include "pipe/p_state.h" 32 #include "util/slab.h" 33 #include "xf86drm.h" 34 35 #define __user 36 #include "vc4_drm.h" 37 #include "vc4_bufmgr.h" 38 #include "vc4_resource.h" 39 #include "vc4_cl.h" 40 #include "vc4_qir.h" 41 42 #ifndef DRM_VC4_PARAM_SUPPORTS_ETC1 43 #define DRM_VC4_PARAM_SUPPORTS_ETC1 4 44 #endif 45 #ifndef DRM_VC4_PARAM_SUPPORTS_THREADED_FS 46 #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5 47 #endif 48 49 #ifdef USE_VC4_SIMULATOR 50 #define using_vc4_simulator true 51 #else 52 #define using_vc4_simulator false 53 #endif 54 55 #define VC4_DIRTY_BLEND (1 << 0) 56 #define VC4_DIRTY_RASTERIZER (1 << 1) 57 #define VC4_DIRTY_ZSA (1 << 2) 58 #define VC4_DIRTY_FRAGTEX (1 << 3) 59 #define VC4_DIRTY_VERTTEX (1 << 4) 60 61 #define VC4_DIRTY_BLEND_COLOR (1 << 7) 62 #define VC4_DIRTY_STENCIL_REF (1 << 8) 63 #define VC4_DIRTY_SAMPLE_MASK (1 << 9) 64 #define VC4_DIRTY_FRAMEBUFFER (1 << 10) 65 #define VC4_DIRTY_STIPPLE (1 << 11) 66 #define VC4_DIRTY_VIEWPORT (1 << 12) 67 #define VC4_DIRTY_CONSTBUF (1 << 13) 68 #define VC4_DIRTY_VTXSTATE (1 << 14) 69 #define VC4_DIRTY_VTXBUF (1 << 15) 70 #define VC4_DIRTY_INDEXBUF (1 << 16) 71 #define VC4_DIRTY_SCISSOR (1 << 17) 72 #define VC4_DIRTY_FLAT_SHADE_FLAGS (1 << 18) 73 #define VC4_DIRTY_PRIM_MODE (1 << 19) 74 #define VC4_DIRTY_CLIP (1 << 20) 75 #define VC4_DIRTY_UNCOMPILED_VS (1 << 21) 76 #define VC4_DIRTY_UNCOMPILED_FS (1 << 22) 77 #define VC4_DIRTY_COMPILED_CS (1 << 23) 78 #define VC4_DIRTY_COMPILED_VS (1 << 24) 79 #define VC4_DIRTY_COMPILED_FS (1 << 25) 80 #define VC4_DIRTY_FS_INPUTS (1 << 26) 81 82 struct vc4_sampler_view { 83 struct pipe_sampler_view base; 84 uint32_t texture_p0; 85 uint32_t texture_p1; 86 bool force_first_level; 87 }; 88 89 struct vc4_sampler_state { 90 struct pipe_sampler_state base; 91 uint32_t texture_p1; 92 }; 93 94 struct vc4_texture_stateobj { 95 struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS]; 96 unsigned num_textures; 97 struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS]; 98 unsigned num_samplers; 99 }; 100 101 struct vc4_shader_uniform_info { 102 enum quniform_contents *contents; 103 uint32_t *data; 104 uint32_t count; 105 uint32_t num_texture_samples; 106 }; 107 108 struct vc4_uncompiled_shader { 109 /** A name for this program, so you can track it in shader-db output. */ 110 uint32_t program_id; 111 /** How many variants of this program were compiled, for shader-db. */ 112 uint32_t compiled_variant_count; 113 struct pipe_shader_state base; 114 }; 115 116 struct vc4_ubo_range { 117 /** 118 * offset in bytes from the start of the ubo where this range is 119 * uploaded. 120 * 121 * Only set once used is set. 122 */ 123 uint32_t dst_offset; 124 125 /** 126 * offset in bytes from the start of the gallium uniforms where the 127 * data comes from. 128 */ 129 uint32_t src_offset; 130 131 /** size in bytes of this ubo range */ 132 uint32_t size; 133 }; 134 135 struct vc4_fs_inputs { 136 /** 137 * Array of the meanings of the VPM inputs this shader needs. 138 * 139 * It doesn't include those that aren't part of the VPM, like 140 * point/line coordinates. 141 */ 142 struct vc4_varying_slot *input_slots; 143 uint32_t num_inputs; 144 }; 145 146 struct vc4_compiled_shader { 147 uint64_t program_id; 148 struct vc4_bo *bo; 149 150 struct vc4_shader_uniform_info uniforms; 151 152 struct vc4_ubo_range *ubo_ranges; 153 uint32_t num_ubo_ranges; 154 uint32_t ubo_size; 155 /** 156 * VC4_DIRTY_* flags that, when set in vc4->dirty, mean that the 157 * uniforms have to be rewritten (and therefore the shader state 158 * reemitted). 159 */ 160 uint32_t uniform_dirty_bits; 161 162 /** bitmask of which inputs are color inputs, for flat shade handling. */ 163 uint32_t color_inputs; 164 165 bool disable_early_z; 166 167 /* Set if the compile failed, likely due to register allocation 168 * failure. In this case, we have no shader to run and should not try 169 * to do any draws. 170 */ 171 bool failed; 172 173 bool fs_threaded; 174 175 uint8_t num_inputs; 176 177 /* Byte offsets for the start of the vertex attributes 0-7, and the 178 * total size as "attribute" 8. 179 */ 180 uint8_t vattr_offsets[9]; 181 uint8_t vattrs_live; 182 183 const struct vc4_fs_inputs *fs_inputs; 184 }; 185 186 struct vc4_program_stateobj { 187 struct vc4_uncompiled_shader *bind_vs, *bind_fs; 188 struct vc4_compiled_shader *cs, *vs, *fs; 189 }; 190 191 struct vc4_constbuf_stateobj { 192 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS]; 193 uint32_t enabled_mask; 194 uint32_t dirty_mask; 195 }; 196 197 struct vc4_vertexbuf_stateobj { 198 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS]; 199 unsigned count; 200 uint32_t enabled_mask; 201 uint32_t dirty_mask; 202 }; 203 204 struct vc4_vertex_stateobj { 205 struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS]; 206 unsigned num_elements; 207 }; 208 209 /* Hash table key for vc4->jobs */ 210 struct vc4_job_key { 211 struct pipe_surface *cbuf; 212 struct pipe_surface *zsbuf; 213 }; 214 215 /** 216 * A complete bin/render job. 217 * 218 * This is all of the state necessary to submit a bin/render to the kernel. 219 * We want to be able to have multiple in progress at a time, so that we don't 220 * need to flush an existing CL just to switch to rendering to a new render 221 * target (which would mean reading back from the old render target when 222 * starting to render to it again). 223 */ 224 struct vc4_job { 225 struct vc4_cl bcl; 226 struct vc4_cl shader_rec; 227 struct vc4_cl uniforms; 228 struct vc4_cl bo_handles; 229 struct vc4_cl bo_pointers; 230 uint32_t shader_rec_count; 231 /** 232 * Amount of memory used by the BOs in bo_pointers. 233 * 234 * Used for checking when we should flush the job early so we don't 235 * OOM. 236 */ 237 uint32_t bo_space; 238 239 /** @{ Surfaces to submit rendering for. */ 240 struct pipe_surface *color_read; 241 struct pipe_surface *color_write; 242 struct pipe_surface *zs_read; 243 struct pipe_surface *zs_write; 244 struct pipe_surface *msaa_color_write; 245 struct pipe_surface *msaa_zs_write; 246 /** @} */ 247 /** @{ 248 * Bounding box of the scissor across all queued drawing. 249 * 250 * Note that the max values are exclusive. 251 */ 252 uint32_t draw_min_x; 253 uint32_t draw_min_y; 254 uint32_t draw_max_x; 255 uint32_t draw_max_y; 256 /** @} */ 257 /** @{ 258 * Width/height of the color framebuffer being rendered to, 259 * for VC4_TILE_RENDERING_MODE_CONFIG. 260 */ 261 uint32_t draw_width; 262 uint32_t draw_height; 263 /** @} */ 264 /** @{ Tile information, depending on MSAA and float color buffer. */ 265 uint32_t draw_tiles_x; /** @< Number of tiles wide for framebuffer. */ 266 uint32_t draw_tiles_y; /** @< Number of tiles high for framebuffer. */ 267 268 uint32_t tile_width; /** @< Width of a tile. */ 269 uint32_t tile_height; /** @< Height of a tile. */ 270 /** Whether the current rendering is in a 4X MSAA tile buffer. */ 271 bool msaa; 272 /** @} */ 273 274 /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the 275 * first rendering. 276 */ 277 uint32_t cleared; 278 /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to 279 * (either clears or draws). 280 */ 281 uint32_t resolve; 282 uint32_t clear_color[2]; 283 uint32_t clear_depth; /**< 24-bit unorm depth */ 284 uint8_t clear_stencil; 285 286 /** 287 * Set if some drawing (triangles, blits, or just a glClear()) has 288 * been done to the FBO, meaning that we need to 289 * DRM_IOCTL_VC4_SUBMIT_CL. 290 */ 291 bool needs_flush; 292 293 /** 294 * Number of draw calls (not counting full buffer clears) queued in 295 * the current job. 296 */ 297 uint32_t draw_calls_queued; 298 299 struct vc4_job_key key; 300 }; 301 302 struct vc4_context { 303 struct pipe_context base; 304 305 int fd; 306 struct vc4_screen *screen; 307 308 /** The 3D rendering job for the currently bound FBO. */ 309 struct vc4_job *job; 310 311 /* Map from struct vc4_job_key to the job for that FBO. 312 */ 313 struct hash_table *jobs; 314 315 /** 316 * Map from vc4_resource to a job writing to that resource. 317 * 318 * Primarily for flushing jobs rendering to textures that are now 319 * being read from. 320 */ 321 struct hash_table *write_jobs; 322 323 struct slab_child_pool transfer_pool; 324 struct blitter_context *blitter; 325 326 /** bitfield of VC4_DIRTY_* */ 327 uint32_t dirty; 328 329 struct primconvert_context *primconvert; 330 331 struct hash_table *fs_cache, *vs_cache; 332 struct set *fs_inputs_set; 333 uint32_t next_uncompiled_program_id; 334 uint64_t next_compiled_program_id; 335 336 struct ra_regs *regs; 337 unsigned int reg_class_any[2]; 338 unsigned int reg_class_a_or_b[2]; 339 unsigned int reg_class_a_or_b_or_acc[2]; 340 unsigned int reg_class_r0_r3; 341 unsigned int reg_class_r4_or_a[2]; 342 unsigned int reg_class_a[2]; 343 344 uint8_t prim_mode; 345 346 /** Maximum index buffer valid for the current shader_rec. */ 347 uint32_t max_index; 348 /** Last index bias baked into the current shader_rec. */ 349 uint32_t last_index_bias; 350 351 /** Seqno of the last CL flush's job. */ 352 uint64_t last_emit_seqno; 353 354 struct u_upload_mgr *uploader; 355 356 /** @{ Current pipeline state objects */ 357 struct pipe_scissor_state scissor; 358 struct pipe_blend_state *blend; 359 struct vc4_rasterizer_state *rasterizer; 360 struct vc4_depth_stencil_alpha_state *zsa; 361 362 struct vc4_texture_stateobj verttex, fragtex; 363 364 struct vc4_program_stateobj prog; 365 366 struct vc4_vertex_stateobj *vtx; 367 368 struct { 369 struct pipe_blend_color f; 370 uint8_t ub[4]; 371 } blend_color; 372 struct pipe_stencil_ref stencil_ref; 373 unsigned sample_mask; 374 struct pipe_framebuffer_state framebuffer; 375 struct pipe_poly_stipple stipple; 376 struct pipe_clip_state clip; 377 struct pipe_viewport_state viewport; 378 struct vc4_constbuf_stateobj constbuf[PIPE_SHADER_TYPES]; 379 struct vc4_vertexbuf_stateobj vertexbuf; 380 struct pipe_index_buffer indexbuf; 381 /** @} */ 382 }; 383 384 struct vc4_rasterizer_state { 385 struct pipe_rasterizer_state base; 386 387 /* VC4_CONFIGURATION_BITS */ 388 uint8_t config_bits[3]; 389 390 float point_size; 391 392 /** 393 * Half-float (1/8/7 bits) value of polygon offset units for 394 * VC4_PACKET_DEPTH_OFFSET 395 */ 396 uint16_t offset_units; 397 /** 398 * Half-float (1/8/7 bits) value of polygon offset scale for 399 * VC4_PACKET_DEPTH_OFFSET 400 */ 401 uint16_t offset_factor; 402 }; 403 404 struct vc4_depth_stencil_alpha_state { 405 struct pipe_depth_stencil_alpha_state base; 406 407 /* VC4_CONFIGURATION_BITS */ 408 uint8_t config_bits[3]; 409 410 /** Uniforms for stencil state. 411 * 412 * Index 0 is either the front config, or the front-and-back config. 413 * Index 1 is the back config if doing separate back stencil. 414 * Index 2 is the writemask config if it's not a common mask value. 415 */ 416 uint32_t stencil_uniforms[3]; 417 }; 418 419 #define perf_debug(...) do { \ 420 if (unlikely(vc4_debug & VC4_DEBUG_PERF)) \ 421 fprintf(stderr, __VA_ARGS__); \ 422 } while (0) 423 424 static inline struct vc4_context * 425 vc4_context(struct pipe_context *pcontext) 426 { 427 return (struct vc4_context *)pcontext; 428 } 429 430 static inline struct vc4_sampler_view * 431 vc4_sampler_view(struct pipe_sampler_view *psview) 432 { 433 return (struct vc4_sampler_view *)psview; 434 } 435 436 static inline struct vc4_sampler_state * 437 vc4_sampler_state(struct pipe_sampler_state *psampler) 438 { 439 return (struct vc4_sampler_state *)psampler; 440 } 441 442 struct pipe_context *vc4_context_create(struct pipe_screen *pscreen, 443 void *priv, unsigned flags); 444 void vc4_draw_init(struct pipe_context *pctx); 445 void vc4_state_init(struct pipe_context *pctx); 446 void vc4_program_init(struct pipe_context *pctx); 447 void vc4_program_fini(struct pipe_context *pctx); 448 void vc4_query_init(struct pipe_context *pctx); 449 void vc4_simulator_init(struct vc4_screen *screen); 450 void vc4_simulator_destroy(struct vc4_screen *screen); 451 int vc4_simulator_flush(struct vc4_context *vc4, 452 struct drm_vc4_submit_cl *args, 453 struct vc4_job *job); 454 int vc4_simulator_ioctl(int fd, unsigned long request, void *arg); 455 void vc4_simulator_open_from_handle(int fd, uint32_t winsys_stride, 456 int handle, uint32_t size); 457 458 static inline int 459 vc4_ioctl(int fd, unsigned long request, void *arg) 460 { 461 if (using_vc4_simulator) 462 return vc4_simulator_ioctl(fd, request, arg); 463 else 464 return drmIoctl(fd, request, arg); 465 } 466 467 void vc4_set_shader_uniform_dirty_flags(struct vc4_compiled_shader *shader); 468 void vc4_write_uniforms(struct vc4_context *vc4, 469 struct vc4_compiled_shader *shader, 470 struct vc4_constbuf_stateobj *cb, 471 struct vc4_texture_stateobj *texstate); 472 473 void vc4_flush(struct pipe_context *pctx); 474 void vc4_job_init(struct vc4_context *vc4); 475 struct vc4_job *vc4_get_job(struct vc4_context *vc4, 476 struct pipe_surface *cbuf, 477 struct pipe_surface *zsbuf); 478 struct vc4_job *vc4_get_job_for_fbo(struct vc4_context *vc4); 479 480 void vc4_job_submit(struct vc4_context *vc4, struct vc4_job *job); 481 void vc4_flush_jobs_writing_resource(struct vc4_context *vc4, 482 struct pipe_resource *prsc); 483 void vc4_flush_jobs_reading_resource(struct vc4_context *vc4, 484 struct pipe_resource *prsc); 485 void vc4_emit_state(struct pipe_context *pctx); 486 void vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c); 487 struct qpu_reg *vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c); 488 bool vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode); 489 490 bool vc4_rt_format_supported(enum pipe_format f); 491 bool vc4_rt_format_is_565(enum pipe_format f); 492 bool vc4_tex_format_supported(enum pipe_format f); 493 uint8_t vc4_get_tex_format(enum pipe_format f); 494 const uint8_t *vc4_get_format_swizzle(enum pipe_format f); 495 void vc4_init_query_functions(struct vc4_context *vc4); 496 void vc4_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info); 497 void vc4_blitter_save(struct vc4_context *vc4); 498 #endif /* VC4_CONTEXT_H */ 499
